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21. 发明授权

US07265019B2 Elastomeric CMOS based micro electromechanical varactor 有权
标题翻译：弹性体CMOS微机电变容二极管
公开(公告)号：US07265019B2
公开(公告)日：2007-09-04
申请号：US10710286
申请日：2004-06-30
申请人： Anil K. Chinthakindi , Henri D. Schnurmann
发明人： Anil K. Chinthakindi , Henri D. Schnurmann
IPC分类号： H01L21/20 , H01L21/4763
CPC分类号： H01G5/18 , H01G5/38
摘要： A micro electro-mechanical system (MEMS) variable capacitor is described, wherein movable comb electrodes of opposing polarity are fabricated simultaneously on the same substrate and are independently actuated. The electrodes are formed in an interdigitated fashion to maximize capacitance. The MEMS variable capacitor includes CMOS manufacturing steps in combination with elastomeric material selectively used in areas under greatest stress to ensure that the varactor will not fail as a result of stresses that may result in the separation of dielectric material from the conductive elements. The combination of a CMOS process with the conducting elastomeric material between vias increases the overall sidewall area, which provides increased capacitance density.
摘要翻译：描述了微机电系统（MEMS）可变电容器，其中相同极性的可移动梳状电极同时制造在相同的衬底上并且被独立地致动。电极以交叉形式形成以最大化电容。 MEMS可变电容器包括与在最大应力区域选择性地使用的弹性体材料组合的CMOS制造步骤，以确保变容二极管不会由于可能导致介电材料与导电元件分离的应力而失效。 CMOS工艺与通孔之间的导电弹性体材料的组合增加了整个侧壁面积，这提供了增加的电容密度。

22. 发明授权

US07166913B2 Heat dissipation for heat generating element of semiconductor device and related method 有权
标题翻译：半导体器件发热元件的散热及相关方法
公开(公告)号：US07166913B2
公开(公告)日：2007-01-23
申请号：US10907873
申请日：2005-04-19
申请人： Anil K. Chinthakindi , Lawrence A. Clevenger , Tom C. Lee , Gerald Matusiewicz , Conal E. Murray , Chih-Chao Yang
发明人： Anil K. Chinthakindi , Lawrence A. Clevenger , Tom C. Lee , Gerald Matusiewicz , Conal E. Murray , Chih-Chao Yang
IPC分类号： H01L23/34
CPC分类号： H01L23/5228 , H01L23/3677 , H01L2924/0002 , H01L2924/00
摘要： A structure and method are disclosed for heat dissipation relative to a heat generating element in a semiconductor device. The structure includes a plurality of heat transmitting lines partially vertically coincidental with the heat generating element, and at least one interconnecting path from each heat transmitting line to a substrate of the semiconductor device. In one embodiment, the heat generating element includes a resistor in a non-first metal level. The invention is compatible with conventional BEOL interconnect schemes, minimizes the amount of heat transfer from the resistor to the surrounding interconnect wiring, thus eliminating the loss of current carrying capability in the wiring.
摘要翻译：公开了相对于半导体器件中的发热元件的散热的结构和方法。该结构包括多个与发热元件垂直一致的传热线，以及从每个传热线到半导体器件的基板的至少一个互连路径。在一个实施例中，发热元件包括非第一金属水平的电阻器。本发明与传统的BEOL互连方案兼容，使得从电阻器到周围互连布线的传热量最小化，从而消除了布线中的载流能力的损失。

23. 发明授权

US06906905B1 Micro electro-mechanical variable capacitor 失效
标题翻译：微机电可变电容器
公开(公告)号：US06906905B1
公开(公告)日：2005-06-14
申请号：US10710283
申请日：2004-06-30
申请人： Anil K. Chinthakindi
发明人： Anil K. Chinthakindi
IPC分类号： H01G5/00 , H01G5/18
CPC分类号： H01G5/18
摘要： A three-dimensional micro electro-mechanical (MEMS) variable capacitor is described wherein movable comb electrodes of opposing polarity are fabricated simultaneously on the same substrate are independently actuated. These electrodes are formed in an interdigitated fashion to maximize the capacitance of the device. The electrodes are jointly or individually actuated. A separate actuation electrode and a ground plane electrode actuate the movable electrodes. The voltage potential between the two electrodes provides a primary mode of operation of the device. The variation of the sidewall overlap area between the interdigitated fingers provides the expected capacitance tuning of the device. The interdigitated electrodes can also be attached on both ends to form fixed-fixed beams. The stiffness of the electrodes is reduced by utilizing thin support structures at the ends of the electrodes. The three dimensional aspect of the device avails large surface area. Large capacitance variation and tuning ranges are obtained by independent actuation of the electrode fingers. A plurality of modes of operation of the device provides wide flexibility and greater performance advantage for the device. Upon fabrication of the device, a separate substrate with etched dielectric is used to encapsulated the device. The MEMS device is then completely encapsulated, requiring no additional packaging of the device. Further, since alignment and bonding can be done on a wafer scale, an improved device yield is obtained at a lower cost.
摘要翻译：描述了三维微机电（MEMS）可变电容器，其中在相同基板上同时制造相反极性的可动梳状电极被独立地致动。这些电极以交错方式形成，以使器件的电容最大化。电极共同或单独致动。单独的致动电极和接地平面电极致动可动电极。两个电极之间的电压电位提供了器件的主要操作模式。交叉指状物之间的侧壁重叠区域的变化提供了设备的预期电容调谐。交叉电极也可以安装在两端以形成固定的光束。通过在电极的端部利用薄的支撑结构来减小电极的刚度。该装置的三维方面具有较大的表面积。通过电极指的独立致动获得大的电容变化和调谐范围。器件的多种操作模式为器件提供了广泛的灵活性和更大的性能优势。在制造器件时，使用具有蚀刻电介质的单独衬底来封装器件。然后，MEMS器件被完全封装，不需要额外的器件封装。此外，由于可以在晶片规模上进行取向和接合，所以可以以更低的成本获得提高的器件产量。

24. 发明授权

US06661069B1 Micro-electromechanical varactor with enhanced tuning range 有权
标题翻译：具有增强调谐范围的微机电变容二极管
公开(公告)号：US06661069B1
公开(公告)日：2003-12-09
申请号：US10278211
申请日：2002-10-22
申请人： Anil K. Chinthakindi , Robert A. Groves , Kenneth J. Stein , Seshadri Subbanna , Richard P. Volant
发明人： Anil K. Chinthakindi , Robert A. Groves , Kenneth J. Stein , Seshadri Subbanna , Richard P. Volant
IPC分类号： H01L2986
CPC分类号： H01G5/18 , B81B2201/01 , H01G5/011 , Y10S257/924
摘要： A three-dimensional micro- electromechanical (MEM) varactor is described wherein a movable beam and fixed electrode are respectively fabricated on separate substrates coupled to each other. The movable beam with comb-drive electrodes are fabricated on the “chip side” while the fixed bottom electrode is fabricated on a separated substrate “carrier side”. Upon fabrication of the device on both surfaces of the substrate, the chip side device is diced and “flipped over”, aligned and joined to the “carrier” substrate to form the final device. Comb-drive (fins) electrodes are used for actuation while the motion of the electrode provides changes in capacitance. Due to the constant driving forces involved, a large capacitance tuning range can be obtained. The three dimensional aspect of the device avails large surface area. When large aspect ratio features are provided, a lower actuation voltage can be used. Upon fabrication, the MEMS device is completely encapsulated, requiring no additional packaging of the device. Further, since alignment and bonding can be done on a wafer scale (wafer scale MEMS packaging), an improved device yield can be obtained at a lower cost.
摘要翻译：描述了三维微机电（MEM）变容二极管，其中可移动光束和固定电极分别制造在彼此耦合的分开的基板上。具有梳状驱动电极的可移动光束在“芯片侧”上制造，而固定底部电极制造在分离的基板“载体侧”上。在衬底的两个表面上制造器件时，芯片侧器件被切割并“翻转”，对准并接合到“载体”衬底以形成最终器件。梳状驱动（鳍）电极用于致动，同时电极的运动提供电容的变化。由于所涉及的驱动力恒定，可以获得大的电容调谐范围。该装置的三维方面具有较大的表面积。当提供大的纵横比特征时，可以使用较低的致动电压。在制造时，MEMS器件被完全封装，不需要额外的器件封装。此外，由于可以在晶片规模（晶片级MEMS封装）上进行取向和接合，所以可以以更低的成本获得改进的器件产量。

25. 发明授权

US08487401B2 Methods of fabricating passive element without planarizing and related semiconductor device 有权
标题翻译：无平面化制造无源元件及相关半导体器件的方法
公开(公告)号：US08487401B2
公开(公告)日：2013-07-16
申请号：US13359634
申请日：2012-01-27
申请人： Anil K. Chinthakindi , Timothy J. Dalton , Ebenezer E. Eshun , Jeffrey P. Gambino , Anthony K. Stamper , Kunal Vaed
发明人： Anil K. Chinthakindi , Timothy J. Dalton , Ebenezer E. Eshun , Jeffrey P. Gambino , Anthony K. Stamper , Kunal Vaed
IPC分类号： H01L23/522
CPC分类号： H01L21/76819 , H01L23/522 , H01L28/40 , H01L2924/0002 , H01L2924/00
摘要： Methods of fabricating a passive element and a semiconductor device including the passive element are disclosed including the use of a dummy passive element. A dummy passive element is a passive element or wire which is added to the chip layout to aid in planarization but is not used in the active circuit. One embodiment of the method includes forming the passive element and a dummy passive element adjacent to the passive element; forming a dielectric layer over the passive element and the dummy passive element, wherein the dielectric layer is substantially planar between the passive element and the dummy passive element; and forming in the dielectric layer an interconnect to the passive element through the dielectric layer and a dummy interconnect portion overlapping at least a portion of the dummy passive element. The methods eliminate the need for planarizing.
摘要翻译：公开了制造无源元件的方法和包括无源元件的半导体器件，其包括使用虚拟无源元件。虚拟无源元件是被添加到芯片布局以帮助平坦化但在有源电路中不使用的无源元件或线。该方法的一个实施例包括形成无源元件和邻近无源元件的虚拟无源元件; 在无源元件和虚拟无源元件上形成电介质层，其中介电层在无源元件和虚拟无源元件之间基本上是平面的; 并且在电介质层中形成通过电介质层与无源元件的互连以及与虚拟无源元件的至少一部分重叠的虚拟互连部分。该方法消除了平面化的需要。

26. 发明申请

US20120184081A1 PROCESS FOR SINGLE AND MULTIPLE LEVEL METAL-INSULATOR-METAL INTEGRATION WITH A SINGLE MASK 有权
标题翻译：单层和多层金属绝缘子 - 金属整合与单面蒙皮的工艺
公开(公告)号：US20120184081A1
公开(公告)日：2012-07-19
申请号：US13432440
申请日：2012-03-28
申请人： Anil K. CHINTHAKINDI , Douglas D. COOLBAUGH , Keith E. DOWNES , Ebenezer E. ESHUN , Zhong-Xiang HE , Robert M. RASSEL , Anthony K. STAMPER
发明人： Anil K. CHINTHAKINDI , Douglas D. COOLBAUGH , Keith E. DOWNES , Ebenezer E. ESHUN , Zhong-Xiang HE , Robert M. RASSEL , Anthony K. STAMPER
IPC分类号： H01L21/02
CPC分类号： H01L21/32139 , H01L21/32136 , H01L28/75
摘要： A method of fabricating a MIM capacitor is provided. The method includes providing a substrate including a dielectric layer formed on a first conductive layer and a second conductive layer formed over the dielectric layer, and patterning a mask on the second conductive layer. Exposed portions of the second conductive layer are removed to form an upper plate of a MIM capacitor having edges substantially aligned with respective edges of the mask. The upper plate is undercut so that edges of the upper plate are located under the mask. Exposed portions of the dielectric layer and the first conductive layer are removed using the mask to form a capacitor dielectric layer and a lower plate of the MIM capacitor having edges substantially aligned with respective edges of the mask.
摘要翻译：提供一种制造MIM电容器的方法。该方法包括提供包括形成在第一导电层上的电介质层和形成在电介质层上的第二导电层的衬底，以及在第二导电层上构图掩模。去除第二导电层的暴露部分以形成具有与掩模的相应边缘基本对齐的边缘的MIM电容器的上板。上板被切下，使得上板的边缘位于掩模下方。使用掩模去除电介质层和第一导电层的暴露部分，以形成MIM电容器的电容器电介质层和具有基本上与掩模的各个边缘对准的边缘的MIM电容器的下板。

27. 发明授权

US08207568B2 Process for single and multiple level metal-insulator-metal integration with a single mask 有权
标题翻译：单层和多层金属绝缘体金属与单一掩模集成的工艺
公开(公告)号：US08207568B2
公开(公告)日：2012-06-26
申请号：US11162661
申请日：2005-09-19
申请人： Anil K. Chinthakindi , Douglas D. Coolbaugh , Keith E. Downes , Ebenezer E. Eshun , Zhong-Xiang He , Robert M. Rassel , Anthony K. Stamper
发明人： Anil K. Chinthakindi , Douglas D. Coolbaugh , Keith E. Downes , Ebenezer E. Eshun , Zhong-Xiang He , Robert M. Rassel , Anthony K. Stamper
IPC分类号： H01L29/92
CPC分类号： H01L21/32139 , H01L21/32136 , H01L28/75
摘要： Method of fabricating a MIM capacitor and MIM capacitor. The method includes providing a substrate including a dielectric layer formed on a first conductive layer and a second conductive layer formed over the dielectric layer, and patterning a mask on the second conductive layer. Exposed portions of the second conductive layer are removed to form an upper plate of a MIM capacitor having edges substantially aligned with respective edges of the mask. The upper plate is undercut so that edges of the upper plate are located under the mask. Exposed portions of the dielectric layer and the first conductive layer are removed using the mask to form a capacitor dielectric layer and a lower plate of the MIM capacitor having edges substantially aligned with respective edges of the mask.
摘要翻译：制造MIM电容器和MIM电容器的方法。该方法包括提供包括形成在第一导电层上的电介质层和形成在电介质层上的第二导电层的衬底，以及在第二导电层上构图掩模。去除第二导电层的暴露部分以形成具有与掩模的相应边缘基本对齐的边缘的MIM电容器的上板。上板被切下，使得上板的边缘位于掩模下方。使用掩模去除电介质层和第一导电层的暴露部分，以形成MIM电容器的电容器电介质层和具有基本上与掩模的各个边缘对准的边缘的MIM电容器的下板。

28. 发明授权

US08119491B2 Methods of fabricating passive element without planarizing and related semiconductor device 有权
标题翻译：无平面化制造无源元件及相关半导体器件的方法
公开(公告)号：US08119491B2
公开(公告)日：2012-02-21
申请号：US12106374
申请日：2008-04-21
申请人： Anil K. Chinthakindi , Timothy J. Dalton , Ebenezer E. Eshun , Jeffrey P. Gambino , Anthony K. Stamper , Kunal Vaed
发明人： Anil K. Chinthakindi , Timothy J. Dalton , Ebenezer E. Eshun , Jeffrey P. Gambino , Anthony K. Stamper , Kunal Vaed
IPC分类号： H01L21/20
CPC分类号： H01L21/76819 , H01L23/522 , H01L28/40 , H01L2924/0002 , H01L2924/00
摘要： Methods of fabricating a passive element and a semiconductor device including the passive element are disclosed including the use of a dummy passive element. A dummy passive element is a passive element or wire which is added to the chip layout to aid in planarization but is not used in the active circuit. One embodiment of the method includes forming the passive element and a dummy passive element adjacent to the passive element; forming a dielectric layer over the passive element and the dummy passive element, wherein the dielectric layer is substantially planar between the passive element and the dummy passive element; and forming in the dielectric layer an interconnect to the passive element through the dielectric layer and a dummy interconnect portion overlapping at least a portion of the dummy passive element. The methods eliminate the need for planarizing.
摘要翻译：公开了制造无源元件的方法和包括无源元件的半导体器件，其包括使用虚拟无源元件。虚拟无源元件是被添加到芯片布局以帮助平坦化但在有源电路中不使用的无源元件或线。该方法的一个实施例包括形成无源元件和邻近无源元件的虚拟无源元件; 在无源元件和虚拟无源元件上形成电介质层，其中介电层在无源元件和虚拟无源元件之间基本上是平面的; 并且在电介质层中形成通过电介质层与无源元件的互连以及与虚拟无源元件的至少一部分重叠的虚拟互连部分。该方法消除了平面化的需要。

29. 发明授权

US07768055B2 Passive components in the back end of integrated circuits 失效
标题翻译：集成电路后端的被动元件
公开(公告)号：US07768055B2
公开(公告)日：2010-08-03
申请号：US11164634
申请日：2005-11-30
申请人： Anil K. Chinthakindi , Douglas D. Coolbaugh , Ebenezer E. Eshun , Zhong-Xiang He , Jeffrey B. Johnson , Jonghae Kim , Jean-Oliver Plouchart , Anthony K. Stamper
发明人： Anil K. Chinthakindi , Douglas D. Coolbaugh , Ebenezer E. Eshun , Zhong-Xiang He , Jeffrey B. Johnson , Jonghae Kim , Jean-Oliver Plouchart , Anthony K. Stamper
IPC分类号： H01L29/94
CPC分类号： H01L23/5228 , H01L23/5227 , H01L28/87 , H01L2924/0002 , H01L2924/00
摘要： Passive components are formed in the back end by using the same deposition process and materials as in the rest of the back end. Resistors are formed by connecting in series individual structures on the nth, (n+1)th, etc levels of the back end. Capacitors are formed by constructing a set of vertical capacitor plates from a plurality of levels in the back end, the plates being formed by connecting electrodes on two or more levels of the back end by vertical connection members.
摘要翻译：通过使用与后端的其余部分相同的沉积工艺和材料在后端形成被动部件。电阻器通过连接在后端的第n（n + 1）等级上的串联单独结构而形成。电容器通过从后端的多个层构造一组垂直电容器板而形成，该板通过垂直连接构件在后端的两层或更多层上连接电极而形成。

30. 发明授权

US07701037B2 Orientation-independent multi-layer BEOL capacitor 有权
标题翻译：取向无关多层BEOL电容
公开(公告)号：US07701037B2
公开(公告)日：2010-04-20
申请号：US11831208
申请日：2007-07-31
申请人： Anil K. Chinthakindi , Eric Thompson
发明人： Anil K. Chinthakindi , Eric Thompson
IPC分类号： H01L29/00
CPC分类号： H01L27/0805 , H01L23/5223 , H01L2924/0002 , H01L2924/00
摘要： A plurality of interdigitized conductive fingers are arranged to form a substantially square configuration in each of a plurality of layers separated by a high dielectric constant material, wherein each of the plurality of interdigitized conductive fingers includes at least one bend of substantially ninety degrees. The plurality of interdigitized conductive fingers includes a first set of fingers that are connected to an anode terminal, and a second set of fingers that are connected to a cathode terminal. The plurality of layers includes a bottommost layer that is in closest proximity to a substrate relative to other layers of the plurality of layers. The bottommost layer does not include any fingers connected to the anode terminal.
摘要翻译：多个交叉指状的导电指状物被布置成在由高介电常数材料分离的多个层中的每一层中形成基本上正方形的构造，其中多个交叉指状导电指状物中的每一个包括至少一个基本上90度的弯曲部。多个交叉指状的导电指状物包括连接到阳极端子的第一组指状物和连接到阴极端子的第二组指状物。多个层包括相对于多个层中的其它层最靠近衬底的最底层。最底层不包括连接到阳极端子的任何手指。

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