专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明申请

US20110127542A1 SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20110127542A1
公开(公告)日：2011-06-02
申请号：US12881421
申请日：2010-09-14
申请人： Akira Hokazono
发明人： Akira Hokazono
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L21/823814 , H01L21/823807 , H01L27/092 , H01L29/165 , H01L29/665 , H01L29/66545 , H01L29/66628 , H01L29/66636 , H01L29/7834 , H01L29/7848
摘要： According to one embodiment, a semiconductor device contains a gate electrode, SiGe layers, Si layers, source/drain regions, and silicide layers. The gate electrode is formed on a semiconductor substrate via a gate insulating film. The SiGe layers are formed on both sides of the gate electrode on the semiconductor substrate. Over half of a region of the SiGe layers is higher than an interface between the semiconductor substrate and the gate insulating film. The Si layers are formed on the SiGe layers. The source/drain regions are formed on both sides of the gate electrode in the Si layers, the SiGe layers and the semiconductor substrate. The silicide layers are formed on the Si layers.
摘要翻译：根据一个实施例，半导体器件包含栅电极，SiGe层，Si层，源/漏区和硅化物层。栅电极通过栅极绝缘膜形成在半导体衬底上。 SiGe层形成在半导体衬底上的栅电极的两侧。 SiGe层的一半以上的区域高于半导体衬底和栅极绝缘膜之间的界面。在SiGe层上形成Si层。源极/漏极区域形成在Si层中的栅电极的两侧，SiGe层和半导体衬底上。硅化物层形成在Si层上。

22. 发明授权

US07888747B2 Semiconductor device and method of fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07888747B2
公开(公告)日：2011-02-15
申请号：US12421203
申请日：2009-04-09
申请人： Akira Hokazono
发明人： Akira Hokazono
IPC分类号： H01L27/088
CPC分类号： H01L21/823412 , H01L21/823418 , H01L21/82345 , H01L21/823481 , H01L29/1054 , H01L29/6659 , H01L29/7833
摘要： A semiconductor device includes a semiconductor substrate; a first impurity diffusion suppression layer and a thicker second impurity diffusion suppression layer formed on the semiconductor substrate in first and second isolated transistor regions; first and second crystal layers formed on the first and second impurity diffusion suppression layers; first and second gate electrodes formed on the first and second crystal layers; first and second p-type channel regions formed in the semiconductor substrate, the first impurity diffusion suppression layer and respective of the first and second crystal layers below the first and second gate electrodes; and first and second source/drain regions formed on both sides of the first and second channel region; wherein the first and second p-type channels have lower impurity concentrations in respective of the first and second crystal layers than in the semiconductor substrate.
摘要翻译：半导体器件包括半导体衬底; 形成在第一和第二隔离晶体管区域的半导体衬底上的第一杂质扩散抑制层和较厚的第二杂质扩散抑制层; 形成在第一和第二杂质扩散抑制层上的第一和第二晶体层; 形成在第一和第二晶体层上的第一和第二栅电极; 形成在半导体衬底中的第一和第二p型沟道区，第一杂质扩散抑制层以及第一和第二栅电极下面的第一和第二晶体层中的每一个; 以及形成在第一和第二沟道区域的两侧上的第一和第二源极/漏极区域; 其中所述第一和第二p型沟道在所述第一晶体层和所述第二晶体层中的杂质浓度比所述半导体衬底中的杂质浓度低。

23. 发明申请

US20100252869A1 SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME 失效
标题翻译：半导体器件及其制造方法
公开(公告)号：US20100252869A1
公开(公告)日：2010-10-07
申请号：US12491674
申请日：2009-06-25
申请人： Akira HOKAZONO
发明人： Akira HOKAZONO
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L21/823807 , H01L21/823814 , H01L29/165 , H01L29/66507 , H01L29/66628 , H01L29/66636 , H01L29/7834 , H01L29/7848 , Y10S438/938
摘要： A semiconductor device according to one embodiment includes: a gate electrode formed on a semiconductor substrate via a gate insulating film; Si:C layers formed on the semiconductor substrate in sides of the gate electrode; p-type source/drain regions formed in sides of the gate electrode in the semiconductor substrate, and a part of the p-type source/drain regions being formed in the Si:C layers; and silicide layers formed on the Si:C layers.
摘要翻译：根据一个实施例的半导体器件包括：通过栅极绝缘膜形成在半导体衬底上的栅电极; Si：在栅极侧的半导体衬底上形成的C层; 形成在半导体衬底中的栅电极的侧面中的p型源极/漏极区，并且部分p型源极/漏极区域形成在Si：C层中; 以及形成在Si：C层上的硅化物层。

24. 发明申请

US20080054364A1 SEMICONDUCTOR DEVICE HAVING CMOS DEVICE 审中-公开
标题翻译：具有CMOS器件的半导体器件
公开(公告)号：US20080054364A1
公开(公告)日：2008-03-06
申请号：US11847865
申请日：2007-08-30
申请人： Akira HOKAZONO
发明人： Akira HOKAZONO
IPC分类号： H01L21/8238
CPC分类号： H01L21/823814 , H01L27/092 , H01L27/1203
摘要： A semiconductor device includes an n-channel MIS transistor and a p-channel MIS transistor. The n-channel MIS transistor includes a first source region formed in a semiconductor region on a substrate, a first drain region formed in the semiconductor region apart from the first source region, a first gate insulating film, and a first gate electrode formed on the first gate insulating film. The p-channel MIS transistor includes a second source region formed in the semiconductor region, a second drain region formed in the semiconductor region apart from the second source region, a second gate insulating film, and a second gate electrode formed on the second gate insulating film. The first and second drain regions are arranged to be connected to each other and made of the same material, and one of the first and second source regions is made of a material different from the first and second drain regions.
摘要翻译：半导体器件包括n沟道MIS晶体管和p沟道MIS晶体管。 n沟道MIS晶体管包括形成在衬底上的半导体区域中的第一源极区域，形成在与第一源极区域隔开的半导体区域中的第一漏极区域，形成在第一源极区域上的第一栅极绝缘膜和第一栅极电极第一栅绝缘膜。 p沟道MIS晶体管包括形成在半导体区域中的第二源极区域，形成在与第二源极区域隔开的半导体区域中的第二漏极区域，第二栅极绝缘膜和形成在第二栅极绝缘体上的第二栅极电极电影。第一和第二漏极区域被布置为彼此连接并由相同的材料制成，并且第一和第二源极区域之一由与第一和第二漏极区域不同的材料制成。

25. 发明授权

US07141467B2 Semiconductor device having metal silicide films formed on source and drain regions and method for manufacturing the same 失效
标题翻译：在源极和漏极区域上形成有金属硅化物膜的半导体器件及其制造方法
公开(公告)号：US07141467B2
公开(公告)日：2006-11-28
申请号：US10759205
申请日：2004-01-20
申请人： Akira Hokazono , Kazuya Ohuchi
发明人： Akira Hokazono , Kazuya Ohuchi
IPC分类号： H01L21/8238
CPC分类号： H01L21/28202 , H01L29/4933 , H01L29/518
摘要： A semiconductor device includes a p-type well region, n+-type diffusion regions formed in the surface region of the p-type well region, a gate electrode containing silicon and formed above the p-type well region with a gate insulating film disposed therebetween, and NiSi films formed in the surface regions of the n+-type diffusion regions. In the semiconductor device, p-type impurity is doped in the depth direction from the surface of the NiSi film and the impurity profile of p-type impurity is so formed that a peak concentration of not lower than 1E20 cm−3 will be provided in a preset depth position of the NiSi film and the concentration in the interface between the NiSi film and the n+-type diffusion region and the concentration in a position deeper than the interface will not be higher than 5E19 cm−3.
摘要翻译：半导体器件包括在p型阱区的表面区域中形成的p型阱区，n + +型扩散区，含有硅并形成在p型阱上的p型阱的扩散区区域，其间设置有栅极绝缘膜，以及形成在n + +型扩散区域的表面区域中的NiSi膜。在半导体装置中，从NiSi膜的表面向深度方向掺杂p型杂质，p型杂质的杂质分布形成为不低于1E20cm -3的峰值浓度， / SUP>将设置在NiSi膜的预设深度位置以及NiSi膜和n + +型扩散区之间的界面中的浓度，并且在比界面更深的位置处的浓度不会高于5E19 cm -3。

26. 发明申请

US20060166456A1 Semiconductor device and manufacturing method thereof 审中-公开
标题翻译：半导体装置及其制造方法
公开(公告)号：US20060166456A1
公开(公告)日：2006-07-27
申请号：US11388523
申请日：2006-03-25
申请人： Makoto Fujiwara , Kazunari Ishimaru , Akira Hokazono
发明人： Makoto Fujiwara , Kazunari Ishimaru , Akira Hokazono
IPC分类号： H01L21/20
CPC分类号： H01L29/785 , H01L21/26586 , H01L29/41733 , H01L29/458 , H01L29/66545 , H01L29/66803 , H01L29/66818
摘要： A semiconductor layer in which a primary part of a FinFET is formed, i.e., a fin has a shape which is long in a direction x and short in a direction y. A width of the fin in the direction y changes on three stages. First, in a channel area between gate electrodes each having a gate length Lg, the width of the fin in the direction y is Wch. Further, the width of the fin in the direction y in a source/drain extension area adjacent to the channel area in the direction x is Wext (>Wch). Furthermore, the width of the fin in the direction y in a source/drain area adjacent to the source/drain extension area in the direction x is Wsd (>Wext).
摘要翻译：形成FinFET的主要部分即散热片的半导体层具有在x方向上长且在y方向上短的形状。翅片沿方向y的宽度在三个阶段上变化。首先，在栅极长度为Lg的栅电极之间的沟道区域中，鳍方向y的宽度为Wch。此外，与方向x上的通道区域相邻的源极/漏极扩展区域中的鳍状物的宽度方向是Wext（> Wch）。此外，与源极/漏极扩展区域相邻的源极/漏极区域中在方向x上的方向y上的鳍的宽度为Wsd（> Wext）。

27. 发明授权

US07045409B2 Semiconductor device having active regions connected together by interconnect layer and method of manufacture thereof 失效
公开(公告)号：US07045409B2
公开(公告)日：2006-05-16
申请号：US10974821
申请日：2004-10-28
申请人： Akira Hokazono
发明人： Akira Hokazono
IPC分类号： H01L21/8238
CPC分类号： H01L21/76895 , H01L21/76224 , H01L21/823871 , H01L21/823878
摘要： A semiconductor device having active regions connected by an interconnect line, which includes first and second transistors each having active regions and formed spaced apart from each other in a semiconductor substrate, an isolation region for isolating the first and second transistors from each other, a slit formed in the isolation region to allow those paired active regions of the first and second transistors which are opposed to each other with the isolation region interposed therebetween to communicate with each other through it, a conductive film formed on the inner walls of the slit, and an interconnect layer having first and second portions, each of which is electrically connected with a corresponding one of the paired active regions, and a third portion which is formed along the slit on the isolation region to connect the first and second portions with each other.

28. 发明申请

US20050212040A1 Semiconductor device having gate sidewall structure in silicide process and producing method of the semiconductor device 审中-公开
标题翻译：在硅化物工艺中具有栅极侧壁结构的半导体器件和半导体器件的制造方法
公开(公告)号：US20050212040A1
公开(公告)日：2005-09-29
申请号：US10947405
申请日：2004-09-23
申请人： Akira Hokazono , Makoto Fujiwara
发明人： Akira Hokazono , Makoto Fujiwara
IPC分类号： H01L21/28 , H01L21/336 , H01L29/423 , H01L29/49 , H01L29/78
CPC分类号： H01L29/665 , H01L29/6656 , H01L29/6659
摘要： A gate insulation film is formed on a semiconductor substrate. A gate electrode is formed on the gate insulation film. A silicide film is formed on the gate electrode. First gate sidewall films are formed on side surfaces of the gate electrode. Second gate sidewall films are formed on the first gate sidewall films on the side surfaces of the gate electrode. First sidewall films are formed on side surfaces of the silicide film on the gate electrode. A source region and a drain region are formed on the semiconductor substrate so as to sandwich a channel region formed under the gate insulation film. Second sidewall films are formed on end portions of the first and second gate sidewall films formed on the source region and the drain region.
摘要翻译：在半导体衬底上形成栅极绝缘膜。在栅极绝缘膜上形成栅电极。在栅电极上形成硅化物膜。第一栅极侧壁膜形成在栅电极的侧表面上。第二栅极侧壁膜形成在栅电极的侧表面上的第一栅极侧壁膜上。第一侧壁膜形成在栅电极上的硅化物膜的侧表面上。源极区域和漏极区域形成在半导体衬底上，以夹持形成在栅极绝缘膜下面的沟道区域。第二侧壁膜形成在形成在源极区域和漏极区域上的第一和第二栅极侧壁膜的端部。

29. 发明授权

US06864544B2 Semiconductor device having active regions connected together by interconnect layer and method of manufacture thereof 失效
公开(公告)号：US06864544B2
公开(公告)日：2005-03-08
申请号：US10083163
申请日：2002-02-27
申请人： Akira Hokazono
发明人： Akira Hokazono
IPC分类号： H01L21/28 , H01L21/3205 , H01L21/76 , H01L21/762 , H01L21/768 , H01L21/8234 , H01L21/8238 , H01L21/8244 , H01L23/52 , H01L23/522 , H01L27/08 , H01L27/088 , H01L27/092 , H01L27/11 , H01L29/06
CPC分类号： H01L21/76895 , H01L21/76224 , H01L21/823871 , H01L21/823878
摘要： A semiconductor device having active regions connected by an interconnect line, which includes first and second transistors each having active regions and formed spaced apart from each other in a semiconductor substrate, an isolation region for isolating the first and second transistors from each other, a slit formed in the isolation region to allow those paired active regions of the first and second transistors which are opposed to each other with the isolation region interposed therebetween to communicate with each other through it, a conductive film formed on the inner walls of the slit, and an interconnect layer having first and second portions, each of which is electrically connected with a corresponding one of the paired active regions, and a third portion which is formed along the slit on the isolation region to connect the first and second portions with each other.

30. 发明授权

US5854496A Hydrogen-terminated diamond misfet and its manufacturing method 失效
标题翻译：氢终止金刚石错误及其制造方法
公开(公告)号：US5854496A
公开(公告)日：1998-12-29
申请号：US919792
申请日：1997-08-29
申请人： Takefumi Ishikura , Satoshi Yamashita , Hiroshi Kawarada , Akira Hokazono
发明人： Takefumi Ishikura , Satoshi Yamashita , Hiroshi Kawarada , Akira Hokazono
IPC分类号： H01L21/04 , H01L21/336 , H01L29/10 , H01L29/16 , H01L29/78 , H01L29/786 , H01L31/0312
CPC分类号： H01L29/1602 , H01L29/1033 , H01L29/66045 , H01L29/78
摘要： On the surface of a hydrogen-terminated diamond 1 formed by terminating a surface 2 of either a homoepitaxial diamond or a heteroepitaxial diamond or a surface-flattened polycrystal diamond are formed a drain-ohmic contact 4 and a source-ohmic contact 3 of gold or platinum, an insulating layer 5 formed of silicon oxide (SiO.sub.x : 1.ltoreq.X.ltoreq.2) and a gate electrode 6 mounted on said insulating layer, and the surface other than the element forming region is set to be an insulating region being non-hydrogen-terminated, for example, oxygen-terminated, and the elements formed on said region is being isolated.
摘要翻译：在通过端接同质外延金刚石或异质外延金刚石或表面平坦多晶金刚石的表面2形成的氢终止金刚石1的表面上形成漏极 - 欧姆接触4和金 - 欧姆接触3，铂，由氧化硅（SiO x：1

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式