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211. 发明授权

US07514730B2 Method of fabricating a non-floating body device with enhanced performance 有权
标题翻译：制造具有增强性能的非浮体装置的方法
公开(公告)号：US07514730B2
公开(公告)日：2009-04-07
申请号：US11032403
申请日：2005-01-10
申请人： Horng-Huei Tseng , Jhy-Chyum Guo , Chenming Hu , Da-Chi Lin
发明人： Horng-Huei Tseng , Jhy-Chyum Guo , Chenming Hu , Da-Chi Lin
IPC分类号： H01L29/06
CPC分类号： H01L29/7842 , H01L21/76232 , H01L21/76264 , H01L21/76283 , H01L29/0653 , H01L29/1054 , H01L29/7848 , H01L2924/0002 , H01L2924/00
摘要： Provided is a semiconductor transistor device including a substrate having at least two regions, a semiconductive region extending to a first surface of the substrate and an insulative region extending to a second surface of the substrate. The semiconductor transistor device also includes a patterned semiconductor structure overlying both surfaces of the substrate. The patterned semiconductor structure includes a source or drain region overlying the second surface of the substrate. The semiconductor transistor device further includes a patterned gate structure overlying the patterned semiconductor structure.
摘要翻译：提供了一种半导体晶体管器件，其包括具有至少两个区域的衬底，延伸到衬底的第一表面的半导体区域和延伸到衬底的第二表面的绝缘区域。半导体晶体管器件还包括覆盖在衬底的两个表面上的图案化半导体结构。图案化的半导体结构包括覆盖在衬底的第二表面上的源极或漏极区域。半导体晶体管器件还包括覆盖图案化半导体结构的图案化栅极结构。

212. 发明申请

US20080185724A1 Aluminum-based interconnection in bond pad layer 有权
标题翻译：接合垫层中的铝基互连
公开(公告)号：US20080185724A1
公开(公告)日：2008-08-07
申请号：US11582129
申请日：2006-10-17
申请人： Horng-Huei Tseng , Chenming Hu
发明人： Horng-Huei Tseng , Chenming Hu
IPC分类号： H01L23/48
CPC分类号： H01L23/53238 , H01L23/53223 , H01L24/02 , H01L2224/04073 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01022 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01044 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/05042 , H01L2924/14 , H01L2924/19041 , H01L2924/30105 , H01L2924/3025
摘要： A semiconductor metal structure with an efficient usage of the chip area is provided. The structure includes a substrate, a copper-based interconnection structure over the substrate, the copper-based interconnection structure comprising a plurality of metallization layers connected by vias and in first dielectric layers, at least one aluminum-based layer over and connected to the copper-based interconnection structure, wherein a top layer of the at least one aluminum-based layer comprises a bond pad and an interconnect line connecting to two underlying vias, vias/contacts connecting a top layer of the copper-based interconnection structure and a bottom layer of the at least one aluminum-based layer, wherein the vias/contacts are in a second dielectric layer, and a third dielectric layer overlying the at least one aluminum-based layer, wherein the bond pad is exposed through an opening in the third dielectric layer.
摘要翻译：提供了一种有效利用芯片面积的半导体金属结构。该结构包括衬底，在衬底上的铜基互连结构，铜基互连结构包括通过通孔连接的多个金属化层和在第一介电层中的至少一个铝基层，并连接到铜的所述互连结构，其中所述至少一个铝基层的顶层包括接合焊盘和连接到两个底部通孔的互连线，连接铜基互连结构的顶层的通孔/触点和底层的至少一个铝基层，其中所述通孔/触点位于第二电介质层中，以及覆盖所述至少一个铝基层的第三电介质层，其中所述接合焊盘通过所述第三电介质中的开口暴露层。

213. 发明申请

US20070117374A1 Method of forming via recess in underlying conductive line 审中-公开
标题翻译：在下面的导线中形成通孔凹槽的方法
公开(公告)号：US20070117374A1
公开(公告)日：2007-05-24
申请号：US11652210
申请日：2007-01-11
申请人： Chung-Shi Liu , Chen-Hua Yu , Horng-Huei Tseng
发明人： Chung-Shi Liu , Chen-Hua Yu , Horng-Huei Tseng
IPC分类号： H01L21/4763
CPC分类号： H01L23/5329 , H01L21/76802 , H01L21/76805 , H01L21/76807 , H01L21/76816 , H01L21/76834 , H01L21/76844 , H01L21/76847 , H01L23/5226 , H01L23/53214 , H01L23/53228 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A method of fabricating a semiconductor device includes forming a via in a dielectric layer that opens to a conductive line underlying the dielectric layer, and forming a via recess in the conductive line at the via. The via recess in the conductive line has a depth ranging from about 100 angstroms to about 600 angstroms. Via-fill material fills the via recess and at least partially fills the via, such that the via-fill material is electrically connected to the conductive line. The via recess may have a same size or smaller cross-section area than that of the via, for example. Such via structure may be part of a dual damascene structure in an intermetal dielectric structure, for example.
摘要翻译：制造半导体器件的方法包括在介电层下方形成导电线的电介质层中形成通孔，以及在通孔中的导电线中形成通路凹槽。导线中的通路凹槽的深度范围为约100埃至约600埃。通孔填充材料填充通孔凹部并且至少部分地填充通孔，使得通孔填充材料电连接到导电线。例如，通孔凹部可以具有与通孔相同的尺寸或更小的横截面面积。例如，这种通孔结构可以是金属间电介质结构中的双镶嵌结构的一部分。

214. 发明申请

US20060027932A1 Interconnect with composite barrier layers and method for fabricating the same 有权
标题翻译：与复合阻挡层互连及其制造方法
公开(公告)号：US20060027932A1
公开(公告)日：2006-02-09
申请号：US11240216
申请日：2005-09-30
申请人： Chen-Hua Yu , Horng-Huei Tseng , Syun-Ming Jang , Chenming Hu
发明人： Chen-Hua Yu , Horng-Huei Tseng , Syun-Ming Jang , Chenming Hu
IPC分类号： H01L23/48 , H01L23/52
CPC分类号： H01L21/76846
摘要： Composite ALD-formed diffusion barrier layers. In a preferred embodiment, a composite conductive layer is composed of a diffusion barrier layer and/or a low-resistivity metal layer formed by atomic layer deposition (ALD) lining a damascene opening in dielectrics, serving as diffusion blocking and/or adhesion improvement. The preferred composite diffusion barrier layers are dual titanium nitride layers or dual tantalum nitride layers, triply laminar of tantalum, tantalum nitride and tantalum-rich nitride, or tantalum, tantalum nitride and tantalum, formed sequentially on the opening by way of ALD.
摘要翻译：复合ALD形成的扩散阻挡层。在优选实施例中，复合导电层由扩散阻挡层和/或由电介质中的镶嵌开口衬底的原子层沉积（ALD）形成的低电阻金属层组成，用作扩散阻挡和/或粘附改善。优选的复合扩散阻挡层是通过ALD在开口上依次形成的双氮化钛层或双氮化钽层，三层层状的钽，氮化钽和富钽的氮化物，或钽，氮化钽和钽。

215. 发明授权

US06897510B2 MIM capacitor having a high-dielectric-constant interelectrode insulator and a method of fabrication 有权
标题翻译：具有高介电常数的电极间绝缘体的MIM电容器及其制造方法
公开(公告)号：US06897510B2
公开(公告)日：2005-05-24
申请号：US10647715
申请日：2003-08-25
申请人： Horng-Huei Tseng
发明人： Horng-Huei Tseng
IPC分类号： H01L21/00 , H01L21/02 , H01L21/20 , H01L21/8242 , H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L28/55 , H01L27/10852 , H01L28/60
摘要： A metal-insulator-metal (MIM) capacitor using a high-k dielectric and method of fabrication are described. After forming node contacts to the substrate a patterned stacked layer comprised of a first metal layer, an insulating dummy layer, and a second metal layer is formed over the node contacts. Sidewall spacers are formed form a third metal layer to complete the lower electrode. A thin dielectric film is deposited. A patterned fourth metal layer is used as the upper electrode to complete the MIM capacitor. The patterned insulating dummy layer acts as a template for making the capacitor without partaking in the electrical properties of the capacitor. The height of the dummy layer is used to fine-tune the capacitance for the circuit requirements. The dummy layer is not an active part of the circuit. The dummy layer does not react with the metals, barrier layers are not required, reducing process complexity.
摘要翻译：描述了使用高k电介质和制造方法的金属绝缘体金属（MIM）电容器。在与衬底形成节点接触之后，在节点接触件上形成由第一金属层，绝缘假层和第二金属层构成的图案化叠层。侧壁间隔件由第三金属层形成，以完成下电极。沉积薄介电膜。使用图案化的第四金属层作为上电极来完成MIM电容器。图案化的绝缘伪层作为制造电容器的模板，而不会分离电容器的电性能。虚拟层的高度用于对电路要求的电容进行微调。虚拟层不是电路的有效部分。虚拟层不与金属反应，不需要阻挡层，降低了工艺的复杂性。

216. 发明申请

US20050048713A1 MIM CAPACITOR HAVING A HIGH-DIELECTRIC-CONSTANT INTERELECTRODE INSULATOR AND A METHOD OF FABRICATION 有权
标题翻译：具有高介电常数电介质绝缘体的MIM电容器和制造方法
公开(公告)号：US20050048713A1
公开(公告)日：2005-03-03
申请号：US10647715
申请日：2003-08-25
申请人： Horng-Huei Tseng
发明人： Horng-Huei Tseng
IPC分类号： H01L21/00 , H01L21/02 , H01L21/20 , H01L21/8242 , H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L28/55 , H01L27/10852 , H01L28/60
摘要： A metal-insulator-metal (MIM) capacitor using a high-k dielectric and method of fabrication are described. After forming node contacts to the substrate a patterned stacked layer comprised of a first metal layer, an insulating dummy layer, and a second metal layer is formed over the node contacts. Sidewall spacers are formed form a third metal layer to complete the lower electrode. A thin high-k dielectric film is deposited. A patterned fourth metal layer is used as the upper electrode to complete the MIM capacitor. The patterned insulating dummy layer acts as a template for making the capacitor without partaking in the electrical properties of the capacitor. The height of the dummy layer is used to fine-tune the capacitance for the circuit requirements. The dummy layer is not an active part of the circuit. The dummy layer does not react with the metals, barrier layers are not required, reducing process complexity.
摘要翻译：描述了使用高k电介质和制造方法的金属绝缘体金属（MIM）电容器。在与衬底形成节点接触之后，在节点接触件上形成由第一金属层，绝缘假层和第二金属层构成的图案化叠层。侧壁间隔件由第三金属层形成，以完成下电极。沉积薄的高k电介质膜。使用图案化的第四金属层作为上电极来完成MIM电容器。图案化的绝缘伪层作为制造电容器的模板，而不会分离电容器的电性能。虚拟层的高度用于对电路要求的电容进行微调。虚拟层不是电路的有效部分。虚拟层不与金属反应，不需要阻挡层，降低了工艺的复杂性。

217. 发明申请

US20050014360A1 Method for fabricating copper interconnects 失效
标题翻译：制造铜互连的方法
公开(公告)号：US20050014360A1
公开(公告)日：2005-01-20
申请号：US10621676
申请日：2003-07-17
申请人： Chen-Hua Yu , Horng-Huei Tseng
发明人： Chen-Hua Yu , Horng-Huei Tseng
IPC分类号： H01L21/768 , H01L21/4763 , H01L21/44
CPC分类号： H01L21/76849 , H01L21/76867
摘要： A method for capping copper or copper alloy interconnects. A dielectric layer is formed overlaying a semiconductor substrate. An opening is formed in the dielectric layer and subsequently embedded copper or copper alloy form an interconnect structure. A silicon layer is formed on the copper or copper alloy by sputtering or chemical vapor deposition. A copper silicide layer is formed by reacting the silicon layer with the underlying copper or copper alloy as a capping layer.
摘要翻译：一种用于封盖铜或铜合金互连的方法。形成覆盖半导体基板的电介质层。在电介质层中形成开口，随后嵌入的铜或铜合金形成互连结构。通过溅射或化学气相沉积在铜或铜合金上形成硅层。硅化硅层通过使硅层与下面的铜或铜合金作为覆盖层反应而形成。

218. 发明授权

US06730958B2 Nonvolatile memory device with reduced floating gate and increased coupling ratio and manufacturing method thereof 有权
标题翻译：具有减小的浮动栅极和增加耦合比的非易失性存储器件及其制造方法
公开(公告)号：US06730958B2
公开(公告)日：2004-05-04
申请号：US10446684
申请日：2003-05-29
申请人： Horng-Huei Tseng
发明人： Horng-Huei Tseng
IPC分类号： H01L29788
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/42324 , Y10S257/90
摘要： A nonvolatile memory device with a reduced size floating gate and an increased coupling ratio is disclosed. The nonvolatile memory device includes two isolation structures protruding above a semiconductor substrate. Two dielectric spacers are disposed on a pair of opposing sidewalls of the two isolation structures. The two dielectric spacers are spaced from one another at a distance that defines a gate width which is beyond lithography limit. A tunnel dielectric and a floating gate are provided on substrate and confined between the two dielectric spacers. The floating gate has a smaller bottom surface area relative to its top surface area and has a surface substantially coplanar with a surface of the isolation structures. On the coplanar surface, an inter-gate dielectric and a control gate are provided. Optionally, a lightly doped region is provided beside the floating gate 118 and within the substrate. A manufacturing method for forming such memory device is also disclosed.
摘要翻译：公开了一种具有减小尺寸的浮动栅极和增加的耦合比的非易失性存储器件。非易失性存储器件包括在半导体衬底上突出的两个隔离结构。两个电介质间隔物设置在两个隔离结构的一对相对的侧壁上。两个电介质间隔物以限定超出光刻极限的栅极宽度的距离彼此间隔开。隧道电介质和浮栅设置在衬底上并被限制在两个电介质间隔物之间。浮动栅极相对于其顶表面区域具有较小的底表面积，并且具有与隔离结构的表面基本上共面的表面。在共面上设置栅极间电介质和控制栅极。可选地，在浮置栅极118旁边和衬底内设置轻掺杂区域。还公开了一种用于形成这种存储器件的制造方法。

219. 发明授权

US06642570B2 Structure of flash memory with high coupling ratio 有权
标题翻译：具有高耦合比的闪存结构
公开(公告)号：US06642570B2
公开(公告)日：2003-11-04
申请号：US09852405
申请日：2001-05-09
申请人： Horng-Huei Tseng
发明人： Horng-Huei Tseng
IPC分类号： H01L29788
CPC分类号： H01L27/11521 , H01L21/28273 , H01L27/115 , H01L29/42332
摘要： The flash memory structure includes a substrate having trenches formed therein, a first dielectric layer and a first conductive layer are stacked on the substrate. Isolations are formed in the trenches and protruding over the surface of the substrate, wherein the first conductive layer is also protruded over the isolations. A second conductive layer is lying the surface of the first conductive layer and a second dielectric layer formed thereon. A third conductive layer is formed on the second dielectric layer. The floating gate is consisted of first conductive layer and the second conductive layer.
摘要翻译：闪速存储器结构包括其中形成有沟槽的衬底，第一介电层和第一导电层堆叠在衬底上。隔离层形成在沟槽中并在衬底的表面上突出，其中第一导电层也突出在隔离物上。第二导电层位于第一导电层的表面和形成在其上的第二介电层。在第二电介质层上形成第三导电层。浮栅由第一导电层和第二导电层构成。

220. 发明授权

US06627515B1 Method of fabricating a non-floating body device with enhanced performance 有权
标题翻译：制造具有增强性能的非浮体装置的方法
公开(公告)号：US06627515B1
公开(公告)日：2003-09-30
申请号：US10318471
申请日：2002-12-13
申请人： Horng-Huei Tseng , Jyh-Chyurn Guo , Chenming Hu , Da-Chi Lin
发明人： Horng-Huei Tseng , Jyh-Chyurn Guo , Chenming Hu , Da-Chi Lin
IPC分类号： H01L2176
CPC分类号： H01L29/7842 , H01L21/76232 , H01L21/76264 , H01L21/76283 , H01L29/0653 , H01L29/1054 , H01L29/7848 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a buried silicon oxide region in a semiconductor substrate with portions of the buried silicon oxide region formed underlying portions of a strained silicon shape, and where the strained silicon shape is used to accommodate a semiconductor device, has been developed. A first embodiment of this invention features a buried oxide region formed in a silicon alloy layer, via thermal oxidation procedures. A first portion of the strained silicon layer, protected during the thermal oxidation procedure, overlays the silicon alloy layer while a second portion of the strained silicon layer overlays the buried oxide region. A second embodiment of this invention features an isotropic dry etch procedure used to form an isotropic opening in the silicon alloy layer, with the opening laterally extending under a portion of the strained silicon layer. Subsequent silicon oxide deposition and planarization procedures results in a first portion of the strained silicon layer overlying the silicon alloy layer while a second portion overlays a buried oxide region. A semiconductor device is then formed in the strained silicon layer, with specific elements of the semiconductor device located on a buried oxide region.
摘要翻译：已经开发了在半导体衬底中形成掩埋氧化硅区域的方法，其中形成在应变硅形状的部分下方的掩埋氧化硅区域的部分以及应变硅形状用于容纳半导体器件的方法。本发明的第一实施例的特征在于通过热氧化工艺在硅合金层中形成的掩埋氧化物区域。在热氧化过程中保护的应变硅层的第一部分覆盖硅合金层，而应变硅层的第二部分覆盖掩埋氧化物区域。本发明的第二实施例的特征在于用于在硅合金层中形成各向同性开口的各向同性干法蚀刻程序，其中开口横向延伸在应变硅层的一部分下方。随后的氧化硅沉积和平坦化过程导致覆盖硅合金层的应变硅层的第一部分，而第二部分覆盖掩埋氧化物区域。然后在应变硅层中形成半导体器件，其中半导体器件的特定元件位于掩埋氧化物区域上。

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