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11. 发明授权

EP0430289B1 Fabrication of self-aligned, T-gate hemt 失效
标题翻译：自对准T-栅HEMT的制造
公开(公告)号：EP0430289B1
公开(公告)日：2002-12-18
申请号：EP90122995.5
申请日：1990-11-30
申请人： Hughes Electronics Corporation
发明人： Mishra, Umesh K. , Thompson, Mark A. , Jelloian, Linda M.
IPC分类号： H01L21/335 , H01L21/28 , H01L29/76
CPC分类号： H01L29/66462 , H01L21/28587 , Y10S148/10 , Y10S148/102 , Y10S148/143 , Y10S438/951

12. 发明公开

EP0958608A4 A FIDUCIAL FOR ALIGNING AN INTEGRATED CIRCUIT DIE 失效
标题翻译：取向的取向是集成电路
公开(公告)号：EP0958608A4
公开(公告)日：2001-03-14
申请号：EP97954083
申请日：1997-12-11
申请人： INTEL CORP
发明人： WINER PAUL GEORGE , LIVENGOOD RICHARD H
IPC分类号： H01L23/544 , H01L23/58 , H01L29/41
CPC分类号： H01L23/544 , H01L2223/5442 , H01L2223/54473 , H01L2223/5448 , H01L2924/0002 , Y10S148/102 , Y10S438/975 , H01L2924/00
摘要： A fiducial for aligning an integrated circuit die (301). In one embodiment, the fiducial is configured to be exposed by laser chemical etching through a silicon substrate (313) through the back side of a C4 package integrated circuit die. The presently described fiducial includes floating diffusion regions (307, 309, 311) disposed in the substrate. An oxide layer (321) free of metal contacts is disposed over the diffusion regions (307, 309, 311) within the fiducial region of the integrated circuit. A metal pattern layer (323) is disposed beneath the oxide layer (321) to provide alignment information. The metal pattern layer (323) is configured to be visible through the oxide layer (321) after the silicon substrate (313) has been removed from the fiducial region. A light block (327) is disposed between the metal pattern layer (323) and an underlying epoxy underfill layer (325) to minimize the risk of an excessive amount of light from being exposed to the underlying epoxy layer (325), which minimizes the risk of the epoxy layer (325) from damaging the integrated circuit from excessive light exposure.

13. 发明公开

EP0430289A2 Fabrication of self-aligned, T-gate hemt 失效
标题翻译： Herstellung von einem selbstausrichtenden T-Gatter-Hemt。
公开(公告)号：EP0430289A2
公开(公告)日：1991-06-05
申请号：EP90122995.5
申请日：1990-11-30
申请人： Hughes Aircraft Company
发明人： Mishra, Umesh K. , Thompson, Mark A. , Jelloian, Linda M.
IPC分类号： H01L21/335 , H01L21/28 , H01L29/76
CPC分类号： H01L29/66462 , H01L21/28587 , Y10S148/10 , Y10S148/102 , Y10S148/143 , Y10S438/951
摘要： A generally T-shaped gate (34) is formed by electron beam irradiation of a multilevel resist structure (20) on a substrate (12). The resist structure (20) has an upper layer (24) which is more sensitive to the electron beam than a lower layer (22) thereof. A generally T-shaped opening (30) is formed in the resist structure (20) by etching of the irradiated areas. An electrically conductive metal is deposited to fill the opening and thereby form a T-shaped gate (34) on the substrate (12). After the resist layer structure (20) and metal deposited thereon is removed, a masking layer (40) is formed on the substrate (12) around the gate (34), having an opening therethrough which is aligned with and wider than the cross section of the gate (34), and defining first and second lateral spacings (52, 54) between opposite extremities of the cross section and adjacent edges of the opening. Deposition of an electrically conductive metal forms source and drain metallizations (48,50) on the substrate (12) on areas underlying the first and lateral spacings (52, 54) respectively. The metallizations (48, 50) are self-aligned to the gate (34) and separated therefrom by the masking effect of the gate (34) during the metal deposition. The gate (34') may have an asymmetrical top section (34b') which provides a larger spacing between the gate (34') and source metallization (48) to increase the breakdown voltage of the device. Insulative oxide sidewalls (38) may be formed on the gate.
摘要翻译：通常在基板（12）上通过电子束照射多层抗蚀剂结构（20）形成大致T形的栅极（34）。抗蚀剂结构（20）具有比其下层（22）对电子束更敏感的上层（24）。通过蚀刻照射区域，在抗蚀剂结构（20）中形成大致T形的开口（30）。沉积导电金属以填充开口，从而在基板（12）上形成T形门（34）。在除去抗蚀剂层结构（20）和沉积在其上的金属之后，在栅极（34）周围的基板（12）上形成掩模层（40），该掩模层具有与其横截面对准并且宽于其截面的开口并且限定在所述横截面的相对两端和所述开口的相邻边缘之间的第一和第二横向间隔（52,54）。导电金属的沉积分别在第一和侧向间隔（52,54）下方的区域上的基底（12）上形成源极和漏极金属化层（48,50）。金属化（48,50）在栅极（34）处自对准，并且在金属沉积期间通过栅极（34）的掩蔽效应与其分离。栅极（34'）可以具有不对称的顶部部分（34b'），其在栅极（34'）和源极金属化（48）之间提供更大的间隔，以增加器件的击穿电压。绝缘氧化物侧壁（38）可以形成在栅极上。

14. 发明授权

EP0173414B1 Method of producing semiconductor devices comprising an overlying polysilicon layer 失效
标题翻译：生产包含多层多晶硅层的半导体器件的方法
公开(公告)号：EP0173414B1
公开(公告)日：1990-07-11
申请号：EP85303692.9
申请日：1985-05-24
申请人： THORN EMI North America Inc.
发明人： Bourassa, Ronald R.
IPC分类号： H01L21/31 , H01L21/82
CPC分类号： H01L28/20 , H01L21/321 , H01L21/32137 , H01L21/32155 , Y10S148/102

15. 发明授权

EP0589631B1 Method for recessed, self aligned, low base resistance structure 失效
标题翻译：一种用于增强，自对准底座结构的方法具有低电阻
公开(公告)号：EP0589631B1
公开(公告)日：1998-12-02
申请号：EP93307352.0
申请日：1993-09-17
申请人： STMicroelectronics, Inc.
发明人： Imhauser, William P.
IPC分类号： H01L21/331 , H01L29/10
CPC分类号： H01L29/66303 , H01L29/0804 , H01L29/1004 , Y10S148/01 , Y10S148/102

16. 发明授权

EP0399881B1 Semiconductor device having two conductor layers and production method thereof 失效
标题翻译：一种半导体器件，包括其制备方法的两个导电层和方法
公开(公告)号：EP0399881B1
公开(公告)日：1996-04-17
申请号：EP90401331.5
申请日：1990-05-18
申请人： FUJITSU LIMITED
发明人： Kajita, Tatsuya
IPC分类号： H01L29/41 , H01L21/82
CPC分类号： H01L21/28273 , H01L29/516 , H01L29/7881 , Y10S148/102 , Y10S438/975

17. 发明授权

EP0478072B1 Procédé pour réaliser des motifs d'alignement de masques 失效
标题翻译：一种用于生产标记为标记的对准过程。
公开(公告)号：EP0478072B1
公开(公告)日：1995-08-02
申请号：EP91202419.7
申请日：1991-09-19
申请人： Philips Electronics N.V.
发明人： van der Plas, Paulus, Société Civile S.P.I.D. , Lifka, Herbert, Société Civile S.P.I.D. , Verhaar, Robertus, Société Civile S.P.I.D.
IPC分类号： H01L21/32 , H01L23/544
CPC分类号： H01L23/544 , H01L21/32 , H01L2223/54453 , H01L2924/0002 , Y10S148/102 , H01L2924/00

18. 发明公开

EP0465152A3 Method for producing semiconductor device having alignment mark 失效
标题翻译：用于生产具有对准标记的半导体器件的方法
公开(公告)号：EP0465152A3
公开(公告)日：1992-04-15
申请号：EP91305871.5
申请日：1991-06-28
申请人： CANON KABUSHIKI KAISHA
发明人： Okabe, Takahiko, c/o Canon Kabushiki Kaisha , Monma, Genzo, c/o Canon Kabushiki Kaisha , Yuzurihara, Hiroshi, c/o Canon Kabushiki Kaisha
IPC分类号： H01L23/544 , H01L21/768
CPC分类号： H01L23/544 , H01L2223/54426 , H01L2223/54453 , H01L2924/0002 , Y10S148/102 , Y10S438/975 , H01L2924/00
摘要： An alignment method for a semiconductor device having a conductive thin film (9) on a conductive substrate surface across an insulation film (4), comprises steps of:
forming in the insulation film, at least two apertures (5,6) exposing the substrate surface therein;
selectively depositing a conductive material (7,8) in the apertures thereby forming a stepped portion in at least one of said apertures; and
forming the conductive thin film (9) at least on said insulation film. The alignment is conducted utilizing the stepped portion.

19. 发明授权

EP0129915B1 A method of manufacturing an integrated circuit device 失效
标题翻译：一种制造集成电路装置的方法
公开(公告)号：EP0129915B1
公开(公告)日：1987-10-28
申请号：EP84107422.2
申请日：1984-06-27
申请人： Teletype Corporation
发明人： Christian, Raymond R. , Zuercher, Joseph C.
IPC分类号： B41J3/20 , H01L21/80 , H01L23/54
CPC分类号： H01L23/544 , H01L2223/54453 , H01L2924/0002 , Y10S148/102 , Y10S438/975 , Y10T156/1052 , H01L2924/00

20. 发明授权

EP0762492B1 Semiconductor device manufacturing method 失效
标题翻译：一种半导体装置的制造方法
公开(公告)号：EP0762492B1
公开(公告)日：2002-11-27
申请号：EP96401812.1
申请日：1996-08-23
申请人： SONY CORPORATION
发明人： Anmo, Hiroaki , Kanematsu, Shigeru , Gomi, Takayuki
IPC分类号： H01L21/74 , H01L21/8228 , H01L21/266
CPC分类号： H01L21/26513 , H01L21/74 , H01L21/8228 , H01L23/544 , H01L2223/54453 , H01L2924/0002 , Y10S148/102 , Y10S438/975 , H01L2924/00

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