专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明申请

US20110092035A1 Formation of high sheet resistance resistors and high capacitance capacitors by a single polysilicon process 有权
标题翻译：通过单个多晶硅工艺形成高电阻电阻器和高容量电容器
公开(公告)号：US20110092035A1
公开(公告)日：2011-04-21
申请号：US12928813
申请日：2010-12-20
申请人： YongZhong Hu , Sung-Shan Tai
发明人： YongZhong Hu , Sung-Shan Tai
IPC分类号： H01L21/8242
CPC分类号： H01L27/0629 , H01L28/20 , H01L28/60 , Y10S438/957
摘要： A semiconductor device includes a transistor, a capacitor and a resistor wherein the capacitor includes a doped polysilicon layer to function as a bottom conductive layer with a salicide block (SAB) layer as a dielectric layer covered by a Ti/TiN layer as a top conductive layer thus constituting a single polysilicon layer metal-insulator-polysilicon (MIP) structure. While the high sheet rho resistor is also formed on the same single polysilicon layer with differential doping of the polysilicon layer.
摘要翻译：半导体器件包括晶体管，电容器和电阻器，其中电容器包括用作底部导电层的掺杂多晶硅层，其中具有作为顶部导电的Ti / TiN层覆盖的电介质层的硅化物块（SAB）层从而构成单个多晶硅层金属 - 绝缘体 - 多晶硅（MIP）结构。虽然高电阻rho电阻器也形成在同一个多晶硅层上，同时具有多晶硅层的差分掺杂。

12. 发明申请

US20080237777A1 Completely decoupled high voltage and low voltage transistor manufacurting processes 有权
标题翻译：完全去耦的高压和低压晶体管制造工艺
公开(公告)号：US20080237777A1
公开(公告)日：2008-10-02
申请号：US11729408
申请日：2007-03-27
申请人： YongZhong Hu , Sung-Shan Tai
发明人： YongZhong Hu , Sung-Shan Tai
IPC分类号： H01L29/00
CPC分类号： H01L29/7322 , H01L21/823418 , H01L21/823462 , H01L21/823493 , H01L21/823814 , H01L21/823857 , H01L21/823892 , H01L27/088 , H01L27/0922 , H01L29/0878 , H01L29/42368 , H01L29/66689 , H01L29/7816
摘要： A semiconductor wafer includes at least a partially manufactured high voltage transistor covered by a high-voltage low voltage decoupling layer and at least a partially manufactured low voltage transistor with the high-voltage low-voltage decoupling layer etched off for further performance of a low-voltage manufacturing process thereon. The high-voltage low-voltage decoupling layer comprising a high temperature oxide (HTO) oxide layer of about 30-150 Angstroms and a low-pressure chemical vapor deposition (LPCVD) nitride layer.
摘要翻译：半导体晶片包括至少部分制造的由高压低电压去耦层覆盖的高压晶体管和至少部分制造的低压晶体管，其中蚀刻掉高压低压去耦层，电压制造工艺。包括约30-150埃的高温氧化物（HTO）氧化物层和低压化学气相沉积（LPCVD）氮化物层的高压低电压去耦层。

13. 发明授权

US06797568B1 Flash technology transistors and methods for forming the same 有权
标题翻译：闪光技术晶体管及其形成方法相同
公开(公告)号：US06797568B1
公开(公告)日：2004-09-28
申请号：US10302439
申请日：2002-11-21
申请人： YongZhong Hu
发明人： YongZhong Hu
IPC分类号： H01L21336
CPC分类号： H01L27/11526 , H01L27/115 , H01L27/11546 , H01L29/42324
摘要： High voltage (HV), single polysilicon gate NMOS and PMOS transistors in double polysilicon stacked gate flash technology and methods for making the same are described. Specifically, the methods provide for the formation of (and devices comprise) high voltage polysilicon 1 and polysilicon 2 transistors (NMOS and PMOS) in double polysilicon stacked gate flash technology. Different types of transistors (e.g., HV P1 NMOS, HV P1 PMOS, HV P2 NMOS, HV P2 PMOS, LV P1 NMOS, LV P1 PMOS, LV P2 NMOS, LV P2 PMOS) are formed along with a stacked-gate double-poly transistor, thereby providing versatility in flash technology device design. The polysilicon 1 transistors may be salicided without adding to the complexity of the double poly stacked gate fabrication process. In addition, the stacked gate device may include polysilicon 2 only transistors.
摘要翻译：描述了双电晶体堆叠栅极闪存技术中的高电压（HV），单多晶硅栅极NMOS和PMOS晶体管及其制造方法。具体地说，这种方法提供了在双重多晶硅堆叠栅极闪存技术中形成（和器件）高电压多晶硅1和多晶硅2晶体管（NMOS和PMOS）的形成。与层叠栅双极聚合物形成不同类型的晶体管（例如，HV P1 NMOS，HV P1 PMOS，HV P2 NMOS，HV P2 PMOS，LV P1 NMOS，LV P1 PMOS，LV P2 NMOS，LV P2 PMOS）晶体管，从而提供闪存技术设备设计的多功能性。多晶硅1晶体管可以被水银化，而不增加双层多晶硅栅极制造工艺的复杂性。此外，堆叠栅极器件可以仅包括多晶硅2晶体管。

14. 发明授权

US09159828B2 Top drain LDMOS 有权
标题翻译：顶级漏极LDMOS
公开(公告)号：US09159828B2
公开(公告)日：2015-10-13
申请号：US13436308
申请日：2012-03-30
申请人： Shekar Mallikarjunaswamy , John Chen , YongZhong Hu
发明人： Shekar Mallikarjunaswamy , John Chen , YongZhong Hu
IPC分类号： H01L29/78 , H01L29/417 , H01L29/66 , H01L29/06 , H01L29/10 , H01L29/40 , H01L29/45
CPC分类号： H01L29/7835 , H01L29/0692 , H01L29/1083 , H01L29/161 , H01L29/402 , H01L29/4175 , H01L29/41766 , H01L29/456 , H01L29/66659 , H01L29/66681
摘要： In an embodiment, this invention discloses a top-drain lateral diffusion metal oxide field effect semiconductor (TD-LDMOS) device supported on a semiconductor substrate. The TD-LDMOS includes a source electrode disposed on a bottom surface of the semiconductor substrate. The TD-LDMOS further includes a source region and a drain region disposed on two opposite sides of a planar gate disposed on a top surface of the semiconductor substrate wherein the source region is encompassed in a body region constituting a drift region as a lateral current channel between the source region and drain region under the planar gate. The TD-LDMOS further includes at least a trench filled with a conductive material and extending vertically from the body region near the top surface downwardly to electrically contact the source electrode disposed on the bottom surface of the semiconductor substrate.
摘要翻译：在一个实施例中，本发明公开了一种支撑在半导体衬底上的顶排侧向扩散金属氧化物场效应半导体（TD-LDMOS）器件。 TD-LDMOS包括设置在半导体衬底的底表面上的源电极。 TD-LDMOS还包括设置在设置在半导体衬底的顶表面上的平面栅极的两个相对侧上的源极区域和漏极区域，其中源极区域包围在构成漂移区域的体区域中作为横向电流通道在平面栅极下面的源极区域和漏极区域之间。 TD-LDMOS还包括至少填充有导电材料并且从顶表面附近的主体区域向下垂直延伸的沟槽，以电接触设置在半导体衬底的底表面上的源电极。

15. 发明授权

US06794236B1 Eeprom device with improved capacitive coupling and fabrication process 失效
标题翻译： Eeprom器件具有改进的电容耦合和制造工艺
公开(公告)号：US06794236B1
公开(公告)日：2004-09-21
申请号：US10160855
申请日：2002-06-03
申请人： YongZhong Hu
发明人： YongZhong Hu
IPC分类号： H01L218238
CPC分类号： H01L29/42324 , G11C16/0441 , G11C2216/10 , H01L27/115 , H01L27/11521 , H01L27/11558
摘要： An EEPROM device incorporates a partially encapsulated floating gate electrode in order to increase the capacitive coupling between the floating gate electrode and the control gate region of an EEPROM device. The floating gate electrode is partially encapsulated by a capacitor plate that is locally interconnected to the control gate region residing in a semiconductor substrate. The capacitor plate is electrically isolated from the floating gate electrode by a capacitor dielectric layer overlying the floating gate electrode. By partially encapsulating the floating gate electrode with a capacitor plate electrically connected to the control gate region, a high capacitance coupling is obtained between the floating gate electrode and the control gate region, while minimizing the substrate area necessary for fabrication of the capacitor portion of an EEPROM device.
摘要翻译： EEPROM器件包含部分封装的浮栅电极，以便增加浮动栅电极和EEPROM器件的控制栅区之间的电容耦合。浮栅电极被局部地互连到位于半导体衬底中的控制栅极区域的电容器板部分封装。电容器板通过覆盖浮置栅电极的电容器电介质层与浮置栅极电隔离。通过用与控制栅极区域电连接的电容器板部分地封装浮置栅电极，在浮置栅极电极和控制栅极区域之间获得高电容耦合，同时使制造电容器部分所需的衬底面积最小化 EEPROM器件。

16. 发明授权

US06842372B1 EEPROM cell having a floating-gate transistor within a cell well and a process for fabricating the memory cell 失效
标题翻译：具有在单元阱内的浮栅晶体管的EEPROM单元以及用于制造该存储单元的工艺
公开(公告)号：US06842372B1
公开(公告)日：2005-01-11
申请号：US10236829
申请日：2002-09-06
申请人： YongZhong Hu
发明人： YongZhong Hu
IPC分类号： G11C16/04 , H01L21/8247 , H01L27/115
CPC分类号： H01L27/11521 , G11C16/0433 , H01L27/115 , H01L27/11558
摘要： An EEPROM memory device includes a substrate of a first conductivity type having a cell well region of a second conductivity type therein. A floating-gate transistor of the first conductivity type resides in the cell well region and includes a first region separated from a second region by a channel region. A write transistor of the second conductivity type resides in the substrate and includes a first region separated from a second region by a channel region. The second region partially extends into the cell well region and forms a p-n junction with the second region of the floating-gate transistor. The process for fabricating the EEPROM device includes forming the cell well region in the substrate by creating a retrograde doping profile. In operation, the EEPROM device transfers electrons between the cell well region and the floating-gate electrode during both programming and erasing operations.
摘要翻译： EEPROM存储器件包括其中具有第二导电类型的单元阱区的第一导电类型的衬底。第一导电类型的浮栅晶体管位于电池阱区中，并且包括通过沟道区与第二区分离的第一区。第二导电类型的写入晶体管位于衬底中，并且包括通过沟道区域与第二区域分离的第一区域。第二区域部分地延伸到电池阱区域中，并与浮栅晶体管的第二区域形成p-n结。制造EEPROM器件的工艺包括通过产生逆向掺杂分布形成衬底中的电池阱区域。在操作中，EEPROM器件在编程和擦除操作期间在电池阱区域和浮栅电极之间传送电子。

17. 发明授权

US06306713B1 Method for forming self-aligned contacts and local interconnects for salicided gates using a secondary spacer 有权
标题翻译：用于使用次级间隔件形成用于盐水门的自对准接触件和局部互连的方法
公开(公告)号：US06306713B1
公开(公告)日：2001-10-23
申请号：US09799469
申请日：2001-03-05
申请人： YongZhong Hu , Fei Wang , Wenge Yang , Yu Sun , Hiroyuki Kinoshita
发明人： YongZhong Hu , Fei Wang , Wenge Yang , Yu Sun , Hiroyuki Kinoshita
IPC分类号： H01L21336
CPC分类号： H01L21/76897 , H01L21/76895 , H01L2924/3011
摘要： A method of manufacturing a semiconductor device is provided in which multi-layer structures are formed on a semiconductor substrate to form core and peripheral regions. Sidewall spacers are formed around the multi-layer structures and source and drain regions are implanted adjacent the sidewall spacers. The multi-layer structures and the source and drain regions are silicided and a stop layer is deposited over the semiconductor substrate after which a dielectric layer is deposited over the stop layer. A photoresist contact mask is deposited, processed, and used to form core contact openings over the core region, which expose the multi-layer structure in addition to the source and drain regions while covering the peripheral region. Protective secondary sidewall spacers are formed in the core contact openings over the exposed multi-layer structures. A second photoresist contact mask is deposited, processed, and used to form peripheral local interconnect openings over the peripheral region which the source and drain regions and portions of the plurality of multi-layer structures in the peripheral region while covering the core region. A conductive material is deposited over the dielectric layer and in the core contact and peripheral local interconnect openings and is chemical mechanical planarized to remove the conductive material over the dielectric layer so the conductive material is left isolated in the core and peripheral contact openings.
摘要翻译：提供一种制造半导体器件的方法，其中在半导体衬底上形成多层结构以形成芯和周边区域。围绕多层结构形成侧壁间隔物，并且将源极和漏极区域相邻于侧壁间隔物注入。多层结构和源极和漏极区域被硅化，并且在半导体衬底上沉积停止层，之后在停止层上沉积电介质层。光致抗蚀剂接触掩模被沉积，加工并用于在芯部区域上形成芯接触开口，除了覆盖周边区域之外，还暴露多层结构以及源极和漏极区域。保护性次级侧壁间隔件形成在暴露的多层结构上的芯接触开口中。第二光致抗蚀剂接触掩模被沉积，加工并用于在外围区域上形成周边局部互连开口，周边区域是外围区域的源极和漏极区域以及多个多层结构的部分，同时覆盖芯部区域。导电材料沉积在电介质层上，并在芯接触和外围局部互连开口中沉积，并进行化学机械平面化以去除电介质层上的导电材料，使得导电材料在芯和外围接触开口中被隔离。

18. 发明申请

US20120273879A1 TOP DRAIN LDMOS 有权
公开(公告)号：US20120273879A1
公开(公告)日：2012-11-01
申请号：US13436308
申请日：2012-03-30
申请人： Shekar Mallikarjunaswamy , John Chen , YongZhong Hu
发明人： Shekar Mallikarjunaswamy , John Chen , YongZhong Hu
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7835 , H01L29/0692 , H01L29/1083 , H01L29/161 , H01L29/402 , H01L29/4175 , H01L29/41766 , H01L29/456 , H01L29/66659 , H01L29/66681
摘要： In an embodiment, this invention discloses a top-drain lateral diffusion metal oxide field effect semiconductor (TD-LDMOS) device supported on a semiconductor substrate. The TD-LDMOS includes a source electrode disposed on a bottom surface of the semiconductor substrate. The TD-LDMOS further includes a source region and a drain region disposed on two opposite sides of a planar gate disposed on a top surface of the semiconductor substrate wherein the source region is encompassed in a body region constituting a drift region as a lateral current channel between the source region and drain region under the planar gate. The TD-LDMOS further includes at least a trench filled with a conductive material and extending vertically from the body region near the top surface downwardly to electrically contact the source electrode disposed on the bottom surface of the semiconductor substrate.
摘要翻译：在一个实施例中，本发明公开了一种支撑在半导体衬底上的顶排侧向扩散金属氧化物场效应半导体（TD-LDMOS）器件。 TD-LDMOS包括设置在半导体衬底的底表面上的源电极。 TD-LDMOS还包括设置在设置在半导体衬底的顶表面上的平面栅极的两个相对侧上的源极区域和漏极区域，其中源极区域包围在构成漂移区域的体区域中作为横向电流通道在平面栅极下面的源极区域和漏极区域之间。 TD-LDMOS还包括至少填充有导电材料并且从顶表面附近的主体区域向下垂直延伸的沟槽，以电接触设置在半导体衬底的底表面上的源电极。

19. 发明申请

US20060128162A1 Process for fabricating a semiconductor device having an RTCVD layer 审中-公开
标题翻译：制造具有RTCVD层的半导体器件的工艺
公开(公告)号：US20060128162A1
公开(公告)日：2006-06-15
申请号：US11013240
申请日：2004-12-14
申请人： Sunil Mehta , Steven Fong , YongZhong Hu
发明人： Sunil Mehta , Steven Fong , YongZhong Hu
IPC分类号： H01L21/31
CPC分类号： H01L21/0217 , C23C16/345 , H01L21/02271 , H01L21/3185
摘要： A process of fabricating a semiconductor device includes forming a device region including a non-volatile memory element and forming a utility layer overlying the device region, where the utility layer is a dielectric material formed by RTCVD. The utility layer preferably has a hydrogen content below that necessary to reduce the data retention of the non-volatile memory element in the device region. The utility layer can function as one or more of an etch-stop layer, a diffusion barrier layer, or an insulating layer.
摘要翻译：制造半导体器件的工艺包括形成包括非易失性存储元件的器件区域，并且形成覆盖器件区域的实用层，其中该实用层是由RTCVD形成的电介质材料。实用层优选具有低于在装置区域中减少非易失性存储元件的数据保持所需的氢含量。实用层可以用作蚀刻停止层，扩散阻挡层或绝缘层中的一个或多个。

20. 发明授权

US06482699B1 Method for forming self-aligned contacts and local interconnects using decoupled local interconnect process 有权
标题翻译：使用去耦局部互连过程形成自对准触点和局部互连的方法
公开(公告)号：US06482699B1
公开(公告)日：2002-11-19
申请号：US09685972
申请日：2000-10-10
申请人： YongZhong Hu , Fei Wang , Wenge Yang , Yu Sun , Ramkumar Subramanian
发明人： YongZhong Hu , Fei Wang , Wenge Yang , Yu Sun , Ramkumar Subramanian
IPC分类号： H01L21336
CPC分类号： H01L21/76897 , H01L21/76895 , H01L2924/3011
摘要： A method of manufacturing a semiconductor device is provided in which multi-layer structures are formed on a semiconductor substrate to form core and peripheral regions. Sidewall spacers are formed around the multi-layer structures and source and drain regions are implanted adjacent the sidewall spacers and a stop layer is deposited over the semiconductor substrate after which a dielectric layer is deposited over the stop layer. A first and second photoresist contact masks are deposited, processed, and used to respectively etch core and peripheral contact openings. The first and photoresist contact masks are respectively removed after each etching step. A conductive material is deposited over the dielectric layer and in the core and peripheral contact openings and is chemical mechanical planarized to remove the conductive material over the dielectric layer so the conductive material is left isolated in the core and peripheral contact openings with core contacts to the source/drain regions and peripheral contacts to the local interconnect gate contacts of the multi-layer structures and the source/drain regions.
摘要翻译：提供一种制造半导体器件的方法，其中在半导体衬底上形成多层结构以形成芯和周边区域。在多层结构周围形成侧壁间隔物，并且将源极和漏极区域相邻于侧壁间隔物注入，并且在半导体衬底上沉积停止层，之后在停止层上沉积电介质层。第一和第二光致抗蚀剂接触掩模被沉积，处理并用于分别蚀刻芯部和外围接触开口。在每个蚀刻步骤之后分别去除第一和光致抗蚀剂接触掩模。导电材料沉积在电介质层上以及芯和外围接触开口中，并进行化学机械平面化以去除电介质层上的导电材料，因此导电材料在核心和外围接触开口中被隔离，其核心接触到源极/漏极区域和周边接触到多层结构和源极/漏极区域的局部互连栅极触点。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式