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1. 发明授权

US07824977B2 Completely decoupled high voltage and low voltage transistor manufacturing processes 有权
标题翻译：完全去耦的高压和低压晶体管制造工艺
公开(公告)号：US07824977B2
公开(公告)日：2010-11-02
申请号：US11729408
申请日：2007-03-27
申请人： YongZhong Hu , Sung-Shan Tai
发明人： YongZhong Hu , Sung-Shan Tai
IPC分类号： H01L29/00
CPC分类号： H01L29/7322 , H01L21/823418 , H01L21/823462 , H01L21/823493 , H01L21/823814 , H01L21/823857 , H01L21/823892 , H01L27/088 , H01L27/0922 , H01L29/0878 , H01L29/42368 , H01L29/66689 , H01L29/7816
摘要： A semiconductor wafer includes at least a partially manufactured high voltage transistor covered by a high-voltage low voltage decoupling layer and at least a partially manufactured low voltage transistor with the high-voltage low-voltage decoupling layer etched off for further performance of a low-voltage manufacturing process thereon. The high-voltage low-voltage decoupling layer comprising a high temperature oxide (HTO) oxide layer of about 30-150 Angstroms and a low-pressure chemical vapor deposition (LPCVD) nitride layer.
摘要翻译：半导体晶片包括至少部分制造的由高压低电压去耦层覆盖的高压晶体管和至少部分制造的低压晶体管，其中蚀刻掉高压低压去耦层，电压制造工艺。包括约30-150埃的高温氧化物（HTO）氧化物层和低压化学气相沉积（LPCVD）氮化物层的高压低电压去耦层。

2. 发明授权

US07805687B2 One-time programmable (OTP) memory cell 有权
标题翻译：一次性可编程（OTP）存储单元
公开(公告)号：US07805687B2
公开(公告)日：2010-09-28
申请号：US11541369
申请日：2006-09-30
申请人： YongZhong Hu , Yu Cheng Chang , Sung-Shan Tai
发明人： YongZhong Hu , Yu Cheng Chang , Sung-Shan Tai
IPC分类号： G06F17/50
CPC分类号： G11C17/16 , G11C17/18 , H01L27/112 , H01L27/11206
摘要： A method of performing a programming, testing and trimming operation is disclosed in this invention. The method includes a step of applying a programming circuit for programming an OTP memory for probing and sensing one of three different states of the OTP memory for carrying out a trimming operation using one of the three states of the OTP memory whereby a higher utilization of OTP memory cells is achieved. Selecting and programming two conductive circuits of the OTP into two different operational characteristics thus enables the storing and sensing one of the three different states of the OTP memory. These two conductive circuits may include two different transistors for programming into a linear resistor and a nonlinear resistor with different current conducting characteristics. The programming processes include application of a high voltage and different programming currents thus generating different operational characteristics of these two transistors.
摘要翻译：在本发明中公开了执行编程，测试和修整操作的方法。该方法包括应用用于对OTP存储器进行编程的编程电路的步骤，用于探测和感测OTP存储器的三种不同状态之一，以使用OTP存储器的三种状态之一进行修整操作，由此OTP的较高利用率实现了存储单元。将OTP的两个导电电路选择和编程成两个不同的操作特性，因此能够存储和感测OTP存储器的三种不同状态之一。这两个导电电路可以包括用于编程成线性电阻器的两个不同晶体管和具有不同电流传导特性的非线性电阻器。编程过程包括应用高电压和不同的编程电流，从而产生这两个晶体管的不同操作特性。

3. 发明申请

US20120028427A1 Split gate with different gate materials and work functions to reduce gate resistance of ultra high density MOSFET 有权
标题翻译：分闸具有不同的栅极材料和工作功能，可降低超高密度MOSFET的栅极电阻
公开(公告)号：US20120028427A1
公开(公告)日：2012-02-02
申请号：US13200882
申请日：2011-10-04
申请人： Sung-Shan Tai , YongZhong Hu
发明人： Sung-Shan Tai , YongZhong Hu
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L29/407 , H01L29/41766 , H01L29/4958 , H01L29/66727 , H01L29/66734
摘要： This invention discloses a trenched metal oxide semiconductor field effect transistor (MOSFET) cell. The trenched MOSFET cell includes a trenched gate opened from a top surface of the semiconductor substrate surrounded by a source region encompassed in a body region above a drain region disposed on a bottom surface of a substrate. The trenched gate further includes at least two mutually insulated trench-filling segments each filled with materials of different work functions. In an exemplary embodiment, the trenched gate includes a polysilicon segment at a bottom portion of the trenched gate and a metal segment at a top portion of the trenched gate.
摘要翻译：本发明公开了一种沟槽金属氧化物半导体场效应晶体管（MOSFET）单元。沟槽MOSFET单元包括从半导体衬底的顶表面开口的沟槽栅极，该沟槽被包围在布置在衬底底表面上的漏区以上的体区中的源极区围绕。沟槽栅还包括至少两个相互绝缘的沟槽填充段，每个填充段具有不同功函数的材料。在示例性实施例中，沟槽栅极包括在沟槽栅极的底部处的多晶硅段和在沟槽栅极顶部的金属段。

4. 发明授权

US07855422B2 Formation of high sheet resistance resistors and high capacitance capacitors by a single polysilicon process 有权
标题翻译：通过单个多晶硅工艺形成高电阻电阻器和高容量电容器
公开(公告)号：US07855422B2
公开(公告)日：2010-12-21
申请号：US11444852
申请日：2006-05-31
申请人： YongZhong Hu , Sung-Shan Tai
发明人： YongZhong Hu , Sung-Shan Tai
IPC分类号： H01L29/76
CPC分类号： H01L27/0629 , H01L28/20 , H01L28/60 , Y10S438/957
摘要： A semiconductor device includes a transistor, a capacitor and a resistor wherein the capacitor includes a doped polysilicon layer to function as a bottom conductive layer with a salicide block (SAB) layer as a dielectric layer covered by a Ti/TiN layer as a top conductive layer thus constituting a single polysilicon layer metal-insulator-polysilicon (MIP) structure. While the high sheet rho resistor is also formed on the same single polysilicon layer with differential doping of the polysilicon layer.
摘要翻译：半导体器件包括晶体管，电容器和电阻器，其中电容器包括用作底部导电层的掺杂多晶硅层，其中具有作为顶部导电的Ti / TiN层覆盖的电介质层的硅化物块（SAB）层从而构成单个多晶硅层金属 - 绝缘体 - 多晶硅（MIP）结构。虽然高片rho电阻也形成在同一个多晶硅层上，多晶硅层的差分掺杂。

5. 发明授权

US08524558B2 Split gate with different gate materials and work functions to reduce gate resistance of ultra high density MOSFET 有权
标题翻译：分闸具有不同的栅极材料和工作功能，可降低超高密度MOSFET的栅极电阻
公开(公告)号：US08524558B2
公开(公告)日：2013-09-03
申请号：US13200882
申请日：2011-10-04
申请人： Sung-Shan Tai , YongZhong Hu
发明人： Sung-Shan Tai , YongZhong Hu
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L29/407 , H01L29/41766 , H01L29/4958 , H01L29/66727 , H01L29/66734
摘要： This invention discloses a trenched metal oxide semiconductor field effect transistor (MOSFET) cell. The trenched MOSFET cell includes a trenched gate opened from a top surface of the semiconductor substrate surrounded by a source region encompassed in a body region above a drain region disposed on a bottom surface of a substrate. The trenched gate further includes at least two mutually insulated trench-filling segments each filled with materials of different work functions. In an exemplary embodiment, the trenched gate includes a polysilicon segment at a bottom portion of the trenched gate and a metal segment at a top portion of the trenched gate.
摘要翻译：本发明公开了一种沟槽金属氧化物半导体场效应晶体管（MOSFET）单元。沟槽MOSFET单元包括从半导体衬底的顶表面开口的沟槽栅极，该沟槽被包围在布置在衬底底表面上的漏区以上的体区中的源极区围绕。沟槽栅还包括至少两个相互绝缘的沟槽填充段，每个填充段具有不同功函数的材料。在示例性实施例中，沟槽栅极包括在沟槽栅极的底部处的多晶硅段和在沟槽栅极顶部的金属段。

6. 发明授权

US08058687B2 Split gate with different gate materials and work functions to reduce gate resistance of ultra high density MOSFET 有权
标题翻译：分闸具有不同的栅极材料和工作功能，可降低超高密度MOSFET的栅极电阻
公开(公告)号：US08058687B2
公开(公告)日：2011-11-15
申请号：US11700688
申请日：2007-01-30
申请人： Sung-Shan Tai , YongZhong Hu
发明人： Sung-Shan Tai , YongZhong Hu
IPC分类号： H01L29/66
CPC分类号： H01L29/7813 , H01L29/407 , H01L29/41766 , H01L29/4958 , H01L29/66727 , H01L29/66734
摘要： This invention discloses a trenched metal oxide semiconductor field effect transistor (MOSFET) cell. The trenched MOSFET cell includes a trenched gate opened from a top surface of the semiconductor substrate surrounded by a source region encompassed in a body region above a drain region disposed on a bottom surface of a substrate. The trenched gate further includes at least two mutually insulated trench-filling segments each filled with materials of different work functions. In an exemplary embodiment, the trenched gate includes a polysilicon segment at a bottom portion of the trenched gate and a metal segment at a top portion of the trenched gate.
摘要翻译：本发明公开了一种沟槽金属氧化物半导体场效应晶体管（MOSFET）单元。沟槽MOSFET单元包括从半导体衬底的顶表面开口的沟槽栅极，该沟槽被包围在布置在衬底底表面上的漏区以上的体区中的源极区围绕。沟槽栅还包括至少两个相互绝缘的沟槽填充段，每个填充段具有不同功函数的材料。在示例性实施例中，沟槽栅极包括在沟槽栅极的底部处的多晶硅段和在沟槽栅极顶部的金属段。

7. 发明申请

US20080179668A1 Split gate with different gate materials and work functions to reduce gate resistance of ultra high density MOSFET 有权
标题翻译：分闸具有不同的栅极材料和工作功能，可降低超高密度MOSFET的栅极电阻
公开(公告)号：US20080179668A1
公开(公告)日：2008-07-31
申请号：US11700688
申请日：2007-01-30
申请人： Sung-Shan Tai , YongZhong Hu
发明人： Sung-Shan Tai , YongZhong Hu
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7813 , H01L29/407 , H01L29/41766 , H01L29/4958 , H01L29/66727 , H01L29/66734
摘要： This invention discloses a trenched metal oxide semiconductor field effect transistor (MOSFET) cell. The trenched MOSFET cell includes a trenched gate opened from a top surface of the semiconductor substrate surrounded by a source region encompassed in a body region above a drain region disposed on a bottom surface of a substrate. The trenched gate further includes at least two mutually insulated trench-filling segments each filled with materials of different work functions. In an exemplary embodiment, the trenched gate includes a polysilicon segment at a bottom portion of the trenched gate and a metal segment at a top portion of the trenched gate.
摘要翻译：本发明公开了一种沟槽金属氧化物半导体场效应晶体管（MOSFET）单元。沟槽MOSFET单元包括从半导体衬底的顶表面开口的沟槽栅极，该沟槽被包围在布置在衬底底表面上的漏区以上的体区中的源极区围绕。沟槽栅还包括至少两个相互绝缘的沟槽填充段，每个填充段具有不同功函数的材料。在示例性实施例中，沟槽栅极包括在沟槽栅极的底部处的多晶硅段和在沟槽栅极顶部的金属段。

8. 发明申请

US20070281418A1 Formation of high sheet resistance resistors and high capacitance capacitors by a single polysilicon process 有权
标题翻译：通过单个多晶硅工艺形成高电阻电阻器和高容量电容器
公开(公告)号：US20070281418A1
公开(公告)日：2007-12-06
申请号：US11444852
申请日：2006-05-31
申请人： YongZhong Hu , Sung-Shan Tai
发明人： YongZhong Hu , Sung-Shan Tai
IPC分类号： H01L21/8244
CPC分类号： H01L27/0629 , H01L28/20 , H01L28/60 , Y10S438/957
摘要： A semiconductor device includes a transistor, a capacitor and a resistor wherein the capacitor includes a doped polysilicon layer to function as a bottom conductive layer with a salicide block (SAB) layer as a dielectric layer covered by a Ti/TiN layer as a top conductive layer thus constituting a single polysilicon layer metal-insulator-polysilicon (MIP) structure. While the high sheet rho resistor is also formed on the same single polysilicon layer with differential doping of the polysilicon layer.
摘要翻译：半导体器件包括晶体管，电容器和电阻器，其中电容器包括用作底部导电层的掺杂多晶硅层，其中具有作为顶部导电的Ti / TiN层覆盖的电介质层的硅化物块（SAB）层从而构成单个多晶硅层金属 - 绝缘体 - 多晶硅（MIP）结构。虽然高片rho电阻也形成在同一个多晶硅层上，多晶硅层的差分掺杂。

9. 发明申请

US20070069297A1 Tri-states one-time programmable memory (OTP) cell 有权
标题翻译：三态一次可编程存储器（OTP）单元
公开(公告)号：US20070069297A1
公开(公告)日：2007-03-29
申请号：US11541369
申请日：2006-09-30
申请人： YongZhong Hu , Yu Chang , Sung-Shan Tai
发明人： YongZhong Hu , Yu Chang , Sung-Shan Tai
IPC分类号： H01L23/62
CPC分类号： G11C17/16 , G11C17/18 , H01L27/112 , H01L27/11206
摘要： A method of performing a programming, testing and trimming operation is disclosed in this invention. The method includes a step of applying a programming circuit for programming an OTP memory for probing and sensing one of three different states of the OTP memory for carrying out a trimming operation using one of the three states of the OTP memory whereby a higher utilization of OTP memory cells is achieved. Selecting and programming two conductive circuits of the OTP into two different operational characteristics thus enables the storing and sensing one of the three different states of the OTP memory. These two conductive circuits may include two different transistors for programming into a linear resistor and a nonlinear resistor with different current conducting characteristics. The programming processes include application of a high voltage and different programming currents thus generating different operational characteristics of these two transistors.
摘要翻译：在本发明中公开了执行编程，测试和修整操作的方法。该方法包括应用用于对OTP存储器进行编程的编程电路的步骤，用于探测和感测OTP存储器的三种不同状态之一，以使用OTP存储器的三种状态之一进行修整操作，由此OTP的较高利用率实现了存储单元。将OTP的两个导电电路选择和编程成两个不同的操作特性，因此能够存储和感测OTP存储器的三种不同状态之一。这两个导电电路可以包括用于编程成线性电阻器的两个不同晶体管和具有不同电流传导特性的非线性电阻器。编程过程包括应用高电压和不同的编程电流，从而产生这两个晶体管的不同操作特性。

10. 发明授权

US08835251B2 Formation of high sheet resistance resistors and high capacitance capacitors by a single polysilicon process 有权
标题翻译：通过单个多晶硅工艺形成高电阻电阻器和高容量电容器
公开(公告)号：US08835251B2
公开(公告)日：2014-09-16
申请号：US12928813
申请日：2010-12-20
申请人： YongZhong Hu , Sung-Shan Tai
发明人： YongZhong Hu , Sung-Shan Tai
IPC分类号： H01L27/06 , H01L49/02
CPC分类号： H01L27/0629 , H01L28/20 , H01L28/60 , Y10S438/957
摘要： A semiconductor device includes a transistor, a capacitor and a resistor wherein the capacitor includes a doped polysilicon layer to function as a bottom conductive layer with a salicide block (SAB) layer as a dielectric layer covered by a Ti/TiN layer as a top conductive layer thus constituting a single polysilicon layer metal-insulator-polysilicon (MIP) structure. While the high sheet rho resistor is also formed on the same single polysilicon layer with differential doping of the polysilicon layer.
摘要翻译：半导体器件包括晶体管，电容器和电阻器，其中电容器包括用作底部导电层的掺杂多晶硅层，其中具有作为顶部导电的Ti / TiN层覆盖的电介质层的硅化物块（SAB）层从而构成单个多晶硅层金属 - 绝缘体 - 多晶硅（MIP）结构。虽然高片rho电阻也形成在同一个多晶硅层上，多晶硅层的差分掺杂。

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