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1. 发明授权

US09159828B2 Top drain LDMOS 有权
标题翻译：顶级漏极LDMOS
公开(公告)号：US09159828B2
公开(公告)日：2015-10-13
申请号：US13436308
申请日：2012-03-30
申请人： Shekar Mallikarjunaswamy , John Chen , YongZhong Hu
发明人： Shekar Mallikarjunaswamy , John Chen , YongZhong Hu
IPC分类号： H01L29/78 , H01L29/417 , H01L29/66 , H01L29/06 , H01L29/10 , H01L29/40 , H01L29/45
CPC分类号： H01L29/7835 , H01L29/0692 , H01L29/1083 , H01L29/161 , H01L29/402 , H01L29/4175 , H01L29/41766 , H01L29/456 , H01L29/66659 , H01L29/66681
摘要： In an embodiment, this invention discloses a top-drain lateral diffusion metal oxide field effect semiconductor (TD-LDMOS) device supported on a semiconductor substrate. The TD-LDMOS includes a source electrode disposed on a bottom surface of the semiconductor substrate. The TD-LDMOS further includes a source region and a drain region disposed on two opposite sides of a planar gate disposed on a top surface of the semiconductor substrate wherein the source region is encompassed in a body region constituting a drift region as a lateral current channel between the source region and drain region under the planar gate. The TD-LDMOS further includes at least a trench filled with a conductive material and extending vertically from the body region near the top surface downwardly to electrically contact the source electrode disposed on the bottom surface of the semiconductor substrate.
摘要翻译：在一个实施例中，本发明公开了一种支撑在半导体衬底上的顶排侧向扩散金属氧化物场效应半导体（TD-LDMOS）器件。 TD-LDMOS包括设置在半导体衬底的底表面上的源电极。 TD-LDMOS还包括设置在设置在半导体衬底的顶表面上的平面栅极的两个相对侧上的源极区域和漏极区域，其中源极区域包围在构成漂移区域的体区域中作为横向电流通道在平面栅极下面的源极区域和漏极区域之间。 TD-LDMOS还包括至少填充有导电材料并且从顶表面附近的主体区域向下垂直延伸的沟槽，以电接触设置在半导体衬底的底表面上的源电极。

2. 发明申请

US20120273879A1 TOP DRAIN LDMOS 有权
公开(公告)号：US20120273879A1
公开(公告)日：2012-11-01
申请号：US13436308
申请日：2012-03-30
申请人： Shekar Mallikarjunaswamy , John Chen , YongZhong Hu
发明人： Shekar Mallikarjunaswamy , John Chen , YongZhong Hu
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7835 , H01L29/0692 , H01L29/1083 , H01L29/161 , H01L29/402 , H01L29/4175 , H01L29/41766 , H01L29/456 , H01L29/66659 , H01L29/66681
摘要： In an embodiment, this invention discloses a top-drain lateral diffusion metal oxide field effect semiconductor (TD-LDMOS) device supported on a semiconductor substrate. The TD-LDMOS includes a source electrode disposed on a bottom surface of the semiconductor substrate. The TD-LDMOS further includes a source region and a drain region disposed on two opposite sides of a planar gate disposed on a top surface of the semiconductor substrate wherein the source region is encompassed in a body region constituting a drift region as a lateral current channel between the source region and drain region under the planar gate. The TD-LDMOS further includes at least a trench filled with a conductive material and extending vertically from the body region near the top surface downwardly to electrically contact the source electrode disposed on the bottom surface of the semiconductor substrate.
摘要翻译：在一个实施例中，本发明公开了一种支撑在半导体衬底上的顶排侧向扩散金属氧化物场效应半导体（TD-LDMOS）器件。 TD-LDMOS包括设置在半导体衬底的底表面上的源电极。 TD-LDMOS还包括设置在设置在半导体衬底的顶表面上的平面栅极的两个相对侧上的源极区域和漏极区域，其中源极区域包围在构成漂移区域的体区域中作为横向电流通道在平面栅极下面的源极区域和漏极区域之间。 TD-LDMOS还包括至少填充有导电材料并且从顶表面附近的主体区域向下垂直延伸的沟槽，以电接触设置在半导体衬底的底表面上的源电极。

3. 发明授权

US09118322B2 Low leakage dynamic bi-directional body-snatching (LLDBBS) scheme for high speed analog switches 有权
标题翻译：用于高速模拟开关的低泄漏动态双向身体抢夺（LLDBBS）方案
公开(公告)号：US09118322B2
公开(公告)日：2015-08-25
申请号：US13034518
申请日：2011-02-24
申请人： Mohammad Suhaib Husain , Shekar Mallikarjunaswamy
发明人： Mohammad Suhaib Husain , Shekar Mallikarjunaswamy
IPC分类号： H03K17/16 , H03K17/14
CPC分类号： H03K17/145 , H03K2217/0036 , H03K2217/0054
摘要： A bidirectional switch device includes a main pass field effect transistor (FET) connected to an input node and an output node. A body region of the first main pass transistor is tied to a voltage substantially halfway between the voltage at the input node side of the first main pass transistor and the voltage at the output node side of the transistor when the first main pass transistor is in an ON state.
摘要翻译：双向开关装置包括连接到输入节点的主通道场效应晶体管（FET）和输出节点。当第一主通道晶体管处于第一主通道晶体管的输入节点侧的电压和晶体管的输出节点侧的电压之间时，第一主通道晶体管的体区被连接到基本上位于第一主通道晶体管的输入节点侧的电压之间的电压 ON状态。

4. 发明授权

US08791723B2 Three-dimensional high voltage gate driver integrated circuit 有权
公开(公告)号：US08791723B2
公开(公告)日：2014-07-29
申请号：US13588429
申请日：2012-08-17
申请人： Shekar Mallikarjunaswamy
发明人： Shekar Mallikarjunaswamy
IPC分类号： H01L21/98 , H03K3/353
CPC分类号： H01L21/8234 , H01L21/8221 , H01L27/0629 , H01L27/0688 , H01L29/66681 , H01L2924/0002 , H03K17/687 , H01L2924/00
摘要： A three-dimensional (3D) gate driver integrated circuit includes a high-side integrated circuit stacked on a low-side integrated circuit where the high-side integrated circuit and the low-side integrated circuit are interconnected using through-silicon vias (TSV). As thus formed, the high-side integrated circuit and the low-side integrated circuit can be formed without termination regions and without buried layers. The 3D gate driver integrated circuit improves ease of high voltage integration and improves the ruggedness and reliability of the gate driver integrated circuit.

5. 发明授权

US08643137B2 Short channel lateral MOSFET 有权
标题翻译：短沟道横向MOSFET
公开(公告)号：US08643137B2
公开(公告)日：2014-02-04
申请号：US13488350
申请日：2012-06-04
申请人： Shekar Mallikarjunaswamy , Amit Paul
发明人： Shekar Mallikarjunaswamy , Amit Paul
IPC分类号： H01L23/58 , H01L29/66
CPC分类号： H01L21/26513 , H01L21/26586 , H01L29/0878 , H01L29/1095 , H01L29/42368 , H01L29/66681 , H01L29/7816 , H01L2924/0002 , H01L2924/00
摘要： A short channel Lateral MOSFET (LMOS) and method are disclosed with interpenetrating drain-body protrusions (IDBP) for reducing channel-on resistance while maintaining high punch-through voltage. The LMOS includes lower device bulk layer; upper source and upper drain region both located atop lower device bulk layer; both upper source and upper drain region are in contact with an intervening upper body region atop lower device bulk layer; both upper drain and upper body region are shaped to form a drain-body interface; the drain-body interface has an IDBP structure with a surface drain protrusion lying atop a buried body protrusion while revealing a top body surface area of the upper body region; gate oxide-gate electrode bi-layer disposed atop the upper body region forming an LMOS with a short channel length defined by the horizontal length of the top body surface area delineated between the upper source region and the upper drain region.
摘要翻译：公开了一种短沟道横向MOSFET（LMOS）和方法，其具有用于降低通道导通电阻同时保持高穿透电压的互穿漏极体突起（IDBP）。 LMOS包括较低的器件体积层; 上部源极和上部漏极区域位于下部器件体层的顶部; 上部源极和上部漏极区都与下部器件本体层之间的中间上部区域接触; 上排水区和上体区均形成排水体界面; 排水体接口具有IDBP结构，其中表面排出突起位于掩埋体突起的顶部，同时露出上身体区域的顶部体表面积; 栅极氧化物栅极电极双层，其设置在形成LMOS的上部主体区域的顶部，其具有由在上部源区域和上部漏极区域之间描绘的顶部体表面积的水平长度限定的短沟道长度。

6. 发明申请

US20130016446A1 CIRCUIT CONFIGURATIONS TO REDUCE SNAPBACK OF A TRANSIENT VOLTAGE SUPPRESSOR 有权
标题翻译：电路配置减少瞬态电压抑制器的反应
公开(公告)号：US20130016446A1
公开(公告)日：2013-01-17
申请号：US13351186
申请日：2012-01-16
申请人： Shekar Mallikarjunaswamy
发明人： Shekar Mallikarjunaswamy
IPC分类号： H01L21/332 , H02H9/04
CPC分类号： H01L27/0262 , H01L29/87
摘要： This invention discloses a transient voltage suppressing (TVS) circuit that includes a triggering Zener diode connected between an emitter and a collector of a bipolar-junction transistor (BJT) wherein the Zener diode having a reverse breakdown voltage BV less than or equal to a BVceo of the BJT where BVceo stands for a collector to emitter breakdown voltage with base left open. The TVS circuit further includes a rectifier connected in parallel to the BJT for triggering a rectified current through the rectifier for further limiting an increase of a reverse blocking voltage. The triggering Zener diode, the BJT and the rectifier are formed in a semiconductor substrate by implanting and configuring dopant regions of a first and a second conductivity types in an N-well and a P-well whereby the TVS can be formed in parallel as part of the manufacturing processes of the electronic device.
摘要翻译：本发明公开了一种瞬态电压抑制（TVS）电路，其包括连接在双极结型晶体管（BJT）的发射极和集电极之间的触发齐纳二极管，其中齐纳二极管的反向击穿电压BV小于或等于BVceo 的BJT，其中BVceo代表基极左开路的集电极到发射极击穿电压。 TVS电路还包括与BJT并联连接的整流器，用于触发整流器的整流电流，用于进一步限制反向阻断电压的增加。触发齐纳二极管，BJT和整流器通过在N阱和P阱中注入和配置第一和第二导电类型的掺杂区域而形成在半导体衬底中，由此TVS可以平行地形成为部分的电子设备的制造过程。

7. 发明申请

US20120187481A1 Vertical Trench LDMOS Transistor 有权
标题翻译：垂直沟槽LDMOS晶体管
公开(公告)号：US20120187481A1
公开(公告)日：2012-07-26
申请号：US13440929
申请日：2012-04-05
申请人： Shekar Mallikarjunaswamy
发明人： Shekar Mallikarjunaswamy
IPC分类号： H01L27/088
CPC分类号： H01L29/407 , H01L21/823412 , H01L21/823807 , H01L21/8249 , H01L27/0617 , H01L27/0623 , H01L27/092 , H01L29/0634 , H01L29/0649 , H01L29/0696 , H01L29/0821 , H01L29/0878 , H01L29/1095 , H01L29/408 , H01L29/4175 , H01L29/42356 , H01L29/4236 , H01L29/42368 , H01L29/732 , H01L29/7393 , H01L29/7813 , H01L29/7816 , H01L29/7817 , H01L29/7823 , H01L29/7825 , H01L29/7831
摘要： A vertical trench LDMOS transistor includes a semiconductor layer of a first conductivity type; a first trench formed in the semiconductor layer and filled with a trench dielectric and a trench gate is formed in the first trench; a body region of a second conductivity type formed in the semiconductor layer adjacent the first trench; a source region formed in the body region and adjacent the first trench; a planar gate insulated from the semiconductor layer by a second gate dielectric layer and overlying the body region; and a drain drift region formed in the semiconductor layer. The planar gate forms a lateral channel in the body region between the source region and the drain drift region, and the trench gate in the first trench forms a vertical channel in the body region along the sidewall of the first trench between the source region and the semiconductor layer.
摘要翻译：垂直沟槽LDMOS晶体管包括第一导电类型的半导体层; 在所述第一沟槽中形成形成在所述半导体层中且填充有沟槽电介质和沟槽栅极的第一沟槽; 形成在与所述第一沟槽相邻的所述半导体层中的第二导电类型的体区; 源区域，其形成在所述主体区域中并且与所述第一沟槽相邻; 平面栅极，通过第二栅极介电层与半导体层绝缘并覆盖在主体区域上; 以及形成在半导体层中的漏极漂移区。平面栅极在源极区域和漏极漂移区域之间的主体区域中形成横向沟道，并且第一沟槽中的沟槽栅极沿着源极区域和源极区域之间的第一沟槽的侧壁在主体区域中形成垂直沟道半导体层。

8. 发明授权

US07919817B2 Electrostatic discharge (ESD) protection applying high voltage lightly doped drain (LDD) CMOS technologies 有权
标题翻译：使用高电压轻掺杂漏极（LDD）CMOS技术的静电放电（ESD）保护
公开(公告)号：US07919817B2
公开(公告)日：2011-04-05
申请号：US12152805
申请日：2008-05-16
申请人： Shekar Mallikarjunaswamy
发明人： Shekar Mallikarjunaswamy
IPC分类号： H01L23/62
CPC分类号： H01L27/0251
摘要： An electrostatic discharge (ESD) protection circuit includes a triggering diode that includes a junction between a P-grade (PG) region and an N-well. The PG region has a dopant profile equivalent to a P-drain dopant profile of a PMOS transistor having a breakdown voltage represented by V whereby the triggering diode for conducting a current when a voltage greater than the breakdown voltage V is applied. In an exemplary embodiment, the dopant profile of the PG region includes two dopant implant profiles that include a shallow implant profile with a higher dopant concentration and a deep implant profile with a lower dopant concentration.
摘要翻译：静电放电（ESD）保护电路包括触发二极管，其包括P级（PG）区域和N阱之间的连接点。 PG区域具有等效于具有由V表示的击穿电压的PMOS晶体管的P漏极掺杂物轮廓的掺杂物轮廓，由此施加大于击穿电压V的电压时用于传导电流的触发二极管。在示例性实施例中，PG区域的掺杂物分布包括两个掺杂剂注入分布，其包括具有较高掺杂剂浓度的较浅注入分布和具有较低掺杂浓度的深注入分布。

9. 发明授权

US07843019B2 Seal ring for mixed circuitry semiconductor devices 有权
标题翻译：用于混合电路半导体器件的密封环
公开(公告)号：US07843019B2
公开(公告)日：2010-11-30
申请号：US11515172
申请日：2006-08-31
申请人： Shekar Mallikarjunaswamy , Martin Alter
发明人： Shekar Mallikarjunaswamy , Martin Alter
IPC分类号： H01L29/66
CPC分类号： H01L21/761 , H01L21/765 , H01L21/823481 , H01L23/585 , H01L2924/0002 , H01L2924/00
摘要： In mixed-component, mixed-signal, semiconductor devices, selective seal ring isolation from the substrate and its electrical potential is provided in order to segregate noise sensitive circuitry from electrical noise generated by electrically noisy circuitry. Appropriate predetermined sections of such a mixed use chip are isolated from the substrate through a non-ohmic contact with the substrate without compromising reliability of the chip's isolation from scribe region contamination.
摘要翻译：在混合组件，混合信号半导体器件中，提供了与衬底的选择性密封环隔离及其电位，以便将噪声敏感电路与由电噪声电路产生的电噪声隔离。这种混合使用芯片的适当的预定部分通过与基板的非欧姆接触而从基板隔离，而不损害芯片与划线区域污染的隔离的可靠性。

10. 发明授权

US07608907B2 LDMOS gate controlled schottky diode 有权
标题翻译： LDMOS门控肖特基二极管
公开(公告)号：US07608907B2
公开(公告)日：2009-10-27
申请号：US11031201
申请日：2005-01-06
申请人： Shekar Mallikarjunaswamy
发明人： Shekar Mallikarjunaswamy
IPC分类号： H01L21/336
CPC分类号： H01L27/0727 , H01L29/782 , H01L29/872
摘要： An improved diode is disclosed. The diode comprises a Schottky diode and a LDMOS device coupled in series with the Schottky diode. In a preferred embodiment, a forward current from the Schottky diode is allowed to flow through the channel of a depletion mode LDMOS that allows gate control over Schottky forward current. Integrating the Schottky diode into the drain of the depletion mode LDMOS forms the device structure.
摘要翻译：公开了一种改进的二极管。二极管包括与肖特基二极管串联耦合的肖特基二极管和LDMOS器件。在优选实施例中，来自肖特基二极管的正向电流被允许流过耗能模式LDMOS的沟道，其允许栅极控制肖特基正向电流。将肖特基二极管集成到耗尽型LDMOS的漏极中形成器件结构。

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