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11. 发明授权

US06320800B1 Semiconductor memory and nonvolatile semiconductor memory having redundant circuitry for replacing defective memory cell 有权
标题翻译：具有用于替换有缺陷的存储单元的冗余电路的半导体存储器和非易失性半导体存储器
公开(公告)号：US06320800B1
公开(公告)日：2001-11-20
申请号：US09583540
申请日：2000-06-01
申请人： Hidetoshi Saito , Masao Kuriyama , Yasuhiko Honda , Hideo Kato
发明人： Hidetoshi Saito , Masao Kuriyama , Yasuhiko Honda , Hideo Kato
IPC分类号： G11C700
CPC分类号： G11C29/78 , G11C8/06 , G11C16/26 , G11C2216/22
摘要： Redundant cell arrays 201 of a plurality of columns are provided for replacing a defective bit line of a memory cell array 101. Each of the redundant cell arrays 201 is provided with a redundant sense amplifier circuit 105 separately from a sense amplifier circuit 103 of the memory cell array 101. A defective address storing circuit 108 stores a defective address of the memory cell array 101, an input/output terminal, to and from which data corresponding to the defective address are. to be inputted and outputted, and a column set number of the redundant cell array which is to be replaced in accordance with the input/output terminal. An address comparator circuit 109 detects the coincidence of an input address with the defective address. A switch circuit 112 is controlled by the coincidence detection output to switch one corresponding to the defective address of a sense amplifier circuit to one selected by the set number in the redundant sense amplifier circuit, to connect it to a data input/output buffer 113. Thus, it is possible to provide a semiconductor memory capable of effectively relieving a plurality of defective columns and a defect in a boundary region in column directions of the cell array.
摘要翻译：多个列的冗余单元阵列201被提供用于替换存储单元阵列101的有缺陷的位线。每个冗余单元阵列201设置有与存储器的读出放大器电路103分离的冗余读出放大器电路105 单元阵列101.缺陷地址存储电路108存储与缺陷地址对应的数据的存储单元阵列101的缺陷地址，输入/输出端。输入和输出，以及根据输入/输出端子要替换的冗余单元阵列的列组号。地址比较电路109检测输入地址与缺陷地址的一致性。开关电路112由重合检测输出控制，将与读出放大器电路的缺陷地址对应的一个切换到由冗余读出放大器电路中的设定数字选择的一个，将其连接到数据输入/输出缓冲器113。因此，可以提供能够有效地消除多个缺陷列的半导体存储器和单元阵列的列方向上的边界区域中的缺陷。

12. 发明授权

US06532181B2 Semiconductor memory device having redundant circuitry for replacing defective memory cell 有权
标题翻译：具有用于替换有缺陷的存储单元的冗余电路的半导体存储器件
公开(公告)号：US06532181B2
公开(公告)日：2003-03-11
申请号：US09963404
申请日：2001-09-27
申请人： Hidetoshi Saito , Masao Kuriyama , Yasuhiko Honda , Hideo Kato
发明人： Hidetoshi Saito , Masao Kuriyama , Yasuhiko Honda , Hideo Kato
IPC分类号： G11C700
CPC分类号： G11C29/78 , G11C8/06 , G11C16/26 , G11C2216/22
摘要： A nonvolatile semiconductor memory includes a memory cell array and a redundant cell array, and while a data write operation or a data erase operation is carried out in one of banks in the memory cell array, a data read operation can be carried out in the other banks. The redundant cell array has one or more spare blocks and is provided independently of the banks to relieve a defective memory cell of the memory cell array by substituting the spare block for a defective memory block in any of the blocks. The memory block is active when an access block address to be accessed in the memory cell array in the data write or erase operation or the data read operation does not coincide with the defective block address in the defective address storing circuit, whereas the spare block is active when the access block address coincides with the defective block address in the defective address storing circuit.
摘要翻译：非易失性半导体存储器包括存储单元阵列和冗余单元阵列，并且在存储单元阵列中的一个存储体中进行数据写入操作或数据擦除操作时，可以在另一个存储单元阵列中执行数据读取操作银行。冗余单元阵列具有一个或多个备用块，并且独立于存储体提供，以通过将备用块替换为任何块中的有缺陷的存储块来解除存储单元阵列的有缺陷的存储单元。当在数据写入或擦除操作或数据读取操作中要存储在存储单元阵列中的访问块地址与缺陷地址存储电路中的有缺陷块地址不一致时，存储块有效，而备用块是当访问块地址与缺陷地址存储电路中的有缺陷的块地址一致时有效。

13. 发明授权

US06906960B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US06906960B2
公开(公告)日：2005-06-14
申请号：US10383633
申请日：2003-03-10
申请人： Hidetoshi Saito , Hideo Kato , Tokumasa Hara
发明人： Hidetoshi Saito , Hideo Kato , Tokumasa Hara
IPC分类号： G11C16/02 , G11C8/12 , G11C16/08 , G11C16/04
CPC分类号： G11C8/12 , G11C16/08 , G11C2216/22
摘要： A semiconductor memory device includes: a plurality of banks with electrically rewritable memory cells arranged therein, the banks being configured to be simultaneously accessible in such a manner that a data write operation into a bank and a data read operation for another bank are simultaneously performed; a write-use data bus commonly disposed for the plurality of banks; a read-use data bus commonly disposed for the plurality of banks; a write circuit connected to the write-use data bus; a read circuit connected to the read-use data bus; a bank address decoder circuit for decoding external bank address signals for bank selecting to output internal bank address signals, the bank address decoder circuit having such an address conversion function that one of plural kinds of address conversions between the external bank address signals and the internal bank address signals is selectable; and a rewrite control circuit for sequence controlling a data write operation for a bank selected by the bank address decoder circuit.
摘要翻译：一种半导体存储器件包括：具有布置在其中的电可重写存储器单元的多个存储体，所述存储体被配置为可同时访问，以使得对于存储体的数据写操作和对于另一存储体的数据读操作同时进行; 通常为多个银行设置的写用数据总线; 通常为多个银行设置的读取用数据总线; 连接到写入用数据总线的写入电路; 连接到读取用数据总线的读取电路; 用于解码用于存储体选择的外部存储体地址信号以输出内部存储体地址信号的存储体地址解码器电路，该存储体地址译码器电路具有这样一种地址转换功能：外部存储体地址信号与内部存储体之间的多种地址转换之一地址信号可选; 以及重写控制电路，用于对由银行地址解码器电路选择的存储体进行数据写入操作的顺序控制。

14. 发明授权

US06222779B1 Semiconductor storage device with automatic write/erase function 有权
标题翻译：具有自动写入/擦除功能的半导体存储设备
公开(公告)号：US06222779B1
公开(公告)日：2001-04-24
申请号：US09460644
申请日：1999-12-15
申请人： Hidetoshi Saito , Hideo Kato , Naoto Tomita , Tokumasa Hara
发明人： Hidetoshi Saito , Hideo Kato , Naoto Tomita , Tokumasa Hara
IPC分类号： G11C700
CPC分类号： G11C16/16 , G11C16/12
摘要： A semiconductor storage device, which has an automatic write/erase function, and uses a potential obtained by boosting a power supply voltage upon write/erase, has a write division control circuit which shifts the selection timings of bit lines upon write, so as to decrease the number of bits to be written simultaneously, thereby reducing the consumption current and compensating for insufficient current supply performance of a power supply circuit in case the power supply voltage is low, and refers to the contents of erase flags upon pre-programming in erase, and erase only blocks that require erases, while, when the power supply voltage is high as the power supply voltage has a wide range or the write time is short as in an acceleration test, the number of bits to be selected at the same time is increased to prevent an increase in write/erase time.
摘要翻译：具有自动写入/擦除功能并且使用通过在写入/擦除时提高电源电压而获得的电位的半导体存储装置具有写入分配控制电路，其在写入时移位位线的选择定时，以便减少要同时写入的位数，从而降低消耗电流并补偿在电源电压低的情况下电源电路的电流供应不足，并且在擦除预编程时参考擦除标志的内容，并且仅擦除需要擦除的块，而当电源电压为高电平时，电源电压具有较大的范围或写入时间短于加速度测试时，同时选择的位数增加以防止写入/擦除时间的增加。

15. 发明申请

US20090319840A1 SEMICONDUCTOR MEMORY DEVICE AND TEST METHOD THEREOF 审中-公开
标题翻译：半导体存储器件及其测试方法
公开(公告)号：US20090319840A1
公开(公告)日：2009-12-24
申请号：US12487250
申请日：2009-06-18
申请人： Tokumasa Hara , Keiji Maruyama , Yutaka Shirai , Hidetoshi Saito
发明人： Tokumasa Hara , Keiji Maruyama , Yutaka Shirai , Hidetoshi Saito
IPC分类号： G11C29/12 , H03M13/05 , G06F11/10 , G06F11/27
CPC分类号： G11C29/42 , G06F11/1068 , G11C16/04
摘要： A semiconductor memory device includes a nonvolatile memory functioning as a main memory unit, a volatile memory functioning as a buffer unit of the nonvolatile memory, a controller, an ECC buffer, a parity syndrome circuit, an ECC control circuit, a multiplexer, and an ECC error position decoder.
摘要翻译：半导体存储器件包括用作主存储器单元的非易失性存储器，用作非易失性存储器的缓冲单元的易失性存储器，控制器，ECC缓冲器，奇偶校验电路，ECC控制电路，多路复用器和 ECC错误位置解码器。

16. 发明授权

US06856543B2 Semiconductor integrated circuit device with erasable and programmable fuse memory 失效
标题翻译：具有可擦除和可编程保险丝存储器的半导体集成电路器件
公开(公告)号：US06856543B2
公开(公告)日：2005-02-15
申请号：US10743385
申请日：2003-12-23
申请人： Shigeru Atsumi , Masao Kuriyama , Akira Umezawa , Hironori Banba , Tadayuki Taura , Hidetoshi Saito
发明人： Shigeru Atsumi , Masao Kuriyama , Akira Umezawa , Hironori Banba , Tadayuki Taura , Hidetoshi Saito
IPC分类号： G11C5/00 , G11C5/14 , G11C16/04 , H01L29/78 , H03K5/153 , H03K5/22
CPC分类号： G11C5/143 , G11C5/14 , G11C7/1045 , G11C16/26 , G11C16/30
摘要： A semiconductor integrated circuit device includes fuse cells arranged at a fuse cell array, a fuse cell data program and erase circuit, a fuse cell data control circuit, and fuse data latch circuits. The fuse cells include erasable and programmable nonvolatile memory cells. The fuse cell data program and erase circuit programs fuse data to the memory cells and erases the fuse data from the memory cells. The fuse cell data control circuit controls read out timing of the fuse data stored in the memory cells based on a signal generated upon detection of power-on. The fuse data latch circuits latch the fuse data read out from the memory cells.
摘要翻译：半导体集成电路器件包括设置在熔丝单元阵列处的熔丝单元，熔丝单元数据程序和擦除电路，熔丝单元数据控制电路和熔丝数据锁存电路。熔丝单元包括可擦除和可编程的非易失性存储单元。熔丝单元数据程序和擦除电路程序将数据熔化到存储单元，并从存储单元擦除熔丝数据。熔丝单元数据控制电路基于在检测到通电时产生的信号来控制存储在存储单元中的熔丝数据的读出定时。熔丝数据锁存电路锁存从存储器单元读出的熔丝数据。

17. 发明申请

US20050117406A1 Semiconductor integrated circuit device with main cell array and fuse cell array 失效
标题翻译：具有主单元阵列和熔丝单元阵列的半导体集成电路器件
公开(公告)号：US20050117406A1
公开(公告)日：2005-06-02
申请号：US11033398
申请日：2005-01-12
申请人： Shigeru Atsumi , Masao Kuriyama , Akira Umezawa , Hironori Banba , Tadayuki Taura , Hidetoshi Saito
发明人： Shigeru Atsumi , Masao Kuriyama , Akira Umezawa , Hironori Banba , Tadayuki Taura , Hidetoshi Saito
IPC分类号： G11C5/00 , G11C5/14 , G11C16/04 , H01L29/78 , H03K5/153 , H03K5/22
CPC分类号： G11C5/143 , G11C5/14 , G11C7/1045 , G11C16/26 , G11C16/30
摘要： A semiconductor integrated circuit device includes a main cell array, a fuse cell array, main cell word lines arranged at the main cell array, and fuse cell word lines arranged at the fuse cell array. The fuse cell word lines are formed in a same direction as a direction of the main cell word lines.
摘要翻译：半导体集成电路器件包括主单元阵列，熔丝单元阵列，布置在主单元阵列处的主单元字线以及布置在熔丝单元阵列处的熔丝单元字线。熔丝单元字线形成在与主单元字线的方向相同的方向上。

18. 发明授权

US06480426B2 Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US06480426B2
公开(公告)日：2002-11-12
申请号：US09977294
申请日：2001-10-16
申请人： Shigeru Atsumi , Masao Kuriyama , Akira Umezawa , Hironori Banba , Tadayuki Taura , Hidetoshi Saito
发明人： Shigeru Atsumi , Masao Kuriyama , Akira Umezawa , Hironori Banba , Tadayuki Taura , Hidetoshi Saito
IPC分类号： G11C1604
CPC分类号： G11C5/143 , G11C5/14 , G11C7/1045 , G11C16/26 , G11C16/30
摘要： A semiconductor integrated circuit device includes an integrated circuit provided in a semiconductor chip and setting information memory. The setting information memory stores operation/function setting information of the integrated circuit and receives a signal generated based on power-on in reading out the operation/function setting information.
摘要翻译：半导体集成电路器件包括设置在半导体芯片中的集成电路和设置信息存储器。设置信息存储器存储集成电路的操作/功能设置信息，并且在读出操作/功能设置信息时接收基于通电的信号。

19. 发明授权

US06262916B1 Non-volatile semiconductor memory device capable of pre-conditioning memory cells prior to a data erasure 失效
标题翻译：能够在数据擦除之前对存储单元进行预处理的非易失性半导体存储器件
公开(公告)号：US06262916B1
公开(公告)日：2001-07-17
申请号：US09491019
申请日：2000-01-25
申请人： Masao Kuriyama , Hidetoshi Saito , Tadayuki Taura
发明人： Masao Kuriyama , Hidetoshi Saito , Tadayuki Taura
IPC分类号： G11C1634
CPC分类号： G11C16/107 , G11C16/14 , G11C16/3454 , G11C16/3459
摘要： In a non-volatile semiconductor memory device, a binary counter is connected to a most significant bit portion of an address counter for successively generating addresses of rows of a memory cell array. The binary counter forcibly selects one of spare row lines, and permits a pre-program operation (program operation prior to data erasure) to be performed on memory cells connected to the selected one of spare row lines, when the pre-program operation has completely been performed on the memory cells of the rows of the memory cell array. In the pre-program operation, whether or not to verify data is determined on the basis of a coincidence signal outputted from a defective row address storing section.
摘要翻译：在非易失性半导体存储器件中，二进制计数器连接到地址计数器的最高有效位部分，用于连续产生存储单元阵列的行的地址。二进制计数器强制选择备用行行之一，并且当预编程操作完全被执行时，允许对连接到所选择的备用行行的存储器单元执行预编程操作（数据擦除之前的程序操作）在存储单元阵列的行的存储单元上执行。在预编程操作中，是否根据从缺陷行地址存储部分输出的一致信号确定是否验证数据。

20. 发明授权

US06078525A Non-volatile semiconductor memory device capable of pre-conditioning memory cells prior to a data erasure 失效
标题翻译：能够在数据擦除之前对存储单元进行预处理的非易失性半导体存储器件
公开(公告)号：US06078525A
公开(公告)日：2000-06-20
申请号：US233855
申请日：1999-01-19
申请人： Masao Kuriyama , Hidetoshi Saito , Tadayuki Taura
发明人： Masao Kuriyama , Hidetoshi Saito , Tadayuki Taura
IPC分类号： G11C16/02 , G11C16/06 , G11C16/14 , G11C16/34 , G11C29/04
CPC分类号： G11C16/107 , G11C16/14 , G11C16/3454 , G11C16/3459
摘要： In a non-volatile semiconductor memory device, a binary counter is connected to a most significant bit portion of an address counter for successively generating addresses of rows of a memory cell array. The binary counter forcibly selects one of spare row lines, and permits a pre-program operation (program operation prior to data erasure) to be performed on memory cells connected to the selected one of spare row lines, when the pre-program operation has completely been performed on the memory cells of the rows of the memory cell array. In the pre-program operation, whether or not to verify data is determined on the basis of a coincidence signal outputted from a defective row address storing section.
摘要翻译：在非易失性半导体存储器件中，二进制计数器连接到地址计数器的最高有效位部分，用于连续产生存储单元阵列的行的地址。二进制计数器强制选择备用行行之一，并且当预编程操作完全被执行时，允许对连接到所选择的备用行行的存储器单元执行预编程操作（数据擦除之前的程序操作）在存储单元阵列的行的存储单元上执行。在预编程操作中，是否根据从缺陷行地址存储部分输出的一致信号确定是否验证数据。

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