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1. 发明授权

US07345919B2 Semiconductor device that enables simultaneous read and write/read operation 有权
标题翻译：实现同时读/写操作的半导体器件
公开(公告)号：US07345919B2
公开(公告)日：2008-03-18
申请号：US11453830
申请日：2006-06-16
申请人： Yasuhiko Honda , Hideo Kato , Hidetoshi Saito , Masao Kuriyama , Tokumasa Hara , Takafumi Ikeda , Tatsuya Hiramatsu
发明人： Yasuhiko Honda , Hideo Kato , Hidetoshi Saito , Masao Kuriyama , Tokumasa Hara , Takafumi Ikeda , Tatsuya Hiramatsu
IPC分类号： G11C16/04
CPC分类号： G11C8/12 , G11C16/10 , G11C16/26 , G11C2216/22
摘要： A semiconductor device includes a memory cell array including a plurality of cores, each of said cores including one block or a plurality of blocks. The semiconductor device further includes a first power supply line which is provided commonly for said plurality of cores and which provides a data reading power supply potential; a second power supply line which is provided commonly for said plurality of cores and which provides a data writing or erasing power supply potential; and a power supply line switching circuit which is provided for each of said plurality of cores and which selectively connects a corresponding one of said plurality of cores to said first power supply line or said second power supply line in accordance with whether said corresponding one of said plurality of cores is in a data read mode or a data write or erase mode.
摘要翻译：半导体器件包括包括多个核的存储单元阵列，每个所述核包括一个块或多个块。所述半导体器件还包括第一电源线，所述第一电源线通常为所述多个芯提供，并提供数据读取电源电位; 第二电源线，其为所述多个核心共同提供，并且提供数据写入或擦除电源电位; 以及电源线切换电路，其被设置用于所述多个芯中的每一个，并且根据所述多个核中的所述相应一个选择性地将所述多个核中的相应一个核连接到所述第一电源线或所述第二电源线多个核心处于数据读取模式或数据写入或擦除模式。

2. 发明授权

US06377502B1 Semiconductor device that enables simultaneous read and write/erase operation 有权
标题翻译：实现同时读/写/擦除操作的半导体器件
公开(公告)号：US06377502B1
公开(公告)日：2002-04-23
申请号：US09563348
申请日：2000-05-03
申请人： Yasuhiko Honda , Hideo Kato , Hidetoshi Saito , Masao Kuriyama , Tokumasa Hara , Takafumi Ikeda , Tatsuya Hiramatsu
发明人： Yasuhiko Honda , Hideo Kato , Hidetoshi Saito , Masao Kuriyama , Tokumasa Hara , Takafumi Ikeda , Tatsuya Hiramatsu
IPC分类号： G11C800
CPC分类号： G11C8/12 , G11C16/10 , G11C16/26 , G11C2216/22
摘要： A memory cell array 1 has the arrangement of a plurality of cores, each of which comprises one block or a set of a plurality of blocks, each block defining a range of memory cells serving as a unit of data erase. A core selecting part for selecting an optional number of cores to write/erase data is provided for writing data in memory cells in cores selected on the basis of a write command and for erasing data from selected blocks in cores selected on the basis of an erase command. Thus, there is realized a free core system capable of reading data out from memory cells in unselected cores while writing/erasing data in cores selected by the core selecting part.
摘要翻译：存储单元阵列1具有多个核心的布置，每个核心包括一个块或一组多个块，每个块定义用作数据擦除单位的存储单元的范围。提供用于选择写入/擦除数据的可选数量的核心的核心选择部分，用于将数据写入基于写入命令选择的核心的存储器单元中，并且用于从基于擦除选择的核心中的所选择的块中擦除数据命令。因此，实现了一种自由核心系统，其能够在由核心选择部分选择的核心中写入/擦除数据时，从未选择的核心中的存储器单元读出数据。

3. 发明申请

US20060256616A1 Semiconductor device that enables simultaneous read and write/read operation 有权
标题翻译：实现同时读/写操作的半导体器件
公开(公告)号：US20060256616A1
公开(公告)日：2006-11-16
申请号：US11453830
申请日：2006-06-16
申请人： Yasuhiko Honda , Hideo Kato , Hidetoshi Saito , Masao Kuriyama , Tokumasa Hara , Takafumi Ikeda , Tatsuya Hiramatsu
发明人： Yasuhiko Honda , Hideo Kato , Hidetoshi Saito , Masao Kuriyama , Tokumasa Hara , Takafumi Ikeda , Tatsuya Hiramatsu
IPC分类号： G11C16/04
CPC分类号： G11C8/12 , G11C16/10 , G11C16/26 , G11C2216/22
摘要： A semiconductor device includes a memory cell array including a plurality of cores, each of said cores including one block or a plurality of blocks. The semiconductor device further includes a first power supply line which is provided commonly for said plurality of cores and which provides a data reading power supply potential; a second power supply line which is provided commonly for said plurality of cores and which provides a data writing or erasing power supple potential; and a power supply line switching circuit which is provided for each of said plurality of cores and which selectively connects a corresponding one of said plurality of cores to said first power supply line or said second power supply line in accordance with whether said corresponding one of said plurality of cores is in a data read mode or a data write or erase mode.
摘要翻译：半导体器件包括包括多个核的存储单元阵列，每个所述核包括一个块或多个块。所述半导体器件还包括第一电源线，所述第一电源线通常为所述多个芯提供，并提供数据读取电源电位; 第二电源线，其为所述多个核心共同提供，并且提供数据写入或擦除功率补偿电位; 以及电源线切换电路，其被设置用于所述多个芯中的每一个，并且根据所述多个核中的所述相应一个选择性地将所述多个核中的相应一个核连接到所述第一电源线或所述第二电源线多个核心处于数据读取模式或数据写入或擦除模式。

4. 发明授权

US06920057B2 Semiconductor device that enables simultaneous read and write/read operation 有权
标题翻译：实现同时读/写操作的半导体器件
公开(公告)号：US06920057B2
公开(公告)日：2005-07-19
申请号：US10860275
申请日：2004-06-04
申请人： Yasuhiko Honda , Hideo Kato , Hidetoshi Saito , Masao Kuriyama , Tokumasa Hara , Takafumi Ikeda , Tatsuya Hiramatsu
发明人： Yasuhiko Honda , Hideo Kato , Hidetoshi Saito , Masao Kuriyama , Tokumasa Hara , Takafumi Ikeda , Tatsuya Hiramatsu
IPC分类号： G11C16/00 , G11C5/00 , G11C8/12 , G11C16/10 , G11C16/26 , G11C5/02
CPC分类号： G11C8/12 , G11C16/10 , G11C16/26 , G11C2216/22
摘要： A semiconductor device has a memory cell array having the arrangement of a plurality of cores, each of which comprises one block or a set of a plurality of blocks, each block defining a range of memory cells serving as a unit of data erase. The semiconductor device has a bank setting memory circuit configured to select an optional number of cores of the cores as a first bank and to set the remaining cores as a second bank, so as to allow a data read operation to be carried out in one of the first and second banks while a data write or erase operation is carried out in the other of the first and second banks.
摘要翻译：半导体器件具有存储单元阵列，其具有多个核心的布置，每个核心包括一个块或一组多个块，每个块定义作为数据擦除单位的存储单元的范围。半导体器件具有存储体设置存储器电路，其被配置为选择核心的可选数量的核心作为第一存储体，并且将剩余的核心设置为第二存储体，以便允许数据读取操作以在第一和第二组中的另一个中进行数据写入或擦除操作的第一和第二存储体。

5. 发明授权

US06903983B2 Semiconductor integrated circuit device and read start trigger signal generating method therefor 有权
标题翻译：半导体集成电路器件及其读取开始触发信号产生方法
公开(公告)号：US06903983B2
公开(公告)日：2005-06-07
申请号：US10325753
申请日：2002-12-23
申请人： Tokumasa Hara , Hidetoshi Saito , Hitoshi Shiga , Yasuhiko Honda , Tadayuki Taura , Hideo Kato
发明人： Tokumasa Hara , Hidetoshi Saito , Hitoshi Shiga , Yasuhiko Honda , Tadayuki Taura , Hideo Kato
IPC分类号： G11C16/02 , G11C8/18 , G11C16/32 , G11C16/04
CPC分类号： G11C8/18 , G11C16/32 , G11C2216/22
摘要： A semiconductor integrated circuit device includes a first memory cell array corresponding to bank 0, a second memory cell array corresponding to bank 1, first address transition signal generating circuits which detect transitions of input addresses and generate first address transition signals, a second address transition signal generating circuit which pre-detects an end of automatic execution of bank 0 or bank 1 and generates a second address transition signal, and a read start trigger output circuit. The read start trigger output circuit outputs a read start trigger signal on the basis of the first address transition signals and the second address transition signal.
摘要翻译：半导体集成电路装置包括对应于存储体0的第一存储单元阵列，对应于存储体1的第二存储单元阵列，检测输入地址的转换并产生第一地址转换信号的第一地址转换信号产生电路，第二地址转换信号生成电路，其预先检测存储体0或存储体1的自动执行结束并产生第二地址转换信号，以及读取开始触发输出电路。读取开始触发输出电路基于第一地址转换信号和第二地址转换信号输出读取开始触发信号。

6. 发明授权

US06717852B2 Nonvolatile semiconductor memory device capable of concurrently and reliably writing/erasing and reading memory cores 有权
标题翻译：能够同时且可靠地写入/擦除和读取存储器核的非易失性半导体存储器件
公开(公告)号：US06717852B2
公开(公告)日：2004-04-06
申请号：US10267693
申请日：2002-10-10
申请人： Yasuhiko Honda , Hideo Kato , Masao Kuriyama , Hidetoshi Saito , Tokumasa Hara
发明人： Yasuhiko Honda , Hideo Kato , Masao Kuriyama , Hidetoshi Saito , Tokumasa Hara
IPC分类号： G11C1632
CPC分类号： G11C16/08 , G11C7/1042 , G11C16/10 , G11C16/26 , G11C2216/22
摘要： A semiconductor memory device, which allows concurrent execution of a write/erase operation and a read operation, is provided for each core with a core busy output circuit which has a function of, at the start, end, suspending or resuming of a write/erase operation, setting the sequence in which a command to write into/erase or read from a core, a core select signal indicating whether or not the core has been selected, and a busy signal indicating that the core is in the write/erase mode are set or reset so that multiple selection of a core in a write/erase operation and a core in a read operation does not occur.
摘要翻译：为每个核心提供一个允许并行执行写入/擦除操作和读取操作的半导体存储器件，其具有核心忙输出电路，其具有在开始和结束时挂起或恢复写/ 擦除操作，设置写入/擦除或从内核读取的命令的顺序，指示核心是否被选择的核心选择信号以及指示核心处于写/擦除模式的忙信号被设置或复位，使得在写入/擦除操作中的核心和读取操作中的核心不会发生多次选择。

7. 发明授权

US06906960B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US06906960B2
公开(公告)日：2005-06-14
申请号：US10383633
申请日：2003-03-10
申请人： Hidetoshi Saito , Hideo Kato , Tokumasa Hara
发明人： Hidetoshi Saito , Hideo Kato , Tokumasa Hara
IPC分类号： G11C16/02 , G11C8/12 , G11C16/08 , G11C16/04
CPC分类号： G11C8/12 , G11C16/08 , G11C2216/22
摘要： A semiconductor memory device includes: a plurality of banks with electrically rewritable memory cells arranged therein, the banks being configured to be simultaneously accessible in such a manner that a data write operation into a bank and a data read operation for another bank are simultaneously performed; a write-use data bus commonly disposed for the plurality of banks; a read-use data bus commonly disposed for the plurality of banks; a write circuit connected to the write-use data bus; a read circuit connected to the read-use data bus; a bank address decoder circuit for decoding external bank address signals for bank selecting to output internal bank address signals, the bank address decoder circuit having such an address conversion function that one of plural kinds of address conversions between the external bank address signals and the internal bank address signals is selectable; and a rewrite control circuit for sequence controlling a data write operation for a bank selected by the bank address decoder circuit.
摘要翻译：一种半导体存储器件包括：具有布置在其中的电可重写存储器单元的多个存储体，所述存储体被配置为可同时访问，以使得对于存储体的数据写操作和对于另一存储体的数据读操作同时进行; 通常为多个银行设置的写用数据总线; 通常为多个银行设置的读取用数据总线; 连接到写入用数据总线的写入电路; 连接到读取用数据总线的读取电路; 用于解码用于存储体选择的外部存储体地址信号以输出内部存储体地址信号的存储体地址解码器电路，该存储体地址译码器电路具有这样一种地址转换功能：外部存储体地址信号与内部存储体之间的多种地址转换之一地址信号可选; 以及重写控制电路，用于对由银行地址解码器电路选择的存储体进行数据写入操作的顺序控制。

8. 发明授权

US06829194B2 Semiconductor device that enables simultaneous read and write/read operation 有权
标题翻译：实现同时读/写操作的半导体器件
公开(公告)号：US06829194B2
公开(公告)日：2004-12-07
申请号：US10307283
申请日：2002-12-02
申请人： Yasuhiko Honda , Hideo Kato , Hidetoshi Saito , Masao Kuriyama , Tokumasa Hara , Takafumi Ikeda , Tatsuya Hiramatsu
发明人： Yasuhiko Honda , Hideo Kato , Hidetoshi Saito , Masao Kuriyama , Tokumasa Hara , Takafumi Ikeda , Tatsuya Hiramatsu
IPC分类号： G11C800
CPC分类号： G11C8/12 , G11C16/10 , G11C16/26 , G11C2216/22
摘要： A memory cell array 1 has the arrangement of a plurality of cores, each of which comprises one block or a set of a plurality of blocks, each block defining a range of memory cells serving as a unit of data erase. A core selecting part for selecting an optional number of cores to write/erase data is provided for writing data in memory cells in cores selected on the basis of a write command and for erasing data from selected blocks in cores selected on the basis of an erase command. Thus, there is realized a free core system capable of reading data out from memory cells in unselected cores while writing/erasing data in cores selected by the core selecting part.
摘要翻译：半导体器件具有存储单元阵列，其具有多个核心的布置，每个核心包括一个块或一组多个块，每个块定义用作数据擦除单位的存储单元范围。半导体设备具有存储体设置存储器电路，其被配置为选择核心的可选数量的核心作为第一存储体，并且将剩余的核心设置为第二存储体，以便允许数据读取操作在第一存储器和第二存储体，同时在第一和第二存储体的另一个中进行数据写入或擦除操作。

9. 发明授权

US06512693B2 Semiconductor device that enables simultaneous read and write/erase operation 有权
标题翻译：实现同时读/写/擦除操作的半导体器件
公开(公告)号：US06512693B2
公开(公告)日：2003-01-28
申请号：US09987981
申请日：2001-11-16
申请人： Yasuhiko Honda , Hideo Kato , Hidetoshi Saito , Masao Kuriyama , Tokumasa Hara , Takafumi Ikeda , Tatsuya Hiramatsu
发明人： Yasuhiko Honda , Hideo Kato , Hidetoshi Saito , Masao Kuriyama , Tokumasa Hara , Takafumi Ikeda , Tatsuya Hiramatsu
IPC分类号： G11C1604
CPC分类号： G11C8/12 , G11C16/10 , G11C16/26 , G11C2216/22
摘要： A semiconductor device has a memory cell array having the arrangement of a plurality of cores, each of which comprises one block or a set of a plurality of blocks, each block defining a range of memory cells serving as a unit of data erase. The semiconductor device has a bank setting memory circuit configured to select an optional number of cores of the cores as a first bank and to set the remaining cores as a second bank, so as to allow a data read operation to be carried out in one of the first and second banks while a data write or erase operation is carried out in the other of the first and second banks.
摘要翻译：半导体器件具有存储单元阵列，其具有多个核心的布置，每个核心包括一个块或一组多个块，每个块定义作为数据擦除单位的存储单元的范围。半导体器件具有存储体设置存储器电路，其被配置为选择核心的可选数量的核心作为第一存储体，并且将剩余的核心设置为第二存储体，以便允许数据读取操作以在第一和第二组中的另一个中进行数据写入或擦除操作的第一和第二存储体。

10. 发明授权

US07126855B2 Semiconductor device that enables simultaneous read and write/read operation 失效
标题翻译：实现同时读/写操作的半导体器件
公开(公告)号：US07126855B2
公开(公告)日：2006-10-24
申请号：US11125073
申请日：2005-05-10
申请人： Yasuhiko Honda , Hideo Kato , Hidetoshi Saito , Masao Kuriyama , Tokumasa Hara , Takafumi Ikeda , Tatsuya Hiramatsu
发明人： Yasuhiko Honda , Hideo Kato , Hidetoshi Saito , Masao Kuriyama , Tokumasa Hara , Takafumi Ikeda , Tatsuya Hiramatsu
IPC分类号： G11C16/06 , G11C16/04
CPC分类号： G11C8/12 , G11C16/10 , G11C16/26 , G11C2216/22
摘要： A semiconductor device has a memory cell array having the arrangement of a plurality of cores, each of which comprises one block or a set of a plurality of blocks, each block defining a range of memory cells serving as a unit of data erase. The semiconductor device has a bank setting memory circuit configured to select an optional number of cores of the cores as a first bank and to set the remaining cores as a second bank, so as to allow a data read operation to be carried out in one of the first and second banks while a data write or erase operation is carried out in the other of the first and second banks.
摘要翻译：半导体器件具有存储单元阵列，其具有多个核心的布置，每个核心包括一个块或一组多个块，每个块定义作为数据擦除单位的存储单元的范围。半导体器件具有存储体设置存储器电路，其被配置为选择核心的可选数量的核心作为第一存储体，并且将剩余的核心设置为第二存储体，以便允许数据读取操作以在第一和第二组中的另一个中进行数据写入或擦除操作的第一和第二存储体。

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