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11. 发明授权

US07266708B2 System for idling a processor pipeline wherein the fetch stage comprises a multiplexer for outputting NOP that forwards an idle signal through the pipeline 有权
标题翻译：用于怠速处理器流水线的系统，其中所述提取级包括用于输出通过所述流水线转发空闲信号的NOP的多路复用器
公开(公告)号：US07266708B2
公开(公告)日：2007-09-04
申请号：US10963159
申请日：2004-10-12
申请人： William V. Miller
发明人： William V. Miller
IPC分类号： G06F1/00
CPC分类号： G06F1/3203 , G06F1/3237 , G06F9/30079 , G06F9/30083 , G06F9/3867 , Y02D10/128 , Y02D50/20
摘要： A processor disclosed herein comprises a clock configured to drive clock signals and a processor pipeline having a plurality of stages. The processor includes processor idling circuitry, which is configured within the stages and is responsive to an idle_request signal. A first stage comprises a device for stopping incoming instruction values from being further processed when the idle_request signal is received. Also, at least two of the remaining stages comprise idle_flag logic configured to receive the idle_request signal, the idle_flag logic further configured to transmit an idle_flag through the processor pipeline.
摘要翻译：本文公开的处理器包括被配置为驱动时钟信号的时钟和具有多个级的处理器管线。处理器包括处理器空闲电路，其被配置在阶段内并且响应于空闲请求信号。第一级包括用于在接收到空闲请求信号时停止输入指令值进一步处理的装置。而且，剩余级中的至少两个级别包括被配置为接收空闲请求信号的空闲标志逻辑，该空闲标志逻辑还被配置为通过处理器流水线传输空闲标签。

12. 发明授权

US07143243B2 Tag array access reduction in a cache memory 有权
标题翻译：缓存中的标签数组访问减少
公开(公告)号：US07143243B2
公开(公告)日：2006-11-28
申请号：US10447930
申请日：2003-05-29
申请人： William V. Miller
发明人： William V. Miller
IPC分类号： G06F12/06
CPC分类号： G06F12/0882 , Y02D10/13
摘要： A cache memory is disclosed with reduced tag array searches for sequential memory accesses. The cache memory has components such as at least one tag array, at least one data array associated with the tag array, a tag read control logic module for controlling a tag array search, a comparator associated with the tag array, and a storage module for storing a match result of the comparator while processing a first memory access request that accesses a first data address in a first cacheline of the data array. The stored match result is used for a second memory access request that intends to access a second data address sequential to the first data address, thereby avoiding searching the tag array for the second memory access request.
摘要翻译：公开了一种缓存存储器，其具有减少的标签阵列搜索顺序存储器访问。高速缓冲存储器具有诸如至少一个标签阵列，与标签阵列相关联的至少一个数据阵列，用于控制标签阵列搜索的标签读取控制逻辑模块，与该标签阵列相关联的比较器以及与该标签阵列相关联的存储模块存储比较器的匹配结果，同时处理访问数据阵列的第一高速缓存行中的第一数据地址的第一存储器访问请求。所存储的匹配结果用于第二存储器访问请求，该第二存储器访问请求旨在连续地访问与第一数据地址相对应的第二数据地址，从而避免在标签阵列中搜索第二存储器访问请求。

13. 发明授权

US06842052B2 Multiple asynchronous switching system 有权
标题翻译：多异步交换系统
公开(公告)号：US06842052B2
公开(公告)日：2005-01-11
申请号：US10170077
申请日：2002-06-11
申请人： William V. Miller
发明人： William V. Miller
IPC分类号： G06F1/08 , H03K5/1252 , H03L17/00
CPC分类号： G06F1/08 , H03K5/1252
摘要： A system for allowing an asynchronous clock signal to be selected from a plurality of asynchronous clock signals without causing glitches. In the system, a requestor is connected to control signals. The control signals indicate to the requestor which asynchronous clock signal, of the two or more clock signals, to request. The requestor informs a selector of the request. The selector determines which asynchronous clock signal was selected. The selected asynchronous clock is then detected by the detector. The detector feeds the selected asynchronous clock signal to a signal output. The signal output releases the selected asynchronous clock signal.
摘要翻译：一种用于允许从多个异步时钟信号中选择异步时钟信号而不引起毛刺的系统。在系统中，请求者连接到控制信号。控制信号向请求者指示两个或更多个时钟信号中哪个异步时钟信号请求。请求者通知选择器请求。选择器确定选择了哪个异步时钟信号。然后由检测器检测所选择的异步时钟。检测器将所选择的异步时钟信号馈送到信号输出。信号输出释放选定的异步时钟信号。

14. 发明授权

US08949573B2 Translation lookaside buffer structure including an output comparator 有权
标题翻译：翻译后备缓冲结构包括一个输出比较器
公开(公告)号：US08949573B2
公开(公告)日：2015-02-03
申请号：US13097286
申请日：2011-04-29
申请人： Edward M. McCombs , Chetan C. Kamdar , William V. Miller
发明人： Edward M. McCombs , Chetan C. Kamdar , William V. Miller
IPC分类号： G06F12/00 , H03K19/096 , G06F12/10 , G11C7/06
CPC分类号： H03K19/096 , G06F12/1027 , G11C7/062 , Y02D10/13
摘要： A processor includes a translation lookaside buffer (TLB) including a data array and a compare unit. The data array includes a number of entries each configured to store a respective translated physical address. In response to a read access to a given entry of the TLB, the data array is configured to output within a particular clock cycle, the respective translated physical address stored in the given entry. In addition the compare unit may be configured to compare the respective translated physical address output by the data array with a number of additional addresses. The compare unit may also be configured to provide a hit indication for each of the additional addresses within the particular clock cycle.
摘要翻译：处理器包括包括数据阵列和比较单元的翻译后备缓冲器（TLB）。数据阵列包括多个条目，每个条目被配置为存储相应的翻译的物理地址。响应于对TLB的给定条目的读取访问，数据阵列被配置为在特定时钟周期内输出存储在给定条目中的相应翻译的物理地址。此外，比较单元可以被配置为将由数据阵列输出的相应翻译的物理地址与多个附加地址进行比较。比较单元还可以被配置为为特定时钟周期内的每个附加地址提供命中指示。

15. 发明授权

US08432756B1 Collision prevention in a dual port memory 有权
标题翻译：双端口内存中的防碰撞
公开(公告)号：US08432756B1
公开(公告)日：2013-04-30
申请号：US13275920
申请日：2011-10-18
申请人： Steven C. Sullivan , William V. Miller
发明人： Steven C. Sullivan , William V. Miller
IPC分类号： G11C7/00
CPC分类号： G11C7/1075
摘要： A dual port memory includes a mechanism for preventing collisions. The memory includes dual port bit cells arranged in rows and columns and each bit cell stores a data bit. The memory also includes a wordline unit that may provide a respective write wordline signal and a respective read wordline signal to each row of bit cells. The wordline unit may also selectively inhibit the read wordline signal for a given row based upon address information that is indicative of whether a write operation will be performed to the given row.
摘要翻译：双端口存储器包括用于防止冲突的机构。存储器包括以行和列布置的双端口位单元，并且每个位单元存储数据位。存储器还包括字线单元，其可以向每行位单元提供相应的写入字线信号和相应的读取字线信号。字线单元还可以基于指示是否对给定行执行写入操作的地址信息来选择性地禁止给定行的读取字线信号。

16. 发明授权

US07676632B2 Partial cache way locking 有权
标题翻译：部分缓存方式锁定
公开(公告)号：US07676632B2
公开(公告)日：2010-03-09
申请号：US11470304
申请日：2006-09-06
申请人： William V. Miller
发明人： William V. Miller
IPC分类号： G06F13/00
CPC分类号： G06F12/126 , G06F12/0864 , G06F12/128
摘要： Systems and methods are disclosed for locking code in cache. A processor comprises a cache and a cache controller. The cache is configured to store a temporary copy of code residing in main memory. Also, the cache is divided into a number of cache ways, where each cache way is further divided into a number of cache way portions. The cache controller is configured to utilize a first signal and a second signal. The first signal designates one of the cache ways as a partial cache way and the second signal defines which ones of the cache way portions of the partial cache way are to be locked.
摘要翻译：公开了用于将代码锁定在高速缓存中的系统和方法。处理器包括高速缓存和高速缓存控制器。高速缓存配置为存储驻留在主存储器中的代码的临时副本。此外，高速缓存被分成多个高速缓存方式，其中每个高速缓存方式被进一步划分成多个缓存方式部分。高速缓存控制器被配置为利用第一信号和第二信号。第一信号将高速缓存路径中的一个指定为部分高速缓存方式，第二信号定义部分高速缓存方式中的哪个高速缓存方式部分将被锁定。

17. 发明授权

US07496779B2 Dynamically synchronizing a processor clock with the leading edge of a bus clock 有权
标题翻译：将处理器时钟与总线时钟的前沿动态同步
公开(公告)号：US07496779B2
公开(公告)日：2009-02-24
申请号：US11451806
申请日：2006-06-13
申请人： William V. Miller
发明人： William V. Miller
IPC分类号： G06F1/04
CPC分类号： G06F1/10 , G06F1/12
摘要： Systems and methods for detecting a leading edge of a bus clock signal are disclosed herein. One edge detecting system includes a device for providing a bus clock and a processor clock, in which the processor clock is an integer multiple of the bus clock. The device for providing the clocks, however, does not provide a control signal that indicates the location of an edge of the bus clock. The system further includes a clock tree configured to distribute the bus clock and processor clock to multiple destinations, whereby the destinations receive the bus clock and processor clock delayed by an insertion time of the clock tree. The system also includes a processor having a device for detecting the leading edge of the bus clock delayed by the insertion time. Furthermore, a method is disclosed herein. The method includes generating a bus clock and a processor clock without a corresponding control signal, receiving an insertion-delayed version of the bus clock and processor clock, and processing the insertion-delayed bus clock and processor clock to generate a flag signal that indicates the location of a leading edge of the insertion-delayed bus clock.
摘要翻译：本文公开了用于检测总线时钟信号的前沿的系统和方法。一个边缘检测系统包括用于提供总线时钟和处理器时钟的装置，其中处理器时钟是总线时钟的整数倍。然而，用于提供时钟的装置不提供指示总线时钟的边缘的位置的控制信号。该系统还包括配置成将总线时钟和处理器时钟分配到多个目的地的时钟树，由此目的地接收时钟树的插入时间延迟的总线时钟和处理器时钟。该系统还包括具有用于检测延迟插入时间的总线时钟前沿的装置的处理器。此外，本文公开了一种方法。该方法包括产生总线时钟和没有相应控制信号的处理器时钟，接收总线时钟和处理器时钟的插入延迟版本，以及处理插入延迟的总线时钟和处理器时钟，以产生一个标志信号，插入延迟总线时钟的前沿位置。

18. 发明申请

US20080104327A1 Systems and Method for Improved Data Retrieval from Memory on Behalf of Bus Masters 有权
标题翻译：用于改进从总线主机内存中检索数据的系统和方法
公开(公告)号：US20080104327A1
公开(公告)日：2008-05-01
申请号：US11553586
申请日：2006-10-27
申请人： Richard Duncan , William V. Miller , Daniel Davis
发明人： Richard Duncan , William V. Miller , Daniel Davis
IPC分类号： G06F12/00
CPC分类号： G06F12/0862 , G06F2212/601
摘要： Systems and methods are disclosed herein for retrieving data from memory in a computer system. In one example, a memory controller is coupled to a system bus in a computer system that includes bus masters similarly coupled to the system bus. The memory controller is configured to receive requests to read or write data from memory from bus masters of the computer system. If the memory controller receives an initial request from certain bus masters, the memory controller is further configured to anticipate a future request from certain bus masters and prefetch data on behalf of certain bus masters for rapid delivery following a subsequent request to read data from memory submitted by the certain bus masters.
摘要翻译：本文公开了用于从计算机系统中的存储器检索数据的系统和方法。在一个示例中，存储器控制器耦合到计算机系统中的系统总线，其包括类似地耦合到系统总线的总线主控器。存储器控制器被配置为从计算机系统的总线主机接收从存储器读取或写入数据的请求。如果存储器控制器接收到来自某些总线主机的初始请求，则存储器控制器被进一步配置成预期来自某些总线主机的将来的请求，并且代表某些总线主机预取数据，以便在随后的从提交的存储器读取数据的请求之后快速传送由某些公交车主人。

19. 发明授权

US07305510B2 Multiple master buses and slave buses transmitting simultaneously 有权
标题翻译：多个主总线和从属总线同时传输
公开(公告)号：US07305510B2
公开(公告)日：2007-12-04
申请号：US10877376
申请日：2004-06-25
申请人： William V. Miller
发明人： William V. Miller
IPC分类号： G06F13/40 , G00F13/00
CPC分类号： G06F13/4054
摘要： A bus system, such as an internal bus system located within a digital device, is disclosed herein. The bus system comprises a plurality of master buses, each master bus connected to at least one master. The bus system also comprises a multi-bus interface connected to the plurality of master buses and a slave bus connected to the multi-bus interface. The multi-bus interface enables one master bus at a time to access the slave bus. Also disclosed herein are bus structures and methods for interfacing between master buses and slave buses.
摘要翻译：本文公开了一种总线系统，例如位于数字设备内部的内部总线系统。总线系统包括多个主总线，每个主总线连接到至少一个主站。总线系统还包括连接到多个主总线的多总线接口和连接到多总线接口的从总线。多总线接口使一个主总线能够一次访问从总线。这里还公开了用于在主总线和从属总线之间进行接口的总线结构和方法。

20. 发明授权

US5553244A Reflexively sizing memory bus interface 失效
标题翻译：反映尺寸的内存总线接口
公开(公告)号：US5553244A
公开(公告)日：1996-09-03
申请号：US387964
申请日：1995-02-10
申请人： Thomas M. Norcross , William V. Miller
发明人： Thomas M. Norcross , William V. Miller
IPC分类号： G06F12/06 , G06F12/04 , G06F13/16 , G06F13/40 , G06F13/00
CPC分类号： G06F13/4018
摘要： A reflexively scaling memory bus interface system and method allows the implementation of an ISA bus peripheral card that will effectively operate within the decoded memory space of another sixteen bit card while using only the external memory components required for an eight bit interface. The same peripheral card will also be compatible in a system with other eight bit cards located in a corresponding memory space. The reflexively sizing memory bus interface responds automatically to memory accesses that vary in data bus width (i.e., eight or sixteen bits) by directly or indirectly monitoring feedback signals from other devices on the bus. This technique solves the problem of integrating eight and sixteen bit cards on the ISA bus.
摘要翻译：反向缩放的存储器总线接口系统和方法允许实现ISA总线外围卡，其将仅在使用八位接口所需的外部存储器组件的同时在另一十六位卡的解码存储器空间内有效地操作。相同的外围卡也将与位于相应存储器空间中的其他八位卡的系统兼容。自动调整大小的存储器总线接口通过直接或间接监视总线上其他设备的反馈信号，自动响应数据总线宽度（即八位或十六位）变化的存储器访问。这种技术解决了在ISA总线上集成8位和16位位卡的问题。

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