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11. 发明授权

US07316572B2 Compliant electrical contacts 有权
标题翻译：符合电气触点
公开(公告)号：US07316572B2
公开(公告)日：2008-01-08
申请号：US10906111
申请日：2005-02-03
申请人： William E. Bernier , David E. Eichstadt , Mukta G. Farooq , John U. Knickerbocker
发明人： William E. Bernier , David E. Eichstadt , Mukta G. Farooq , John U. Knickerbocker
IPC分类号： H01R12/00
CPC分类号： H01L24/13 , G01R1/06716 , G01R1/07314 , G01R3/00 , H01L21/6835 , H01L24/11 , H01L24/81 , H01L2221/68377 , H01L2224/11003 , H01L2224/114 , H01L2224/11505 , H01L2224/116 , H01L2224/1308 , H01L2224/13082 , H01L2224/131 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13169 , H01L2224/1318 , H01L2224/13184 , H01L2224/81205 , H01L2224/8121 , H01L2224/81815 , H01L2224/8384 , H01L2924/00011 , H01L2924/00013 , H01L2924/00014 , H01L2924/01004 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01046 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/1461 , H01L2924/30105 , H01L2924/30107 , H05K3/06 , H05K3/3436 , H05K2201/10242 , Y02P70/613 , Y10T29/49124 , Y10T29/49204 , H01L2224/13099 , H01L2924/00 , H01L2224/0401
摘要： A method of forming compliant electrical contacts includes patterning a conductive layer into an array of compliant members. The array of compliant members is then positioned to be in contact with electrical connection pads on an integrated circuit wafer and the compliant members are joined to the pads. Then, the supporting layer that supported the compliant members is removed to leave the compliant members connected to the pads.
摘要翻译：形成顺应性电触头的方法包括将导电层图案化为顺应构件阵列。然后将顺应构件阵列定位成与集成电路晶片上的电连接焊盘接触，并且柔性构件连接到焊盘。然后，移除支撑柔顺构件的支撑层，以使与柔性构件连接的衬垫离开。

12. 发明申请

US20130098176A1 Flat Laminate, Symmetrical Test Structures and Method of Use To Gauge White Bump Sensitivity 有权
标题翻译：扁平层压板，对称测试结构和使用方法来测量白色凹凸感光度
公开(公告)号：US20130098176A1
公开(公告)日：2013-04-25
申请号：US13277246
申请日：2011-10-20
申请人： William E. Bernier , Timothy H. Daubenspeck , Virendra R. Jadhav , Valerie A. Oberson , David L. Questad
发明人： William E. Bernier , Timothy H. Daubenspeck , Virendra R. Jadhav , Valerie A. Oberson , David L. Questad
IPC分类号： G01N33/00
CPC分类号： H01L22/30 , B05D1/36 , G01N3/60 , G01N19/04 , G01N25/16 , G01N2203/0296 , G01N2203/0298 , H01L24/13 , H01L2224/131 , H01L2924/10253 , H01L2924/351 , H01L2924/014 , H01L2924/00
摘要： A symmetrical, flat laminate structure used to minimize variables in a test structure to experimentally gauge white bump sensitivity to CTE mismatch is disclosed. The test structure includes a flat laminate structure. The method of using the test structure includes isolating a cause of a multivariable chip join problem that is adversely impacted by warpage and quantifying a contribution of the warpage, itself, in a formation of the multivariable chip join problem.
摘要翻译：公开了一种对称的平板层压结构，用于使测试结构中的变量最小化，以实验测量白色凸起对CTE不匹配的敏感性。测试结构包括平板层压结构。使用测试结构的方法包括隔离多变量芯片连接问题的原因，其由翘曲不利地影响并量化翘曲的贡献本身在多变量芯片连接问题的形成中。

13. 发明授权

US06585150B1 Solder protective coating and fluxless joining of flip chip devices on laminates with plated solder 失效
标题翻译：倒装芯片器件的焊接保护涂层和无焊接接合在具有电镀焊料的层压板上
公开(公告)号：US06585150B1
公开(公告)日：2003-07-01
申请号：US09687524
申请日：2000-10-12
申请人： William E. Bernier , Donald W. Henderson , James Spalik , Isabelle Paquin
发明人： William E. Bernier , Donald W. Henderson , James Spalik , Isabelle Paquin
IPC分类号： B23K3102
CPC分类号： H01L24/81 , B23K35/226 , C23C8/00 , C23C26/00 , H01L2224/81801 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/0105 , H01L2924/014 , H05K3/282 , H05K3/3457
摘要： A method for protecting tin oxide coated solder surfaces against further oxidation and a method for fluxless solder joining of such surfaces is provided.
摘要翻译：提供了一种用于保护氧化锡涂覆的焊料表面以防止进一步氧化的方法以及这种表面的无焊剂焊料接合的方法。

14. 发明授权

US06559666B2 Method and device for semiconductor testing using electrically conductive adhesives 失效
标题翻译：使用导电胶粘剂进行半导体测试的方法和装置
公开(公告)号：US06559666B2
公开(公告)日：2003-05-06
申请号：US09875246
申请日：2001-06-06
申请人： William E. Bernier , Michael A. Gaynes , Wayne J. Howell , Mark V. Pierson , Ajit K. Trivedi , Charles G. Woychik
发明人： William E. Bernier , Michael A. Gaynes , Wayne J. Howell , Mark V. Pierson , Ajit K. Trivedi , Charles G. Woychik
IPC分类号： G01R3102
CPC分类号： G01R31/2886 , H01L2224/45144 , H01L2224/81385 , H01L2224/83101 , H05K3/321 , H01L2924/00
摘要： A method and device for testing and burning-in semiconductor circuits. The method and device permit the entire wafer to be tested by temporarily attaching the wafer to a test substrate using electrically conductive adhesive (ECA). The ECA conforms to deviations from co-planarity of the contact points of both the wafer and test substrate while providing a quality electrical connection at each point. ECA material can be deposited on either the wafer contacts or the substrate pads. In addition, the ECA may be deposited on C4 bumps or tin-capped lead bases. Variations in the method and device include filling vias of a non-conductive interposer with ECA. The electrical connection may be enhanced by forming conductive dendrites on test pads while the ECA is deposited on the wafer contacts. To further enhance the electrical connection, the ECA material can be plasma etched to remove some of its polymer matrix and to expose the electrically conductive particles on one side and then plating with palladium. After the palladium-plated ECA is brought into contact with aluminum pads, palladium-coated aluminum pads, or even C4 solder bumps, conductive dendrites are formed on the palladium-treated ECA bumps.
摘要翻译：一种用于测试和燃烧半导体电路的方法和装置。该方法和装置允许通过使用导电粘合剂（ECA）将晶片临时附接到测试基板来测试整个晶片。 ECA符合晶片和测试基板的接触点的共平面偏差，同时在每个点提供质量电连接。 ECA材料可以沉积在晶片触点或衬底焊盘上。此外，ECA可以沉积在C4凸点或锡盖铅基上。该方法和装置的变化包括用ECA填充非导电插入件的通孔。可以通过在测试焊盘上形成导电枝晶而增加电连接，同时将ECA沉积在晶片触点上。为了进一步增强电连接，可以对ECA材料进行等离子体蚀刻以除去其一些聚合物基质并使一面上的导电颗粒暴露，然后用钯镀覆。在镀钯的ECA与铝焊盘，钯涂覆的铝焊盘或甚至C4焊料凸块接触之后，在钯处理的ECA凸块上形成导电枝晶。

15. 发明授权

US06268739B1 Method and device for semiconductor testing using electrically conductive adhesives 失效
公开(公告)号：US06268739B1
公开(公告)日：2001-07-31
申请号：US09478678
申请日：2000-01-06
申请人： William E. Bernier , Michael A. Gaynes , Wayne J. Howell , Mark V. Pierson , Ajit K. Trivedi , Charles G. Woychik
发明人： William E. Bernier , Michael A. Gaynes , Wayne J. Howell , Mark V. Pierson , Ajit K. Trivedi , Charles G. Woychik
IPC分类号： G01R3102
CPC分类号： G01R31/2886 , H01L2224/45144 , H01L2224/81385 , H01L2224/83101 , H05K3/321 , H01L2924/00
摘要： A method and device for testing and burning-in semiconductor circuits. The method and device permit the entire wafer to be tested by temporarily attaching the wafer to a test substrate using electrically conductive adhesive (ECA). The ECA conforms to deviations from co-planarity of the contact points of both the wafer and test substrate while providing a quality electrical connection at each point. ECA material can be deposited on either the wafer contacts or the substrate pads. In addition, the ECA may be deposited on C4 bumps or tin-capped lead bases. Variations in the method and device include filling vias of a non-conductive interposer with ECA. The electrical connection may be enhanced by forming conductive dendrites on test pads while the ECA is deposited on the wafer contacts. To further enhance the electrical connection, the ECA material can be plasma etched to remove some of its polymer matrix and to expose the electrically conductive particles on one side and then plating with palladium. After the palladium-plated ECA is brought into contact with aluminum pads, palladium-coated aluminum pads, or even C4 solder bumps, conductive dendrites are formed on the palladium-treated ECA bumps.

16. 发明授权

US4374001A Electrolytic printing 失效
标题翻译：电解印刷
公开(公告)号：US4374001A
公开(公告)日：1983-02-15
申请号：US231832
申请日：1981-02-05
申请人： William E. Bernier
发明人： William E. Bernier
IPC分类号： C09K9/02 , B41M5/20 , G02F1/15 , G02F1/17 , G01D15/06 , G01D15/34
CPC分类号： B41M5/20
摘要： An electrochromic printable media which includes a substrate coated with certain leuco dyes and with a bromide compound; and use thereof for electrochromic printing.
摘要翻译：一种电致变色可印刷介质，其包括涂覆有某些无色染料和溴化合物的基材; 并用于电致变色印刷。

17. 发明授权

US08167962B2 Pulpstone for long fiber pulp production 失效
标题翻译：长纤维纸浆生产纸浆
公开(公告)号：US08167962B2
公开(公告)日：2012-05-01
申请号：US12100084
申请日：2008-04-09
申请人： Glen A. Smith , William E. Bernier
发明人： Glen A. Smith , William E. Bernier
IPC分类号： C09K3/14
CPC分类号： B24D5/06 , C09K3/1409 , D21B1/063
摘要： Pulp production techniques are disclosed. In one embodiment, pulpstone segments are provided, that include proppant grits in the place of some or all of the conventional abrasive typically used in pulpstone applications. The proppant or proppant-abrasive mixture can be combined into a three-dimensional matrix supported by a vitrified bond. Alternative embodiments use proppant grits in an organic bond or a metal bond or a cement bond (each of which may also include abrasive grits in addition to proppant grits). The proportion of proppant grits to abrasive grits can be varied to produce pulp of varying fiber length distribution as required by the end-user (e.g., paper mill). The greater the proppant concentration, the less cutting of the fibers by the conventional abrasive will occur, producing a greater percentage content of longer fibers. Such pulp produces higher quality paper.
摘要翻译：公布了纸浆生产技术。在一个实施例中，提供了纸浆段，其包括支撑剂砂粒代替通常用于纸浆应用中的一些或全部常规磨料。支撑剂或支撑剂 - 研磨剂混合物可以组合成由玻璃化键支撑的三维基质。替代实施例使用有机粘结剂或金属粘结剂或粘结剂粘合剂中的支撑剂砂砾（除了支撑剂砂砾之外，每种也可包括磨料砂粒）。可以改变支撑剂砂粒对磨料砂粒的比例，以产生根据最终用户（例如造纸厂）所要求的不同纤维长度分布的纸浆。支撑剂浓度越大，将会发生常规研磨剂对纤维的切割越少，从而产生更长的纤维含量。这样的纸浆产生更高质量的纸张。

18. 发明授权

US07566649B2 Compressible films surrounding solder connectors 有权
标题翻译：围绕焊料连接器的可压缩薄膜
公开(公告)号：US07566649B2
公开(公告)日：2009-07-28
申请号：US11858147
申请日：2007-09-20
申请人： William E. Bernier , Tien-Jen Cheng , Marie S. Cole , David E. Eichstadt , Mukta G. Farooq , John A. Fitzsimmons , Lewis S. Goldmann , John U. Knickerbocker , Tasha E. Lopez , David J. Welsh
发明人： William E. Bernier , Tien-Jen Cheng , Marie S. Cole , David E. Eichstadt , Mukta G. Farooq , John A. Fitzsimmons , Lewis S. Goldmann , John U. Knickerbocker , Tasha E. Lopez , David J. Welsh
IPC分类号： H01L21/44 , H01L21/50 , H01L21/48 , H01L23/52 , H01L23/48 , H01L23/485 , H01L23/488
CPC分类号： H01L21/563 , H01L23/3171 , H01L24/12 , H01L24/16 , H01L24/81 , H01L2224/10126 , H01L2224/13099 , H01L2224/131 , H01L2224/13566 , H01L2224/16 , H01L2224/73203 , H01L2224/8121 , H01L2224/81815 , H01L2924/00011 , H01L2924/00013 , H01L2924/00014 , H01L2924/01004 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01075 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01R43/0256 , H05K3/284 , H05K3/3436 , H05K2201/0133 , H05K2201/10977 , Y02P70/613 , H01L2224/29099 , H01L2224/0401
摘要： Disclosed is a method of forming an integrated circuit structure that forms lead-free connectors on a device, surrounds the lead-free connectors with a compressible film, connects the device to a carrier (the lead-free connectors electrically connect the device to the carrier), and fills the gaps between the carrier and the device with an insulating underfill.
摘要翻译：公开了一种形成集成电路结构的方法，其在器件上形成无铅连接器，用可压缩膜围绕无铅连接器，将器件连接到载体（无铅连接器将器件电连接到载体上），并用绝缘底部填充物填充载体和装置之间的间隙。

19. 发明授权

US07170187B2 Low stress conductive polymer bump 有权
标题翻译：低应力导电聚合物凸块
公开(公告)号：US07170187B2
公开(公告)日：2007-01-30
申请号：US10711185
申请日：2004-08-31
申请人： William E. Bernier , Marie S. Cole , Mukta G. Farooq , John U. Knickerbocker , Tasha E. Lopez , Roger A. Quon , David J. Welsh
发明人： William E. Bernier , Marie S. Cole , Mukta G. Farooq , John U. Knickerbocker , Tasha E. Lopez , Roger A. Quon , David J. Welsh
IPC分类号： H01L23/48
CPC分类号： H05K3/321 , H01L24/05 , H01L24/12 , H01L24/16 , H01L24/29 , H01L24/83 , H01L2224/0401 , H01L2224/05557 , H01L2224/13076 , H01L2224/13078 , H01L2224/1308 , H01L2224/131 , H01L2224/1319 , H01L2224/1329 , H01L2224/133 , H01L2224/13339 , H01L2224/13464 , H01L2224/29101 , H01L2224/29111 , H01L2224/2919 , H01L2224/2929 , H01L2224/293 , H01L2224/838 , H01L2924/00013 , H01L2924/01006 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/014 , H01L2924/0665 , H01L2924/0781 , H01L2924/09701 , H01L2924/14 , H01L2924/15787 , H01L2924/15788 , H01L2924/1579 , H05K2201/0212 , H05K2201/0248 , H05K2201/0373 , H05K2201/1025 , H01L2924/00014 , H01L2224/13099 , H01L2924/00 , H01L2924/01026 , H01L2924/00015 , H01L2224/29099 , H01L2224/29199 , H01L2224/29299
摘要： Disclosed is a laminated (or non-laminated) conductive interconnection for joining an integrated circuit device to a device carrier, where the conductive interconnection comprises alternating metal layers and polymer layers. In addition, the polymer can include dendrites, metal projections from the carrier or device, and/or micelle brushes on the outer portion of the polymer. The polymer layers include metal particles and the alternating metal layers and polymer layers form either a cube-shaped structure or a cylinder-shaped structure.
摘要翻译：公开了用于将集成电路器件连接到器件载体的层压（或非层叠）导电互连，其中导电互连包括交替的金属层和聚合物层。此外，聚合物可以包括枝晶，来自载体或器件的金属突起，和/或聚合物外部的胶束刷。聚合物层包括金属颗粒，并且交替的金属层和聚合物层形成立方体结构或圆柱形结构。

20. 发明授权

US06492071B1 Wafer scale encapsulation for integrated flip chip and surface mount technology assembly 失效
标题翻译：用于集成倒装芯片和表面贴装技术组装的晶圆级封装
公开(公告)号：US06492071B1
公开(公告)日：2002-12-10
申请号：US09670410
申请日：2000-09-26
申请人： William E. Bernier , Mark V. Pierson , Ajit K. Trivedi
发明人： William E. Bernier , Mark V. Pierson , Ajit K. Trivedi
IPC分类号： G03F900
CPC分类号： H01L21/56 , H01L24/81 , H01L2224/274 , H01L2224/81801 , H01L2224/83191 , H01L2924/14 , H05K3/1225 , H01L2924/00
摘要： A device and process for applying mixtures of adhesive formulations combined with solder flux such that flip chips may be rapidly encapsulated with such combinations without interfering with subsequent wafer processing steps are provided. Also provided is a wafer stencil designed in such a manner that the saw kerf lines separating individual chip dies are protected from coming into contact with the formulation. Extrusion screening using such wafer stencil is also provided.
摘要翻译：提供了一种用于施加与焊料助焊剂组合的粘合剂制剂的混合物的装置和方法，使得可以用这种组合快速包封倒装芯片而不干扰后续的晶片加工步骤。还提供了以这样的方式设计的晶片模板，即分离各个芯片模具的锯切线不受制剂的接触。还提供了使用这种晶片模板的挤出筛选。

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