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11. 发明授权

US06223276B1 Pipelined processing of short data streams using data prefetching 失效
标题翻译：使用数据预取流水线处理短数据流
公开(公告)号：US06223276B1
公开(公告)日：2001-04-24
申请号：US09053376
申请日：1998-03-31
申请人： Hsien-Hsin Lee , Vladimir Pentkovski , Hsien-Cheng E. Hsieh
发明人： Hsien-Hsin Lee , Vladimir Pentkovski , Hsien-Cheng E. Hsieh
IPC分类号： G06F930
CPC分类号： G06F9/3875 , G06F9/383
摘要： The present invention discloses a method and apparatus for processing strips of data, each strip referencing a plurality of parameter sets stored in a memory. The method comprises: prefetching a plurality of parameter sets referenced in a first strip; performing an operation on each of the prefetched parameter sets; and concatenating a first strip and a second strip to eliminate a memory access latency in the second strip.
摘要翻译：本发明公开了一种用于处理数据条带的方法和装置，每个条带参考存储在存储器中的多个参数集。该方法包括：预取在第一条带中引用的多个参数集; 对每个预取参数集执行操作; 并且连接第一条带和第二条带以消除第二条带中的存储器访问等待时间。

12. 发明授权

US6073210A Synchronization of weakly ordered write combining operations using a fencing mechanism 失效
标题翻译：使用栅栏机制同步弱序写入组合操作
公开(公告)号：US6073210A
公开(公告)日：2000-06-06
申请号：US53377
申请日：1998-03-31
申请人： Salvador Palanca , Vladimir Pentkovski , Subramaniam Maiyuran , Lance Hacking , Roger A. Golliver , Shreekant S. Thakkar
发明人： Salvador Palanca , Vladimir Pentkovski , Subramaniam Maiyuran , Lance Hacking , Roger A. Golliver , Shreekant S. Thakkar
IPC分类号： G06F12/08 , G06F13/16 , G06F13/14 , G06F12/00
CPC分类号： G06F13/1631 , G06F12/0802
摘要： The present invention discloses a method and apparatus for synchronizing weakly ordered write combining operations. A memory controller has a buffer to service memory accesses. A store fence instruction is dispatched to the memory controller. If the buffer contains at least a data written by at least one of the weakly ordered write combining operations prior to the store fence instruction, then the store fence instruction is blocked until a block in the buffer containing the data is globally observed. If the buffer does not contain any data written by at least one of the write combining operations prior to the store fence instruction, then the store fence instruction is accepted by the memory controller.
摘要翻译：本发明公开了一种用于使弱顺序的写入组合操作同步的方法和装置。存储器控制器具有用于服务存储器访问的缓冲器。存储栏指令被发送到存储器控制器。如果缓冲区至少包含由存储栏指令之前的弱顺序写入组合操作中的至少一个写入的数据，则存储栅栏指令被阻止，直到包含数据的缓冲区中的块被全局观察到。如果在存储栏指令之前缓冲器不包含写入组合操作中的至少一个写入的任何数据，则存储器控制器接受存储栅栏指令。

13. 发明授权

US5995122A Method and apparatus for parallel conversion of color values from a single precision floating point format to an integer format 失效
标题翻译：将颜色值从单精度浮点格式并行转换为整数格式的方法和装置
公开(公告)号：US5995122A
公开(公告)日：1999-11-30
申请号：US71468
申请日：1998-04-30
申请人： Hsien-Cheng E. Hsieh , Thomas R. Huff , Vladimir Pentkovski , Patrice Roussel , Shreekant S. Thakkar
发明人： Hsien-Cheng E. Hsieh , Thomas R. Huff , Vladimir Pentkovski , Patrice Roussel , Shreekant S. Thakkar
IPC分类号： H03M7/24 , G06F13/00 , G06F15/80
CPC分类号： H03M7/24
摘要： A method and apparatus for parallel processing of graphics data are described. A number of color components are stored in a floating point format in at least one register of a set of 128-bit registers in a packed format. The color components in the floating point format are converted to numbers in an integer format. The numbers in the integer format are placed in at least one register of a set of 64-bit registers in the packed format. Color components are assembled for image pixels from the numbers in the integer format.
摘要翻译：描述用于并行处理图形数据的方法和装置。多个颜色分量以压缩格式在一组128位寄存器的至少一个寄存器中以浮点格式存储。浮点格式的颜色分量将以整数格式转换为数字。整数格式的数字以打包格式放置在一组64位寄存器的至少一个寄存器中。从整数格式的数字组装图像像素的颜色分量。

14. 发明授权

US07467286B2 Executing partial-width packed data instructions 有权
标题翻译：执行部分宽度打包的数据指令
公开(公告)号：US07467286B2
公开(公告)日：2008-12-16
申请号：US11126049
申请日：2005-05-09
申请人： Mohammad Abdallah , James Coke , Vladimir Pentkovski , Patrice Roussel , Shreekant S. Thakkar
发明人： Mohammad Abdallah , James Coke , Vladimir Pentkovski , Patrice Roussel , Shreekant S. Thakkar
IPC分类号： H04Q3/00
CPC分类号： G06F9/3875 , G06F9/30014 , G06F9/30036 , G06F9/30112 , G06F9/3013 , G06F9/30134 , G06F9/30145 , G06F9/30167 , G06F9/3017 , G06F9/30181 , G06F9/30196 , G06F9/384 , G06F9/3885
摘要： A method and apparatus are provided for executing packed data instructions. According to one aspect of the invention, a processor includes registers, a register renaming unit coupled to the registers, a decoder coupled to the register renaming unit, and a partial-width execution unit coupled to the decoder. The register renaming unit provides an architectural register file to store packed data operands that include data elements. The decoder is to decode a first and second set of instructions that each specify one or more registers in the architectural register file. Each of the instructions in the first set specify operations to be performed on all of the data elements. In contrast, each of the instructions in the second set specify operations to be performed on only a subset of the data elements. The partial-width execution unit is to execute operations specified by either the first or second set of instructions.
摘要翻译：提供了一种用于执行打包数据指令的方法和装置。根据本发明的一个方面，处理器包括寄存器，耦合到寄存器的寄存器重命名单元，耦合到寄存器重命名单元的解码器以及耦合到解码器的部分宽度执行单元。寄存器重命名单元提供架构寄存器文件来存储包括数据元素的打包数据操作数。解码器是对第一和第二组指令进行解码，每组指令在架构寄存器文件中指定一个或多个寄存器。第一组中的每个指令指定要对所有数据元素执行的操作。相比之下，第二组中的每个指令指定仅对数据元素的子集执行的操作。部分宽度执行单元是执行由第一组或第二组指令指定的操作。

15. 发明授权

US06369813B2 Processing polygon meshes using mesh pool window 失效
标题翻译：使用网格池窗口处理多边形网格
公开(公告)号：US06369813B2
公开(公告)日：2002-04-09
申请号：US09109257
申请日：1998-06-30
申请人： Vladimir Pentkovski , Deep Buch , Michael K. Dwyer , Hsien-Hsin Lee , Hsien-Cheng E. Hsieh
发明人： Vladimir Pentkovski , Deep Buch , Michael K. Dwyer , Hsien-Hsin Lee , Hsien-Cheng E. Hsieh
IPC分类号： G06T1500
CPC分类号： G06T17/20
摘要： The present invention is directed to a method and apparatus for processing normalized meshes. The normalized meshes are formed by N polygons which have M vertices. M vertex coordinates are stored in a vertex array corresponding to the M vertices of the N polygons. N polygon indices are stored in an index array. Each of the N polygon indices references a predetermined number of the M vertex coordinates. A first subset of the index array having N1 polygon indices is determined. A second subset of the vertex array is selected such that the second subset contains M1 vertex coordinates corresponding entirely to the N1 polygon indices in the first subset. The second subset defines a window having a small size relative to the vertex array. The M1 vertex coordinates in the second subset are processed to generate processed data. The processed data are then concurrently sent to a graphics processor in an on-line manner.
摘要翻译：本发明涉及一种用于处理归一化网格的方法和装置。归一化网格由具有M个顶点的N个多边形形成。 M顶点坐标存储在与N个多边形的M个顶点对应的顶点数组中。 N个多边形索引存储在索引数组中。 N个多边形索引中的每一个引用预定数量的M个顶点坐标。确定具有N1个多边形索引的索引阵列的第一子集。选择顶点阵列的第二子集，使得第二子集包含完全对应于第一子集中的N1多边形索引的M1顶点坐标。第二个子集定义相对于顶点数组具有小尺寸的窗口。处理第二个子集中的M1顶点坐标以产生处理后的数据。然后，处理的数据以在线方式同时发送到图形处理器。

16. 发明授权

US06275904B1 Cache pollution avoidance instructions 失效
标题翻译：缓存污染回避说明
公开(公告)号：US06275904B1
公开(公告)日：2001-08-14
申请号：US09053385
申请日：1998-03-31
申请人： Srinivas Chennupaty , Shreekant S. Thakkar , Thomas Huff , Vladimir Pentkovski
发明人： Srinivas Chennupaty , Shreekant S. Thakkar , Thomas Huff , Vladimir Pentkovski
IPC分类号： G06F1208
CPC分类号： G06F12/0886 , G06F9/30018 , G06F9/30036 , G06F9/30047 , G06F12/0804 , G06F12/0888
摘要： A computer system and method for providing cache memory management. The computer system comprises a main memory having a plurality of main memory addresses each having a corresponding data entry, and a processor coupled to the main memory. At least one cache memory is coupled to the processor. The at least one cache memory has a cache directory with a plurality of addresses and a cache controller having a plurality of data entries corresponding to the plurality of addresses. The processor receives an instruction having an operand address and determines if the operand address matches one of the plurality of addresses in the cache directory. If so, the processor updates a data entry in the cache controller corresponding to the matched address. Otherwise, a data entry corresponding to the operand address in the main memory is updated.
摘要翻译：一种用于提供高速缓存存储器管理的计算机系统和方法。计算机系统包括具有多个主存储器地址的主存储器，每个主存储器地址都具有对应的数据条目，以及耦合到主存储器的处理器。至少一个高速缓存存储器耦合到处理器。所述至少一个高速缓冲存储器具有具有多个地址的高速缓存目录和具有对应于所述多个地址的多个数据条目的高速缓存控制器。处理器接收具有操作数地址的指令，并确定操作数地址是否匹配高速缓存目录中的多个地址之一。如果是这样，则处理器更新对应于匹配地址的高速缓存控制器中的数据条目。否则，更新与主存储器中的操作数地址相对应的数据条目。

17. 发明授权

US06266769B1 Conversion between packed floating point data and packed 32-bit integer data in different architectural registers 失效
公开(公告)号：US06266769B1
公开(公告)日：2001-07-24
申请号：US09070891
申请日：1998-04-30
申请人： Mohammad A. F. Abdallah , Hsien-Cheng E. Hsieh , Thomas R. Huff , Vladimir Pentkovski , Patrice Roussel , Shreekant S. Thakkar
发明人： Mohammad A. F. Abdallah , Hsien-Cheng E. Hsieh , Thomas R. Huff , Vladimir Pentkovski , Patrice Roussel , Shreekant S. Thakkar
IPC分类号： G06F900
CPC分类号： H03M7/24
摘要： A method and instruction for converting a number between a floating point format and an integer format are described. Numbers are stored in the integer format in a register of a first set of architectural registers in a packed format. At least one of the numbers in the integer format is converted to at least one number in the floating point format. The numbers in the floating point format are placed in a register of a second set of architectural registers in a packed format.

18. 发明授权

US6122725A Executing partial-width packed data instructions 失效
标题翻译：执行部分宽度打包的数据指令
公开(公告)号：US6122725A
公开(公告)日：2000-09-19
申请号：US53002
申请日：1998-03-31
申请人： Patrice Roussel , Ticky Thakkar , Mohammad A. Abdallah , Vladimir Pentkovski , James Coke
发明人： Patrice Roussel , Ticky Thakkar , Mohammad A. Abdallah , Vladimir Pentkovski , James Coke
IPC分类号： G06F9/30 , G06F9/302 , G06F9/318 , G06F9/38
CPC分类号： G06F9/3822 , G06F9/30014 , G06F9/30036 , G06F9/30109 , G06F9/3013 , G06F9/30145 , G06F9/30181 , G06F9/30185 , G06F9/30196
摘要： A method and apparatus are provided for executing scalar packed data instructions. According to one aspect of the invention, a processor includes a plurality of registers, a register renaming unit coupled to the plurality of registers, and a decoder coupled to the register renaming unit. The register renaming unit provides an architectural register file to store packed data operands each of which include a plurality of data elements. The decoder is configured to decode a first and second set of instructions (e.g., a set of full-width packed data instructions and a set of partial-width packed data instructions) that each specify one or more registers in the architectural register file. Each of the instructions in the first set of instructions specify operations to be performed on all of the data elements stored in the one or more specified registers. In contrast, each of the instructions in the second set of instructions specify operations to be performed on only a subset of the data element stored in the one or more specified registers.
摘要翻译：提供了一种用于执行标量打包数据指令的方法和装置。根据本发明的一个方面，处理器包括多个寄存器，耦合到多个寄存器的寄存器重命名单元和耦合到寄存器重命名单元的解码器。寄存器重命名单元提供架构寄存器文件以存储打包数据操作数，每个数据操作数包括多个数据元素。解码器被配置为对构造寄存器文件中的每个指定一个或多个寄存器的第一和第二组指令（例如，一组全宽度压缩数据指令和一组部分宽度压缩数据指令）进行解码。第一组指令中的每个指令指定要对存储在一个或多个指定寄存器中的所有数据元素执行的操作。相反，第二组指令中的每个指令指定仅对存储在一个或多个指定寄存器中的数据元素的子集执行的操作。

19. 发明授权

US6122715A Method and system for optimizing write combining performance in a shared buffer structure 失效
标题翻译：用于优化共享缓冲区结构中的写入组合性能的方法和系统
公开(公告)号：US6122715A
公开(公告)日：2000-09-19
申请号：US053384
申请日：1998-03-31
申请人： Salvador Palanca , Vladimir Pentkovski , Niranjan L. Cooray , Subramaniam Maiyuran , Angad Narang
发明人： Salvador Palanca , Vladimir Pentkovski , Niranjan L. Cooray , Subramaniam Maiyuran , Angad Narang
IPC分类号： G06F12/08 , G06F5/06
CPC分类号： G06F12/0804
摘要： An apparatus and method of optimizing write combining operations using write combining buffers. A plurality of control fields are assigned to each of the write combining buffers. Each of the control fields has a value corresponding to one of a plurality of write combining states. A first of the plurality of write combining states transitions to a second of the plurality of write combining states in response to a write combining operation.
摘要翻译：一种使用写入组合缓冲器优化写入组合操作的装置和方法。多个控制字段被分配给每个写合并缓冲器。每个控制字段具有对应于多个写合并状态之一的值。多个写入组合状态中的第一个响应写入组合操作转换到多个写入组合状态中的第二个。

20. 发明授权

US06801208B2 System and method for cache sharing 有权
标题翻译：用于缓存共享的系统和方法
公开(公告)号：US06801208B2
公开(公告)日：2004-10-05
申请号：US09750750
申请日：2000-12-27
申请人： Jagganath Keshava , Vladimir Pentkovski , Subramaniam Maiyuran , Salvador Palanca , Hsin-Chu Tsai
发明人： Jagganath Keshava , Vladimir Pentkovski , Subramaniam Maiyuran , Salvador Palanca , Hsin-Chu Tsai
IPC分类号： G09G536
CPC分类号： G06F3/14 , G06F12/084 , G09G5/001 , G09G5/393 , G09G2330/021 , G09G2350/00
摘要： A system and method for cache sharing. The system is a microprocessor comprising a processor core and a graphics engine, each coupled to a cache memory. The microprocessor also includes a driver to direct how the cache memory is shared by the processor core and the graphics engine. The method comprises receiving a memory request from a graphics application program and determining whether a cache memory that may be shared between a processor core and a cache memory is available to be shared. If the cache memory is available to be shared, a first portion of the cache memory is allocated to the processor core and a second portion of the cache memory is allocated to the graphics engine. The method and microprocessor may be included in a computing device.
摘要翻译：一种用于缓存共享的系统和方法。该系统是包括处理器核心和图形引擎的微处理器，每个耦合到高速缓冲存储器。微处理器还包括一个驱动程序，用于指示高速缓冲存储器如何由处理器核心和图形引擎共享。该方法包括从图形应用程序接收存储器请求并确定可以在处理器核心和高速缓冲存储器之间共享的高速缓存存储器是否可共享。如果高速缓冲存储器可用于共享，则高速缓冲存储器的第一部分被分配给处理器核心，高速缓冲存储器的第二部分被分配给图形引擎。方法和微处理器可以包括在计算设备中。

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