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11. 发明申请

US20090267149A1 SOURCE/DRAIN JUNCTION FOR HIGH PERFORMANCE MOSFET FORMED BY SELECTIVE EPI PROCESS 有权
标题翻译：通过选择性EPI工艺形成的高性能MOSFET的源极/漏极连接
公开(公告)号：US20090267149A1
公开(公告)日：2009-10-29
申请号：US12109025
申请日：2008-04-24
申请人： Xuefeng Hua , Johnathan E. Faltermeier , Toshiharu Furukawa , Oleg Gluschenkov
发明人： Xuefeng Hua , Johnathan E. Faltermeier , Toshiharu Furukawa , Oleg Gluschenkov
IPC分类号： H01L29/786 , H01L21/336 , H01L21/84
CPC分类号： H01L29/66636 , H01L29/1083 , H01L29/665 , H01L29/6653 , H01L29/66772 , H01L29/7848 , H01L29/78609 , H01L29/78621 , H01L29/78696
摘要： In a field effect transistor (FET), halo features may be formed by etching into the surface of a silicon layer followed by a step of growing a first epitaxial silicon (epi-Si) layer on the etched silicon layer. Source (S) and drain (D), as well as S/D extension features may similarly be formed by etching an epitaxial silicon layer, then filling with another epitaxial layer. Source and Drain, and extensions, and halo, which are normally formed by diffusion, may be formed as discrete elements by etching and filling (epi-Si). This may provide a shallow, highly activated, abrupt S/D extension, an optimally formed halo and deep S/D diffusion doping, and maximized improvement of channel mobility from the compressive or tensile stress from e-SiGe or e-SiC.
摘要翻译：在场效应晶体管（FET）中，可以通过蚀刻到硅层的表面中，随后在蚀刻的硅层上生长第一外延硅（epi-Si）层的步骤来形成晕圈特征。源极（S）和漏极（D）以及S / D延伸特征可以类似地通过蚀刻外延硅层形成，然后用另一个外延层填充。通常通过扩散形成的源极和漏极，延伸部分和光晕可以通过蚀刻和填充（epi-Si）形成为离散元件。这可以提供浅的，高活化的，突然的S / D延伸，最佳形成的光晕和深S / D扩散掺杂，并且最大限度地改善来自e-SiGe或e-SiC的压缩或拉伸应力的沟道迁移率。

12. 发明授权

US07605447B2 Highly manufacturable SRAM cells in substrates with hybrid crystal orientation 有权
标题翻译：具有混合晶体取向的基板中的高度可制造的SRAM单元
公开(公告)号：US07605447B2
公开(公告)日：2009-10-20
申请号：US11162780
申请日：2005-09-22
申请人： Bruce B. Doris , Gregory Costrini , Oleg Gluschenkov , Meikei Ieong , Nakgeuon Seong
发明人： Bruce B. Doris , Gregory Costrini , Oleg Gluschenkov , Meikei Ieong , Nakgeuon Seong
IPC分类号： H01L29/06 , H01L29/04 , H01L27/11
CPC分类号： H01L27/1104 , H01L27/11 , Y10S257/903 , Y10S438/973
摘要： The present invention relates to a semiconductor device structure that includes at least one SRAM cell formed in a substrate. Such SRAM cell comprises two pull-up transistors, two pull-down transistors, and two pass-gate transistors. The pull-down transistors and the pass-gate transistors are substantially similar in channel widths and have substantially similar source-drain doping concentrations, while the SRAM cell has a beta ratio of at least 1.5. The substrate preferably comprises a hybrid substrate with at two isolated sets of regions, while carrier mobility in these two sets of regions differentiates by a factor of at least about 1.5. More preferably, the pull-down transistors of the SRAM cell are formed in one set of regions, and the pass-gate transistors are formed in the other set of regions, so that current flow in the pull-down transistors is larger than that in the pass-gate transistors.
摘要翻译：本发明涉及一种半导体器件结构，其包括在衬底中形成的至少一个SRAM单元。这样的SRAM单元包括两个上拉晶体管，两个下拉晶体管和两个通过栅极晶体管。下拉晶体管和栅极晶体管在沟道宽度上基本相似，并且具有基本相似的源极 - 漏极掺杂浓度，而SRAM单元的β比率至少为1.5。衬底优选地包括具有两个分离的区域集合的混合衬底，而这两组区域中的载流子迁移率以至少约1.5的因子差分。更优选地，SRAM单元的下拉晶体管形成在一组区域中，并且栅极晶体管形成在另一组区域中，使得下拉晶体管中的电流大于传输栅晶体管。

13. 发明授权

US07585704B2 Method of producing highly strained PECVD silicon nitride thin films at low temperature 失效
标题翻译：在低温下生产高应变PECVD氮化硅薄膜的方法
公开(公告)号：US07585704B2
公开(公告)日：2009-09-08
申请号：US10907454
申请日：2005-04-01
申请人： Michael P. Belyansky , Oleg Gluschenkov , Ying Li , Anupama Mallikarjunan
发明人： Michael P. Belyansky , Oleg Gluschenkov , Ying Li , Anupama Mallikarjunan
IPC分类号： H01L21/82
CPC分类号： H01L21/0217 , C23C16/345 , C23C16/45523 , H01L21/02271 , H01L21/02274 , H01L21/3185 , H01L21/823807 , H01L21/823864 , H01L29/7833 , H01L29/7843
摘要： A method for increasing the level of stress for amorphous thin film stressors by means of modifying the internal structure of such stressors is provided. The method includes first forming a first portion of an amorphous film stressor material on at least a surface of a substrate, said first portion having a first state of mechanical strain defining a first stress value. After the forming step, the first portion of the amorphous film stressor material is densified such that the first state of mechanical strain is not substantially altered, while increasing the first stress value. In some embodiments, the steps of forming and densifying are repeated any number of times to obtain a preselected and desired thickness for the stressor.
摘要翻译：提供了通过改变这种压力源的内部结构来增加非晶薄膜应力的应力水平的方法。该方法包括首先在基底的至少一个表面上形成非晶膜应力材料的第一部分，所述第一部分具有限定第一应力值的第一机械应变状态。在成形步骤之后，非晶态应力材料的第一部分被致密化，使得在增加第一应力值的同时，基本上不改变机械应变的第一状态。在一些实施例中，形成和致密化的步骤重复任意次数，以获得应激源的预选和期望的厚度。

14. 发明授权

US07504700B2 Method of forming an ultra-thin [[HfSiO]] metal silicate film for high performance CMOS applications and semiconductor structure formed in said method 有权
标题翻译：形成用于高性能CMOS应用的超薄[[HfSiO]]金属硅酸盐膜和在所述方法中形成的半导体结构的方法
公开(公告)号：US07504700B2
公开(公告)日：2009-03-17
申请号：US10907935
申请日：2005-04-21
申请人： Wenjuan Zhu , Michael P. Chudzik , Oleg Gluschenkov , Dae-Gyu Park , Akihisa Sekiguchi
发明人： Wenjuan Zhu , Michael P. Chudzik , Oleg Gluschenkov , Dae-Gyu Park , Akihisa Sekiguchi
IPC分类号： H01L27/088 , H01L21/3205 , H01L21/4763
CPC分类号： H01L21/28185 , H01L21/28097 , H01L21/28229 , H01L21/823857 , H01L29/4966 , H01L29/4975 , H01L29/517
摘要： A semiconductor structure and method of forming the same, comprising forming a uniform buffer layer of diffusion-controlling stable material on top of a base gate dielectric layer, and then forming a uniform layer which contains a source of transitional metal atoms, and then annealing the structure to diffuse the transitional metal atoms from their source through the diffusion-controlling material and into the base gate dielectric layer.
摘要翻译：一种半导体结构及其制造方法，包括在基极电介质层的顶部形成扩散控制稳定材料的均匀缓冲层，然后形成含有过渡金属原子源的均匀层，然后退火结构将过渡金属原子从其源极扩散通过扩散控制材料并进入基极栅极电介质层。

15. 发明授权

US07452761B2 Hybrid SOI-bulk semiconductor transistors 失效
标题翻译：混合SOI体半导体晶体管
公开(公告)号：US07452761B2
公开(公告)日：2008-11-18
申请号：US11870436
申请日：2007-10-11
申请人： Huilong Zhu , Philip J. Oldiges , Bruce B. Doris , Xinlin Wang , Oleg Gluschenkov , Huajie Chen , Ying Zhang
发明人： Huilong Zhu , Philip J. Oldiges , Bruce B. Doris , Xinlin Wang , Oleg Gluschenkov , Huajie Chen , Ying Zhang
IPC分类号： H01L21/00 , H01L21/84 , H01L21/336
CPC分类号： H01L29/7849 , H01L29/0653 , H01L29/1054 , H01L29/7842 , H01L29/78603 , H01L29/78612 , H01L29/78618 , H01L29/78687
摘要： Channel depth in a field effect transistor is limited by an intra-layer structure including a discontinuous film or layer formed within a layer or substrate of semiconductor material. Channel depth can thus be controlled much in the manner of SOI or UT-SOI technology but with less expensive substrates and greater flexibility of channel depth control while avoiding floating body effects characteristic of SOI technology. The profile or cross-sectional shape of the discontinuous film may be controlled to an ogee or staircase shape to improve short channel effects and reduce source/drain and extension resistance without increase of capacitance. Materials for the discontinuous film may also be chosen to impose stress on the transistor channel from within the substrate or layer and provide increased levels of such stress to increase carrier mobility. Carrier mobility may be increased in combination with other meritorious effects.
摘要翻译：场效应晶体管中的沟道深度由包括在半导体材料的层或衬底内形成的不连续膜或层的层内结构限制。因此，可以以SOI或UT-SOI技术的方式控制通道深度，但是具有较便宜的衬底和更大的通道深度控制的灵活性，同时避免SOI技术的浮体效应特性。不连续膜的轮廓或横截面形状可以被控制为奥格或阶梯形状，以改善短通道效应，并且在不增加电容的情况下降低源极/漏极和延伸电阻。也可以选择用于不连续膜的材料以在衬底或层内从晶体管沟道施加应力，并提供增加的这种应力水平以增加载流子迁移率。携带者的流动性可能会与其他有利的影响相结合。

16. 发明申请

US20080206965A1 STRAINED SILICON MADE BY PRECIPITATING CARBON FROM Si(1-x-y)GexCy ALLOY 审中-公开
标题翻译：通过从Si（1-x-y）GexCy合金中制备碳制成的应变硅
公开(公告)号：US20080206965A1
公开(公告)日：2008-08-28
申请号：US11679308
申请日：2007-02-27
申请人： Oleg Gluschenkov , Yaocheng Liu , Alexander Reznicek , Devendra Sadana
发明人： Oleg Gluschenkov , Yaocheng Liu , Alexander Reznicek , Devendra Sadana
IPC分类号： H01L21/20
CPC分类号： H01L29/4983 , H01L21/02529 , H01L21/02532 , H01L21/02667 , H01L29/165 , H01L29/6656 , H01L29/66575 , H01L29/66636 , H01L29/78 , H01L29/7848
摘要： Disclosed herein is a method of preparing strained silicon comprising annealing a carbon-doped silicon-germanium (SiGe:C) alloy containing region disposed adjacent to a silicon region, wherein the lattice constant of the SiGe:C alloy after annealing is greater than that of the SiGe:C alloy prior to annealing. The method can be used to prepare articles including metal oxide semiconductor field effect transistor (MOSFET) devices.
摘要翻译：本发明公开了一种制备应变硅的方法，包括退火邻近硅区的碳掺杂硅 - 锗（SiGe：C）合金含有区域，其中退火后SiGe：C合金的晶格常数大于退火之前的SiGe：C合金。该方法可用于制备包括金属氧化物半导体场效应晶体管（MOSFET）器件的制品。

17. 发明申请

US20080050847A1 SINGLE IC-CHIP DESIGN ON WAFER WITH AN EMBEDDED SENSOR UTILIZING RF CAPABILITIES TO ENABLE REAL-TIME DATA TRANSMISSION 审中-公开
标题翻译：采用嵌入式传感器的单片IC芯片设计，利用RF功能实现实时数据传输
公开(公告)号：US20080050847A1
公开(公告)日：2008-02-28
申请号：US11923856
申请日：2007-10-25
申请人： Oleg Gluschenkov , Timothy Little , Gary Snyder
发明人： Oleg Gluschenkov , Timothy Little , Gary Snyder
IPC分类号： H01L21/00 , G08B1/08
CPC分类号： H01L21/67294
摘要： An apparatus and method for real-time monitoring process conditions of a semiconductor wafer processing operation. A semiconductor wafer subject to processing in a wafer processing tool is embedded with one or more sensor devices. In response to receipt of wireless electromagnetic signals, the embedded sensor devices are activated for generating sensory data. The electromagnetic signals are further utilized to activate a transmitter device provided in the wafer to wirelessly transmit the sensory data generated from the activated embedded sensor device. The transmitted electromagnetic signals comprising the sensory data are communicated to a control device for controlling processing conditions of the process tool based upon the received sensory data.
摘要翻译：一种用于实时监测半导体晶片处理操作的工艺条件的装置和方法。在晶片处理工具中进行处理的半导体晶片被嵌入一个或多个传感器装置。响应于接收到无线电磁信号，嵌入式传感器装置被激活以产生感觉数据。进一步利用电磁信号来激活设置在晶片中的发射器装置，以无线地传输由激活的嵌入式传感器装置产生的感觉数据。包含感官数据的发送的电磁信号被传送到控制装置，用于基于所接收的感觉数据来控制处理工具的处理条件。

18. 发明申请

US20080001227A1 STRUCTURE AND METHOD FOR MANUFACTURING DOUBLE GATE FINFET WITH ASYMMETRIC HALO 有权
标题翻译：使用不对称HALO制造双门FINFET的结构和方法
公开(公告)号：US20080001227A1
公开(公告)日：2008-01-03
申请号：US11427409
申请日：2006-06-29
申请人： Huilong Zhu , Oleg Gluschenkov , Jing Wang
发明人： Huilong Zhu , Oleg Gluschenkov , Jing Wang
IPC分类号： H01L27/12
CPC分类号： H01L29/78612 , H01L29/66795 , H01L29/7855 , H01L29/7856
摘要： A finFet controls conduction channel conditions using one of two gate structures, preferably having a gate length shorter than the other gate structure to limit capacitance, which are opposed across the conduction channel. An asymmetric halo impurity implant performed at an angle adjacent to the gate structure for controlling conduction channel conditions forms a super steep retrograde well to limit short channel effects in the portion of the conduction channel which is controlled by the other gate structure.
摘要翻译： finFet使用两个栅极结构之一来控制传导通道条件，优选地具有比另一个栅极结构更短的栅极长度，以限制在导电沟道上相对的电容。以与栅极结构相邻的角度执行的用于控制导通通道条件的不对称卤素杂质注入形成了超陡逆行阱，以限制由另一栅极结构控制的导电沟道部分中的短沟道效应。

19. 发明授权

US07282403B2 Temperature stable metal nitride gate electrode 有权
标题翻译：温度稳定的金属氮化物栅电极
公开(公告)号：US07282403B2
公开(公告)日：2007-10-16
申请号：US11203952
申请日：2005-08-15
申请人： Dae-Gyu Park , Cyril Cabral, Jr. , Oleg Gluschenkov , Hyungjun Kim
发明人： Dae-Gyu Park , Cyril Cabral, Jr. , Oleg Gluschenkov , Hyungjun Kim
IPC分类号： H01L21/8238 , H01L21/3205 , H01L21/4763
CPC分类号： H01L21/823842 , H01L21/823857 , Y10S257/90 , Y10S438/942
摘要： An integrated circuit is provided including an FET gate structure formed on a substrate. This structure includes a gate dielectric on the substrate, and a metal nitride layer overlying the gate dielectric and in contact therewith. This metal nitride layer is characterized as MNx, where M is one of W, Re, Zr, and Hf, and x is in the range of about 0.7 to about 1.5. Preferably the layer is of WNx, and x is about 0.9. Varying the nitrogen concentration in the nitride layer permits integration of different FET characteristics on the same chip. In particular, varying x in the WNx layer permits adjustment of the threshold voltage in the different FETs. The polysilicon depletion effect is substantially reduced, and the gate structure can be made thermally stable up to about 1000° C.
摘要翻译：提供了一种集成电路，其包括形成在衬底上的FET栅极结构。该结构包括衬底上的栅极电介质和覆盖栅极电介质并与其接触的金属氮化物层。该金属氮化物层的特征在于MN x，其中M是W，Re，Zr和Hf之一，x在约0.7至约1.5的范围内。优选地，该层为W N x X，x为约0.9。改变氮化物层中的氮浓度允许在同一芯片上集成不同的FET特性。特别地，在WN 层中改变x允许调节不同FET中的阈值电压。多晶硅耗尽效应显着降低，并且栅极结构可以在高达约1000℃下热稳定。

20. 发明申请

US20070063278A1 HIGHLY MANUFACTURABLE SRAM CELLS IN SUBSTRATES WITH HYBRID CRYSTAL ORIENTATION 有权
标题翻译：具有混合晶体取向的衬底中的高度可制造的SRAM电池
公开(公告)号：US20070063278A1
公开(公告)日：2007-03-22
申请号：US11162780
申请日：2005-09-22
申请人： Bruce Doris , Gregory Costrini , Oleg Gluschenkov , Meikei Ieong , Nakgeuon Seong
发明人： Bruce Doris , Gregory Costrini , Oleg Gluschenkov , Meikei Ieong , Nakgeuon Seong
IPC分类号： H01L27/12
CPC分类号： H01L27/1104 , H01L27/11 , Y10S257/903 , Y10S438/973
摘要： The present invention relates to a semiconductor device structure that includes at least one SRAM cell formed in a substrate. Such SRAM cell comprises two pull-up transistors, two pull-down transistors, and two pass-gate transistors. The pull-down transistors and the pass-gate transistors are substantially similar in channel widths and have substantially similar source-drain doping concentrations, while the SRAM cell has a beta ratio of at least 1.5. The substrate preferably comprises a hybrid substrate with at two isolated sets of regions, while carrier mobility in these two sets of regions differentiates by a factor of at least about 1.5. More preferably, the pull-down transistors of the SRAM cell are formed in one set of regions, and the pass-gate transistors are formed in the other set of regions, so that current flow in the pull-down transistors is larger than that in the pass-gate transistors.
摘要翻译：本发明涉及一种半导体器件结构，其包括在衬底中形成的至少一个SRAM单元。这样的SRAM单元包括两个上拉晶体管，两个下拉晶体管和两个通过栅极晶体管。下拉晶体管和栅极晶体管在沟道宽度上基本相似，并且具有基本相似的源极 - 漏极掺杂浓度，而SRAM单元的β比率至少为1.5。衬底优选地包括具有两个分离的区域集合的混合衬底，而这两组区域中的载流子迁移率以至少约1.5的因子差分。更优选地，SRAM单元的下拉晶体管形成在一组区域中，并且栅极晶体管形成在另一组区域中，使得下拉晶体管中的电流大于传输栅晶体管。

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