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11. 发明专利

JP2013211427A Semiconductor device and manufacturing method of the same 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2013211427A
公开(公告)日：2013-10-10
申请号：JP2012080944
申请日：2012-03-30
申请人： Toshiba Corp , 株式会社東芝
发明人： SHIMA SHINYA , HONMA SOICHI
IPC分类号： H01L23/532 , H01L21/3205 , H01L21/768 , H01L23/12 , H01L23/522
CPC分类号： H01L24/05 , H01L2224/02166 , H01L2224/04042 , H01L2224/48463 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device which improves reliability and productivity by inhibiting deterioration in insulation reliability and the like, which is caused based on variation in a depth direction of a reformed region of an insulation resin layer.SOLUTION: A semiconductor device of an embodiment comprises: an insulation resin layer 5 which is provided on a semiconductor substrate 2 having a first wiring layer 3 and which has an opening 6 for exposing a part of the first wiring layer 3; and a second wiring layer 7 provided on the insulation resin layer 5. The second wiring layer 7 is composed of an electroless metal plating film. The insulation resin layer 5 includes a laminated film of a first resin layer 10 and a second resin layer 12. The electroless metal plating film has an anchor layer 14 generated by immersion of plated metal into the insulation resin layer 5. The anchor layer 14 is formed only in the second resin layer 11.
摘要翻译：要解决的问题：提供一种半导体器件，其通过抑制由绝缘树脂层的重整区域的深度方向的变化引起的绝缘可靠性等的劣化来提高可靠性和生产率。解决方案：半导体器件实施例包括：绝缘树脂层5，其设置在具有第一布线层3的半导体基板2上，并且具有用于暴露第一布线层3的一部分的开口6; 以及设置在绝缘树脂层5上的第二布线层7.第二布线层7由化学镀金属膜构成。绝缘树脂层5包括第一树脂层10和第二树脂层12的层叠膜。无电解金属镀膜具有通过将电镀金属浸渍到绝缘树脂层5中而产生的锚定层14.锚层14是仅形成在第二树脂层11中。

12. 发明专利

JP2004134821A Semiconductor apparatus 有权
公开(公告)号：JP2004134821A
公开(公告)日：2004-04-30
申请号：JP2004031161
申请日：2004-02-06
申请人： Toshiba Corp , 株式会社東芝
发明人： YAMADA HIROSHI , TOGASAKI TAKASHI , SAITO MASAYUKI , HONMA SOICHI , MORI MIKI
IPC分类号： H01L21/60 , H01L21/56
CPC分类号： H01L2224/16 , H01L2224/26175 , H01L2224/73104 , H01L2224/73204 , H01L2224/83102 , H01L2224/83104 , H01L2224/83191 , H01L2224/83192 , H01L2224/92125 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/15151 , H01L2924/3025
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor apparatus having an improvement in reliability by preventing the occurrence of bubbles from resin disposed in a gap between a semiconductor device and a circuit board. SOLUTION: The semiconductor apparatus has a circuit board and a semiconductor device mounted on the board through bump electrodes, wherein resin is disposed in a gap between the circuit board and the semiconductor device, and around the semiconductor device. The bump electrodes are formed along the circumference of the semiconductor device, and a concave portion is formed in an area surrounded by the bump electrodes on the surface of the circuit board. COPYRIGHT: (C)2004,JPO

13. 发明专利

JP2014056370A Semiconductor memory card 有权
标题翻译：半导体存储卡
公开(公告)号：JP2014056370A
公开(公告)日：2014-03-27
申请号：JP2012200159
申请日：2012-09-12
申请人： Toshiba Corp , 株式会社東芝
发明人： DOI KAZUHIDE , HONMA SOICHI , WATANABE KATSUYOSHI , NISHIYAMA TAKU , IKUTA TAKESHI , OKUMURA NAOHISA
IPC分类号： G06K19/077 , B42D25/305
CPC分类号： H01L23/495 , G06K19/07732 , H01L21/0201 , H01L23/3107 , H01L23/49551 , H01L23/49558 , H01L23/49575 , H01L23/49589 , H01L24/05 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/80 , H01L2224/02166 , H01L2224/04042 , H01L2224/05624 , H01L2224/05644 , H01L2224/05664 , H01L2224/451 , H01L2224/48091 , H01L2224/4813 , H01L2224/48137 , H01L2224/48247 , H01L2224/48463 , H01L2224/48465 , H01L2924/12042 , H01L2924/181 , H01L2924/1815 , H01L2924/19041 , H01L2924/19105 , H01L2924/19107 , H01L2924/00014 , H01L2924/01029 , H01L2924/00 , H01L2924/00012
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor memory card that improves an exposure property of an external connection terminal after achieving a reduction in costs by using a lead frame.SOLUTION: A semiconductor memory card 1 according to an embodiment includes: a lead frame 2 provided with an external connection terminal 3, a lead part 4, a chip component mounting part 5 and a semiconductor chip mounting part 6; a chip component 7 mounted on the chip component mounting part 5; and a controller chip 8 and a memory chip 9 mounted on the semiconductor chip mounting part 6. The lead frame 2 is sealed with resin. A sealing resin layer 10 has a recessed part 15 provided on a first plane 10a so as to surround a circumference of the external connection terminal 3 while exposing a surface of the external connection terminal 3 and a portion of a side face.
摘要翻译：要解决的问题：提供一种半导体存储卡，其通过使用引线框在实现成本降低之后提高外部连接终端的曝光特性。解决方案：根据实施例的半导体存储卡1包括：引线框架2 设置有外部连接端子3，引线部4，芯片部件安装部5和半导体芯片安装部6; 安装在芯片部件安装部5上的芯片部件7; 以及安装在半导体芯片安装部分6上的控制器芯片8和存储芯片9.引线框架2用树脂密封。密封树脂层10具有设置在第一平面10a上的凹部15，以便在暴露外部连接端子3的表面和侧面的一部分的同时围绕外部连接端子3的周围。

14. 发明专利

JP2012069556A Manufacturing method of semiconductor device 审中-公开
标题翻译：半导体器件的制造方法
公开(公告)号：JP2012069556A
公开(公告)日：2012-04-05
申请号：JP2010210571
申请日：2010-09-21
申请人： Toshiba Corp , 株式会社東芝
发明人： KAMOTO TAKU , MIURA MASAYUKI , HONMA SOICHI , TAKANO YUSUKE
IPC分类号： H01L23/12 , H01L21/56
CPC分类号： H01L24/97 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/45144 , H01L2224/48091 , H01L2224/48145 , H01L2224/48227 , H01L2224/73204 , H01L2224/73265 , H01L2224/97 , H01L2225/06562 , H01L2924/15788 , H01L2924/181 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor device which minimizes warpage of a sealing body where a semiconductor chip is covered with a mold resin.SOLUTION: The manufacturing method of a semiconductor device includes a step for forming a first release layer 24 and a second release layer 25 in this order on the surface of a support 23, a step for forming a wiring layer 12 including a wiring pattern 17 on the surface of the second release layer 25, a step for stacking a plurality of semiconductor chips 11A-11D on the surface of a the wiring layer 12, a step for coating the surface of the wiring layer 12 including the plurality of semiconductor chips 11A-11D with a mold resin 22, a step for semi-curing the mold resin 22, a step for separating a sealing body 29 comprising the wiring layer 12, the plurality of semiconductor chips 11A-11D, and the mold resin 22 from the support 23 in this state, and a step for curing the mold resin 22 completely after the step for separating the sealing body 29 and the support 23.
摘要翻译：解决的问题：提供一种半导体器件的制造方法，其使半导体芯片被模制树脂覆盖的密封体的翘曲最小化。解决方案：半导体器件的制造方法包括在支撑体23的表面上依次形成第一释放层24和第二剥离层25的步骤，用于形成包括布线的布线层12的步骤第二剥离层25的表面上的图案17，在布线层12的表面上层叠多个半导体芯片11A-11D的工序，包括多个半导体的布线层12的表面的涂布工序具有模制树脂22的芯片11A-11D，用于半固化模制树脂22的步骤，将包括布线层12，多个半导体芯片11A-11D和模制树脂22的密封体29从在该状态下的支撑体23以及在分离密封体29和支撑体23的步骤后完全固化模塑树脂22的步骤。（C）2012，JPO＆INPIT

15. 发明专利

JP2011204765A Method for manufacturing semiconductor device, and semiconductor device 审中-公开
标题翻译：制造半导体器件的方法和半导体器件
公开(公告)号：JP2011204765A
公开(公告)日：2011-10-13
申请号：JP2010068407
申请日：2010-03-24
申请人： Toshiba Corp , 株式会社東芝
发明人： HONMA SOICHI , MIURA MASAYUKI , KAMOTO TAKU , HONGO SATOSHI
IPC分类号： H01L23/12
CPC分类号： H01L21/568 , H01L21/561 , H01L23/3107 , H01L23/3121 , H01L24/45 , H01L24/48 , H01L24/73 , H01L24/97 , H01L25/03 , H01L2224/05624 , H01L2224/16225 , H01L2224/32225 , H01L2224/45015 , H01L2224/45144 , H01L2224/48227 , H01L2224/48464 , H01L2224/73204 , H01L2224/73265 , H01L2224/854 , H01L2224/97 , H01L2924/00014 , H01L2924/01029 , H01L2924/10253 , H01L2924/12044 , H01L2924/15788 , H01L2924/181 , H01L2924/19107 , H01L2924/351 , H01L2924/00 , H01L2924/00012 , H01L2924/20752 , H01L2924/207
摘要： PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device which enables suppression of separation and damage of a wiring layer in a support substrate separating step, a resin-sealed body cutting step, etc.SOLUTION: A separation layer 2 made of a thermoplastic resin and a wiring layer 3 are formed in order on a support substrate 1. An organic insulating film present in dicing regions D of the wiring layer 3 is eliminated. Semiconductor chips 9 are mounted on the wiring layer 3 in device forming regions, respectively. A sealing resin layer 12 covering the plurality of semiconductor chips 9 is formed on the separation layer 2. The separation layer 2 is heated to separate a resin-sealed body composed of the wiring layer 3, the semiconductor chips 9, and the sealing resin layer 12 from the support substrate 1. The resin-sealed body is cut based on the dicing regions D to dice a structure making up the semiconductor device.
摘要翻译：要解决的问题：提供一种制造半导体器件的方法，该半导体器件能够抑制支撑衬底分离步骤中的布线层的分离和损坏，树脂密封体切割步骤等。解决方案：分离层2由在支撑基板1上依次形成热塑性树脂和布线层3.消除了布线层3的切割区域D中存在的有机绝缘膜。半导体芯片9分别安装在器件形成区域的布线层3上。在分离层2上形成有覆盖多个半导体芯片9的密封树脂层12.将分离层2加热以分离由布线层3，半导体芯片9和密封树脂层构成的树脂密封体基于切割区域D切割树脂密封体，以切割构成半导体器件的结构。

16. 发明专利

JP2007149846A Manufacturing method for semiconductor device 审中-公开
标题翻译：半导体器件的制造方法
公开(公告)号：JP2007149846A
公开(公告)日：2007-06-14
申请号：JP2005340392
申请日：2005-11-25
申请人： Toshiba Corp , Toshiba Lsi Package Solutions Corp , 東芝Lsiパッケージソリューション株式会社 , 株式会社東芝
发明人： SUGIZAKI YOSHIAKI , NOMURA HIROSHI , KOMUDA NAOYUKI , HONMA SOICHI , TOMONO AKIRA
IPC分类号： H01L21/60
CPC分类号： H01L24/81 , H01L2224/16225 , H01L2224/81193 , H01L2924/00011 , H01L2924/01322 , H01L2224/81805
摘要： PROBLEM TO BE SOLVED: To provide a manufacturing method for a semiconductor device which reduces the possibility of the occurrence of melting connection failures, as compared to conventional cases and can improve the reliability and productivity. SOLUTION: According to the manufacturing method for the semiconductor device, a first connection terminal is connected to a second connection terminal by a heating process, where a solder bump is melted by exposing it to a temperature higher than the melting point of the solder bump; and during the heating process, the solder bump is exposed at least twice or more times, to a temperature higher than the melting point of the solder bump, and is cooled at least twice or more times to a temperature lower than the melting point of the solder bump. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：与常规情况相比，提供一种减少熔融连接故障发生的可能性的半导体器件的制造方法，并且可以提高可靠性和生产率。解决方案：根据半导体器件的制造方法，第一连接端子通过加热工艺连接到第二连接端子，其中通过将焊料凸点暴露于高于熔点焊锡凸块并且在加热过程中，焊料凸块暴露至少两次或更多次，达到高于焊料凸点的熔点的温度，并且被冷却至少两倍或更多倍于低于焊锡凸块版权所有（C）2007，JPO＆INPIT

17. 发明专利

JP2005235905A Semiconductor device and its manufacturing method 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2005235905A
公开(公告)日：2005-09-02
申请号：JP2004041174
申请日：2004-02-18
申请人： Toshiba Corp , 株式会社東芝
发明人： HONMA SOICHI
IPC分类号： H01L21/60 , H01L21/44 , H01L23/48 , H01L23/485
CPC分类号： H01L24/11 , H01L23/3192 , H01L24/13 , H01L24/16 , H01L2224/0401 , H01L2224/05022 , H01L2224/05124 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05164 , H01L2224/05166 , H01L2224/05171 , H01L2224/05181 , H01L2224/05541 , H01L2224/05572 , H01L2224/05624 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05664 , H01L2224/05666 , H01L2224/05671 , H01L2224/05681 , H01L2224/13006 , H01L2224/13099 , H01L2224/131 , H01L2224/13111 , H01L2924/0001 , H01L2924/0002 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01024 , H01L2924/01029 , H01L2924/0103 , H01L2924/01032 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01051 , H01L2924/01073 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/04953 , H01L2924/09701 , H01L2924/10253 , H01L2924/15788 , H01L2924/30105 , H01L2924/207 , H01L2924/00014 , H01L2924/01083 , H01L2924/00 , H01L2224/05552 , H01L2924/013
摘要： PROBLEM TO BE SOLVED: To improve a manufacturing yield or reliability in the connection step of a semiconductor device by obtaining such a chip structure or a connection structure that can prevent cracking or peeling, etc. caused by a low dielectric insulating film. SOLUTION: A semiconductor device 10 is provided with a semiconductor chip 11 provided with a solder bump 13 that is formed on an electrode pad with a barrier metal layer 26 between and a substrate 12 provided with an electrode pad 32 that is connected with the solder bump 13. The barrier metal layer 26 has a range of 0.1-3 μm in thickness t. Furthermore, assuming that a diameter of the barrier metal layer 26 is D 1 , an opening diameter of the electrode pad 32 on the side of the substrate is D 2 and a minimum formation pitch of the solder bump 13 is p, it is preferable that at least either of two conditions, D 1 ≥D 2 and D 1 =0.4p-0.7p is satisfied. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：通过获得能够防止由低介电绝缘膜引起的破裂或剥离等的芯片结构或连接结构，来提高半导体器件的连接步骤的制造成品率或可靠性。解决方案：半导体器件10设置有设置有焊料凸块13的半导体芯片11，焊料凸块13形成在具有阻挡金属层26的电极焊盘和衬底12之间，衬底12设置有电极焊盘32，电极焊盘32与阻焊金属层26的厚度为0.1-3μm的范围。此外，假设阻挡金属层26的直径为D 1 ，电极焊盘32在基板侧的开口直径为D 2 ，最小值焊料凸块13的形成间距为p，优选的是，两个条件中的至少一个为D 1 ≥D 2 和D 1 = 0.4p-0.7p。版权所有（C）2005，JPO＆NCIPI

18. 发明专利

JP2003017531A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2003017531A
公开(公告)日：2003-01-17
申请号：JP2001201012
申请日：2001-07-02
申请人： Toshiba Corp , 株式会社東芝
发明人： HONMA SOICHI
IPC分类号： H05K3/32 , H01L21/60 , H05K1/18 , H05K3/34
CPC分类号： H01L24/29 , H01L24/73 , H01L24/81 , H01L24/83 , H01L24/91 , H01L2224/1134 , H01L2224/1147 , H01L2224/13 , H01L2224/16 , H01L2224/16238 , H01L2224/29011 , H01L2224/2929 , H01L2224/29299 , H01L2224/294 , H01L2224/73204 , H01L2224/81191 , H01L2224/81193 , H01L2224/81385 , H01L2224/814 , H01L2224/81409 , H01L2224/83192 , H01L2224/83851 , H01L2224/9221 , H01L2924/01046 , H01L2924/01078 , H01L2924/01322 , H01L2924/01327 , H01L2924/04941 , H01L2924/09701 , H01L2924/10253 , H01L2924/00 , H01L2924/014 , H01L2924/00014 , H01L2924/00012
摘要： PROBLEM TO BE SOLVED: To improve the reliability of a connection part in a semiconductor device where a semiconductor element is connected to a wiring substrate by flip chip. SOLUTION: In the semiconductor device of the present invention, an electrode terminal of the semiconductor element and the wiring layer of the wiring substrate are connected to each other via a bump by two or more kinds of connection forms. As the connection forms via the bump, two or more kinds of connection forms that are selected from the connection by melting solders each other, the connection by melting the solder and metal getting wet thereto, the connection by mutually diffusing or pressing the same kind or different kinds of metals, and the connection by contacting conductive particles can be applied.
摘要翻译：要解决的问题：为了提高半导体器件中的连接部件的可靠性，其中半导体元件通过倒装芯片连接到布线基板。解决方案：在本发明的半导体器件中，半导体元件的电极端子和布线基板的布线层通过两种或多种连接形式通过凸块相互连接。当通过凸块形成连接时，通过熔化焊料从连接中选择的两种或多种连接形式，通过熔化焊料和金属变得湿润的连接，通过相互扩散或挤压相同类型的连接或可以应用不同种类的金属，并且可以应用通过接触导电颗粒的连接。

19. 发明专利

JP2015056458A 半導体装置审中-公开
标题翻译：半导体器件
公开(公告)号：JP2015056458A
公开(公告)日：2015-03-23
申请号：JP2013187776
申请日：2013-09-10
申请人：株式会社東芝 , Toshiba Corp
发明人： HONMA SOICHI , SHIMA SHINYA
IPC分类号： H01L23/12
CPC分类号： H01L24/96 , H01L24/97 , H01L2224/04105 , H01L2224/12105 , H01L2224/19 , H01L2924/3511 , H01L2924/00 , H01L2924/00012
摘要：【課題】クラックの発生を抑制することにより信頼性を向上させた半導体装置を提供する。【解決手段】実施形態の半導体装置は、電極パッド11を有する半導体チップ1と、半導体チップ1上に設けられ、電極パッド11の少なくとも一部を露出させる開口部30を有する絶縁樹脂層3と、接続パッド41を有し、電極パッド11に電気的に接続されるように絶縁樹脂層3上に設けられた配線層4と、絶縁樹脂層3上および配線層4上に設けられ、接続パッド41の一部を露出させる開口部52と接続パッド41の周縁を覆う被覆部51とを有する絶縁樹脂層5と、開口部30で接続パッド41に電気的に接続された外部接続端子6とを具備する。被覆部51の幅は、接続パッド41の径の2.5%以上である。【選択図】図1
摘要翻译：要解决的问题：提供通过抑制裂纹产生而提高可靠性的半导体器件。解决方案：实施例的半导体包括：具有电极焊盘11的半导体芯片1; 绝缘树脂层3设置在半导体芯片1上并具有露出电极焊盘11的至少一部分的开口30; 布线层4，其具有连接焊盘41，并且设置在绝缘树脂层3上以电连接到电极焊盘11; 绝缘树脂层5设置在绝缘树脂层3和布线层上，并且具有暴露连接焊盘41的一部分的开口52和覆盖连接焊盘41的周围的覆盖部51; 以及外部连接端子6，其在开口30处电连接到连接焊盘41.覆盖部分51的宽度为连接焊盘41的直径的2.5％以上。

20. 发明专利

JP2010010644A Method of manufacturing semiconductor device 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：JP2010010644A
公开(公告)日：2010-01-14
申请号：JP2008280132
申请日：2008-10-30
申请人： Toshiba Corp , 株式会社東芝
发明人： SATO TAKAO , HONMA SOICHI , SHIMA SHINYA
IPC分类号： H01L25/04 , H01L23/12 , H01L25/065 , H01L25/07 , H01L25/18
CPC分类号： H01L21/561 , H01L21/6835 , H01L23/3128 , H01L25/0657 , H01L25/50 , H01L2221/68359 , H01L2221/68381 , H01L2224/16225 , H01L2224/45144 , H01L2224/48091 , H01L2225/06513 , H01L2225/06572 , H01L2924/10253 , H01L2924/181 , H01L2924/19107 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： PROBLEM TO BE SOLVED: To provide a means capable of repeatedly using a support substrate when manufacturing a semiconductor device using the support substrate and capable of removing the support substrate in a short time without causing any trouble in a wiring layer and the like constituting the semiconductor device, thereby manufacturing the semiconductor device easily in a short time. SOLUTION: A semiconductor device 30 is obtained by: forming a resin layer 12 composed of a thermoplastic resin on a support substrate 11; forming an insulating layers 13 and 15 and wiring layers 14 and 16 in order; performing a step of form interlayer connectors 17 and 18 by penetrating the insulating layers and electrically conducting the wiring layers; performing the step of mount semiconductor chips 23 and 24 on the wiring layers, heating the resin layer; relatively shifting the support substrate and the insulating layers in a parallel and a perpendicular directions to shear the resin layer; and separating the support substrate and the insulating layers. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：为了提供一种能够在使用支撑基板制造半导体器件并且能够在短时间内移除支撑基板并且不会在布线层等中出现任何问题时重复使用支撑基板的装置构成半导体器件，从而在短时间内容易地制造半导体器件。解决方案：半导体器件30通过以下方式获得：在支撑基板11上形成由热塑性树脂构成的树脂层12; 依次形成绝缘层13和15以及布线层14和16; 通过穿透绝缘层并导电布线层来执行形成层间连接器17和18的步骤; 在布线层上进行安装半导体芯片23和24的步骤，加热树脂层; 将支撑基板和绝缘层沿平行和垂直方向相对移动以剪切树脂层; 并分离支撑基板和绝缘层。版权所有（C）2010，JPO＆INPIT

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