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11. 发明申请

US20070043895A1 Method and apparatus for row based power control of a microprocessor memory array 审中-公开
标题翻译：微处理器存储器阵列的基于行的功率控制的方法和装置
公开(公告)号：US20070043895A1
公开(公告)日：2007-02-22
申请号：US11204417
申请日：2005-08-16
申请人： Chad Adams , Toru Asano , Sang Dhong , Takaaki Nakazato , Joel Silberman , Osamu Takahashi
发明人： Chad Adams , Toru Asano , Sang Dhong , Takaaki Nakazato , Joel Silberman , Osamu Takahashi
IPC分类号： G06F12/06 , G06F1/00
CPC分类号： G06F1/3203 , G06F1/3237 , G06F1/3243 , G06F1/3275 , G11C8/08 , Y02D10/128 , Y02D10/14 , Y02D10/152
摘要： An apparatus, a method, and a computer program are provided to efficiently use a microprocessor array. Typically, microprocessor arrays can be divided into multiple subarrays. Also, in the conventional arrays, each of the subarrays were engaged when the microprocessor array is used. To alleviate the power consumed by the microprocessor arrays, row selection logic is employed to engage only specific rows of subarrays. Therefore, power consumed by unused subarrys is saved.
摘要翻译：提供了一种装置，方法和计算机程序以有效地使用微处理器阵列。通常，微处理器阵列可以分为多个子阵列。此外，在常规阵列中，当使用微处理器阵列时，每个子阵列被接合。为了减轻微处理器阵列消耗的功率，采用行选择逻辑仅与特定的子阵列相啮合。因此，省去了未使用的亚军消耗的电力。

12. 发明授权

US07046045B2 SOI sense amplifier with cross-coupled bit line structure 有权
标题翻译：具有交叉耦合位线结构的SOI读出放大器
公开(公告)号：US07046045B2
公开(公告)日：2006-05-16
申请号：US10852889
申请日：2004-05-25
申请人： Takaaki Nakazato , Toru Asano , Osamu Takahashi , Sang Dhong
发明人： Takaaki Nakazato , Toru Asano , Osamu Takahashi , Sang Dhong
IPC分类号： G01R19/00 , G11C7/00 , H03F3/45
CPC分类号： H03F3/45188
摘要： Systems and methods for decreasing the sensitivity of a sense amplifier to variations in the threshold voltages of the data line pull-down transistors by pre-charging the intermediate nodes of the sense amplifier to the voltages on the opposing bit lines when the sense amplifier is not enabled. In one embodiment, the intermediate nodes are coupled to the input bit lines through transistors that are switched on when the sense amplifier is not enabled and switched off when the sense amplifier is enabled. In one embodiment, the intermediate nodes are pre-charged to a predetermined voltage before being pre-charged to the voltages on the bit lines. In one embodiment, the bodies of the data line pull-down transistors may also be body-tied to the opposing intermediate nodes to increase current flow through these transistors, particularly on the side of the sense amplifier that will be pulled low when the sense amplifier is enabled.
摘要翻译：当读出放大器不是时，将读出放大器的中间节点预充电到相对位线上的电压，从而降低读出放大器对数据线下拉晶体管阈值电压变化的灵敏度的系统和方法启用在一个实施例中，中间节点通过晶体管耦合到输入位线，晶体管在读出放大器未使能时被接通，当读出放大器被使能时，它们被关断。在一个实施例中，中间节点在被预充电到位线上的电压之前被预充电到预定电压。在一个实施例中，数据线下拉晶体管的主体也可以被机构连接到相对的中间节点，以增加通过这些晶体管的电流，特别是在读出放大器的一侧，当读出放大器启用。

13. 发明申请

US20060098520A1 Apparatus and method of word line decoding for deep pipelined memory 失效
标题翻译：深层流水线存储器的字线解码装置及方法
公开(公告)号：US20060098520A1
公开(公告)日：2006-05-11
申请号：US10982109
申请日：2004-11-05
申请人： Toru Asano , Sang Dhong , Takaaki Nakazato , Osamu Takahashi
发明人： Toru Asano , Sang Dhong , Takaaki Nakazato , Osamu Takahashi
IPC分类号： G11C8/00 , G11C7/10
CPC分类号： G11C7/1039 , G11C8/08 , G11C8/10
摘要： A method, an apparatus, and a computer program are provided to reduce the number of required latches in a deep pipeline wordline (WL) decoder. Traditionally, a signal local clock buffer (LCB) has been responsible for providing a driving signal to a WL driver. However, with this configuration, a large number of latches are utilized. To reduce this latch usage, a number of LCBs are employed, such that one latch can enable an increased number of WLs. Hence, the overall area occupied by latches is reduced and power consumption is reduced.
摘要翻译：提供了一种方法，装置和计算机程序以减少深流水线字线（WL）解码器中所需的锁存器的数量。传统上，信号本地时钟缓冲器（LCB）已经负责向WL驱动器提供驱动信号。然而，利用该配置，使用大量的锁存器。为了减少该锁存器的使用，采用多个LCB，使得一个锁存器能够增加数量的WL。因此，锁存器占用的总体面积减少，功耗降低。

14. 发明申请

US20050264323A1 SOI sense amplifier with cross-coupled bit line structure 有权
标题翻译：具有交叉耦合位线结构的SOI读出放大器
公开(公告)号：US20050264323A1
公开(公告)日：2005-12-01
申请号：US10852889
申请日：2004-05-25
申请人： Takaaki Nakazato , Toru Asano , Osamu Takahashi , Sang Dhong
发明人： Takaaki Nakazato , Toru Asano , Osamu Takahashi , Sang Dhong
IPC分类号： G11C11/419 , H03F3/45
CPC分类号： H03F3/45188
摘要： Systems and methods for decreasing the sensitivity of a sense amplifier to variations in the threshold voltages of the data line pull-down transistors by pre-charging the intermediate nodes of the sense amplifier to the voltages on the opposing bit lines when the sense amplifier is not enabled. In one embodiment, the intermediate nodes are coupled to the input bit lines through transistors that are switched on when the sense amplifier is not enabled and switched off when the sense amplifier is enabled. In one embodiment, the intermediate nodes are pre-charged to a predetermined voltage before being pre-charged to the voltages on the bit lines. In one embodiment, the bodies of the data line pull-down transistors may also be body-tied to the opposing intermediate nodes to increase current flow through these transistors, particularly on the side of the sense amplifier that will be pulled low when the sense amplifier is enabled.
摘要翻译：当读出放大器不是时，将读出放大器的中间节点预充电到相对位线上的电压，从而降低读出放大器对数据线下拉晶体管阈值电压变化的灵敏度的系统和方法启用在一个实施例中，中间节点通过晶体管耦合到输入位线，晶体管在读出放大器未使能时被接通，当读出放大器被使能时，它们被关断。在一个实施例中，中间节点在被预充电到位线上的电压之前被预充电到预定电压。在一个实施例中，数据线下拉晶体管的主体也可以被机构连接到相对的中间节点，以增加通过这些晶体管的电流，特别是在读出放大器的一侧，当读出放大器启用。

15. 发明授权

US06833736B2 Pulse generating circuit 有权
公开(公告)号：US06833736B2
公开(公告)日：2004-12-21
申请号：US10359805
申请日：2003-02-07
申请人： Takaaki Nakazato , Toru Asano , Osamu Takahashi , Sang Dhong , Atsushi Kawasumi
发明人： Takaaki Nakazato , Toru Asano , Osamu Takahashi , Sang Dhong , Atsushi Kawasumi
IPC分类号： H03K908
CPC分类号： H03K5/1565 , H03K5/05 , H03K5/06
摘要： A pulse generator circuit includes a first logic means, a second logic means, a first delay means, and a second delay means. The first logic means is for receiving an input clock signal. The first delay means is for delaying the input clock signal by a first delay time. The second logic means is for receiving a signal output from the first logic means. The second delay means is for delaying the signal output from the first logic means by a second delay time.

16. 发明授权

US08040488B2 Substrate processing apparatus 有权
标题翻译：基板加工装置
公开(公告)号：US08040488B2
公开(公告)日：2011-10-18
申请号：US11294727
申请日：2005-12-06
申请人： Shuichi Yasuda , Masashi Kanaoka , Koji Kaneyama , Tadashi Miyagi , Kazuhito Shigemori , Toru Asano , Yukio Toriyama , Takashi Taguchi , Tsuyoshi Mitsuhashi , Tsuyoshi Okumura
发明人： Shuichi Yasuda , Masashi Kanaoka , Koji Kaneyama , Tadashi Miyagi , Kazuhito Shigemori , Toru Asano , Yukio Toriyama , Takashi Taguchi , Tsuyoshi Mitsuhashi , Tsuyoshi Okumura
IPC分类号： G03B27/32 , G03B27/52 , G03D5/00
CPC分类号： G03F7/70991 , H01L21/67051 , H01L21/67173 , H01L21/67178
摘要： A substrate processing apparatus comprises an indexer block, an anti-reflection film processing block, a resist film processing block, a development processing block, a processing block for liquid immersion exposure processing, and an interface block. An exposure device is arranged adjacent to the interface block. The processing block for liquid immersion exposure processing comprises a coating processing group for resist cover film and a removal processing group for resist cover film. The resist cover film is formed in the processing block for liquid immersion exposure processing before the exposure processing. The resist cover film is removed in the processing block for liquid immersion exposure processing after the exposure processing.
摘要翻译：基板处理装置包括分度器块，抗反射膜处理块，抗蚀剂膜处理块，显影处理块，用于液浸曝光处理的处理块和界面块。曝光装置设置在接口块附近。用于液浸曝光处理的处理块包括用于抗蚀剂覆盖膜的涂覆处理组和抗蚀剂覆盖膜的去除处理组。在曝光处理之前，在用于液浸曝光处理的处理块中形成抗蚀剂覆盖膜。在曝光处理之后，在用于液浸曝光处理的处理块中去除抗蚀剂覆盖膜。

17. 发明申请

US20100129526A1 SUBSTRATE PROCESSING APPARATUS 审中-公开
标题翻译：基板加工设备
公开(公告)号：US20100129526A1
公开(公告)日：2010-05-27
申请号：US12698876
申请日：2010-02-02
申请人： Shuichi Yasuda , Masashi Kanaoka , Koji Kaneyama , Tadashi Miyagi , Kazuhito Shigemori , Toru Asano , Yukio Toriyama , Takashi Taguchi , Tsuyoshi Mitsuhashi , Tsuyoshi Okumura
发明人： Shuichi Yasuda , Masashi Kanaoka , Koji Kaneyama , Tadashi Miyagi , Kazuhito Shigemori , Toru Asano , Yukio Toriyama , Takashi Taguchi , Tsuyoshi Mitsuhashi , Tsuyoshi Okumura
IPC分类号： B05D5/12
CPC分类号： H01L21/67034 , G03F7/38 , H01L21/67028 , H01L21/67051 , H01L21/67178 , H01L21/67207
摘要： A method of processing a substrate in a substrate processing apparatus that is arranged adjacent to an exposure device and includes first, second and third processing units, includes the steps of forming a film made of a photosensitive material on the substrate by said first processing unit before exposure processing by said exposure device. The method also includes applying drying processing to the substrate by said second processing unit after the exposure processing by said exposure device and applying development processing to the substrate by said third processing unit after the drying processing by said second processing unit
摘要翻译：一种在与曝光装置相邻并且包括第一，第二和第三处理单元的基板处理装置中处理基板的方法，包括以下步骤：在所述基板上由所述第一处理单元形成由感光材料制成的膜，曝光装置的曝光处理。该方法还包括在所述曝光装置的曝光处理之后通过所述第二处理单元对所述基板进行干燥处理，并且在所述第二处理单元进行干燥处理之后，通过所述第三处理单元对所述基板施加显影处理

18. 发明申请

US20060147202A1 Substrate processing apparatus and substrate processing method 审中-公开
标题翻译：基板加工装置及基板处理方法
公开(公告)号：US20060147202A1
公开(公告)日：2006-07-06
申请号：US11295240
申请日：2005-12-06
申请人： Shuichi Yasuda , Masashi Kanaoka , Koji Kaneyama , Tadashi Miyagi , Kazuhito Shigemori , Toru Asano , Yukio Toriyama , Takashi Taguchi , Tsuyoshi Mitsuhashi , Tsuyoshi Okumura
发明人： Shuichi Yasuda , Masashi Kanaoka , Koji Kaneyama , Tadashi Miyagi , Kazuhito Shigemori , Toru Asano , Yukio Toriyama , Takashi Taguchi , Tsuyoshi Mitsuhashi , Tsuyoshi Okumura
IPC分类号： G03D5/00
CPC分类号： G03F7/70991 , G03F7/70341
摘要： A substrate processing apparatus comprises an indexer block, an anti-reflection film processing block, a resist film processing block, a washing/development processing block, and an interface block. An exposure device is arranged adjacent to the interface block. A resist film is formed on a substrate by the resist film processing block. The substrate is washed and dried by the washing processing unit in the washing/development processing block before the substrate is subjected to the exposure processing by the exposure device.
摘要翻译：基板处理装置包括分度器块，防反射膜处理块，抗蚀剂膜处理块，洗涤/显影处理块和界面块。曝光装置设置在接口块附近。通过抗蚀剂膜处理块在基板上形成抗蚀剂膜。在通过曝光装置对基板进行曝光处理之前，通过洗涤处理单元在洗涤/显影处理块中洗涤和干燥基板。

19. 发明申请

US20060104635A1 Substrate processing apparatus and substrate processing method 有权
标题翻译：基板加工装置及基板处理方法
公开(公告)号：US20060104635A1
公开(公告)日：2006-05-18
申请号：US11273439
申请日：2005-11-10
申请人： Koji Kaneyama , Akihiro Hisai , Toru Asano , Hiroshi Kobayashi
发明人： Koji Kaneyama , Akihiro Hisai , Toru Asano , Hiroshi Kobayashi
IPC分类号： G03D5/00
CPC分类号： G03F7/70991 , Y10S414/135
摘要： A substrate processing apparatus comprises an indexer block, an anti-reflection film processing block, a resist film processing block, a development processing block, a resist cover film processing block, a resist cover film removal block, and an interface block. An exposure device is arranged adjacent to the interface block. A resist film is formed on a substrate in the resist film processing block. A resist cover film is formed on the resist film in the resist cover film processing block before the substrate is subjected to exposure processing by the exposure device.
摘要翻译：基板处理装置包括分度器块，抗反射膜处理块，抗蚀剂膜处理块，显影处理块，抗蚀剂覆盖膜处理块，抗蚀剂覆盖膜去除块和界面块。曝光装置设置在接口块附近。在抗蚀剂膜处理块中的基板上形成抗蚀剂膜。在通过曝光装置对基板进行曝光处理之前，在抗蚀剂覆盖膜处理块的抗蚀剂膜上形成抗蚀剂覆盖膜。

20. 发明申请

US20050254585A1 Self clock generation structure for low power local clock buffering decoder 有权
标题翻译：用于低功耗本地时钟缓冲解码器的自身时钟生成结构
公开(公告)号：US20050254585A1
公开(公告)日：2005-11-17
申请号：US10845540
申请日：2004-05-13
申请人： Chad Adams , Toru Asano , Andrew Maust
发明人： Chad Adams , Toru Asano , Andrew Maust
IPC分类号： G06F1/06 , G06F1/32 , H04B14/04 , H04L27/06
CPC分类号： G06F1/32 , G06F1/06
摘要： A k-to-2k decoder is provided. Within the final stage of a k-to-2k decoder is a plurality of word line drivers. These word line drivers utilize clocking signals to fire word lines to a memory array. However, power consumption by clocks has become a serious issue with the increase component density on silicon wafers. To alleviate the problem, signals from the first stage of the k-to-2k decoder provide enablement signals to Local Clock Buffers (LCBs) that allow the word line drivers to fire. The enablement signal reduces the number of active buffers and signals carried to word line drivers, reducing power consumption.
摘要翻译：提供k-2-k解码器。在k-2-k解码器的最后阶段是多个字线驱动器。这些字线驱动器利用时钟信号将字线触发到存储器阵列。然而，随着硅晶片的组件密度的增加，时钟功耗成为一个严重的问题。为了缓解该问题，来自k-2-k解码器的第一级的信号向本地时钟缓冲器（LCB）提供允许字线驱动器触发的启动信号。启用信号减少了向字线驱动器传送的有效缓冲器和信号的数量，从而降低了功耗。

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