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11. 发明授权

US06359472B2 Semiconductor integrated circuit and its fabrication method 有权
标题翻译：半导体集成电路及其制造方法
公开(公告)号：US06359472B2
公开(公告)日：2002-03-19
申请号：US09791831
申请日：2001-02-26
申请人： Michiaki Nakayama , Masato Hamamoto , Kazutaka Mori , Satoru Isomura
发明人： Michiaki Nakayama , Masato Hamamoto , Kazutaka Mori , Satoru Isomura
IPC分类号： H01L2704
CPC分类号： H01L27/1104 , H01L27/0921 , H01L27/0928
摘要： An integrated circuit having a CMOS circuit constituted by electrically connecting an n-type well 2, in which p-channel transistor Tp of the CMOS circuit is set, with a supply line Vdd through switching transistor Tps, and electrically connecting a p-type well 3, in which n-channel transistor Tn of the CMOS circuit is set, with supply line Vss through switching transistor Tns. Thermal runaway due to leakage current can be controlled by turning off switching transistors Tps and Tns and supplying potentials suitable for a test to the n-type well 2 and the p-type well 3 from an external unit when the integrated circuit is being tested. Fluctuations of the latch-up phenomenon and operation speed can be prevented by turning on switching transistors Tps and Tns and setting the n-type well 2 and the p-type well 3 to the voltages Vdd and Vss, respectively.
摘要翻译：具有CMOS电路的集成电路，其通过将n型阱2（其中CMOS电路的p沟道晶体管Tp被置位）与通过开关晶体管Tps的电源线Vdd电连接而构成，并且电连接p型阱如图3所示，其中CMOS电路的n沟道晶体管Tn被设置，电源线Vss通过开关晶体管Tns。当集成电路被测试时，可以通过关断开关晶体管Tps和Tns并从外部单元向n型阱2和p型阱3提供适合于测试的电位来控制由于泄漏电流引起的热失控。通过接通开关晶体管Tps和Tns并分别将n型阱2和p型阱3分别设置为电压Vdd和Vss可以防止闩锁现象和操作速度的波动。

12. 发明授权

US06194915B1 Semiconductor integrated circuit device and process for manufacturing the same 失效
标题翻译：半导体集成电路器件及其制造方法
公开(公告)号：US06194915B1
公开(公告)日：2001-02-27
申请号：US09077829
申请日：1998-06-04
申请人： Michiaki Nakayama , Masato Hamamoto , Kazutaka Mori , Satoru Isomura
发明人： Michiaki Nakayama , Masato Hamamoto , Kazutaka Mori , Satoru Isomura
IPC分类号： H01L2704
CPC分类号： H01L27/1104 , H01L27/0921 , H01L27/0928
摘要： To provide a semiconductor integrated circuit having a CMOS circuit constituted by electrically connecting an n-type well 2, in which one transistor Tp for constituting the CMOS circuit is set, with a first power-supply-voltage line Vdd through a switching transistor Tps, and electrically connecting a p-type well 3 in which the other transistor Tn for constituting the CMOS circuit is set with a second power-supply-voltage line Vss through a switching transistor Tns. Moreover, the semiconductor integrated circuit is constituted so that thermal runaway due to leakage current can be controlled by turning off the switching transistors Tps and Tns and supplying a potential suitable for a test to the n-type well 2 and the p-type well 3 from an external unit when the semiconductor integrated circuit is being tested. Furthermore, the semiconductor integrated circuit is constituted so that fluctuations of the latch-up phenomenon and operation speed can be prevented by turning on the switching transistors Tps and Tns and setting the n-type well 2 and the p-type well 3 to the power supply voltages Vdd and Vss, respectively.
摘要翻译：为了提供具有CMOS电路的半导体集成电路，该CMOS电路通过电连接构成CMOS电路的一个晶体管Tp与通过开关晶体管Tps的第一电源电压线Vdd电连接的n型阱2，并且通过开关晶体管Tns将构成CMOS电路的另一个晶体管Tn与p型阱3电连接到第二电源电压线Vss。此外，半导体集成电路被构造成使得可以通过关断开关晶体管Tps和Tns并且向n型阱2和p型阱3提供适合于测试的电位来控制由漏电流引起的热失控当半导体集成电路被测试时，从外部单元。此外，半导体集成电路构成为通过接通开关晶体管Tps和Tns并将n型阱2和p型阱3设置为功率来防止闩锁现象和操作速度的波动电源电压Vdd和Vss。

13. 发明授权

US5043297A Wiring method of on-chip modification for an LSI 失效
标题翻译： LSI的片上修改接线方法
公开(公告)号：US5043297A
公开(公告)日：1991-08-27
申请号：US571179
申请日：1990-08-22
申请人： Katsuyoshi Suzuki , Masato Hamamoto , Takahiko Takahashi
发明人： Katsuyoshi Suzuki , Masato Hamamoto , Takahiko Takahashi
IPC分类号： H01L21/3205 , H01L21/768 , H01L21/82 , H01L23/52 , H01L23/525
CPC分类号： H01L21/76894 , H01L21/76888 , H01L23/5258 , H01L2924/0002 , Y10S438/94
摘要： A wiring method for on-chip modification of an LSI is provided to cut a portion of a wire inside of the LSI with an ion beam and connect the wire with a laser induced CVD process so that the logic is changed when developing the LSI. The method comprises the steps of cutting or connecting an LSI wire even if another wire is located above or adjacent to the LSI wire and repairing an excessively cut or connected portion. The method thus makes it possible to widen the range of a possible cutting or connection spot, thereby making any kind of repairs possible, some of which would have never been repaired by the conventional method.
摘要翻译：提供了用于片上修改LSI的布线方法，用离子束切割LSI内的线的一部分，并且用激光感应CVD工艺连接线，使得在开发LSI时逻辑被改变。该方法包括如下步骤：即使另一个线位于LSI线上方或邻近LSI线并修复过度切割或连接部分，也可以切断或连接LSI线。因此，该方法可以扩大可能的切割或连接点的范围，从而进行任何种类的修理成为可能，其中一些将永远不会被常规方法修复。

14. 发明授权

US06937068B2 Semiconductor integrated circuit 失效
标题翻译：半导体集成电路
公开(公告)号：US06937068B2
公开(公告)日：2005-08-30
申请号：US10642138
申请日：2003-08-18
申请人： Michiaki Nakayama , Masato Hamamoto , Kazutaka Mori , Satoru Isomura
发明人： Michiaki Nakayama , Masato Hamamoto , Kazutaka Mori , Satoru Isomura
IPC分类号： H01L27/092 , H01L27/11 , H01L27/04
CPC分类号： H01L27/1104 , H01L27/0921 , H01L27/0928
摘要： An integrated circuit having a CMOS circuit constituted by electrically connecting an n-type well 2, in which p-channel transistor Tp of the CMOS circuit is set, with a supply line Vdd through switching transistor Tps, and electrically connecting a p-type well 3, in which n-channel transistor Tn of the CMOS circuit is set, with supply line Vss through switching transistor Tns. Thermal runaway due to leakage current can be controlled by turning off switching transistors Tps and Tns and supplying potentials suitable for a test to the n-type well 2 and the p-type well 3 from an external unit when the integrated circuit is being tested. Fluctuations of the latch-up phenomenon and operation speed can be prevented by turning on switching transistors Tps and Tns and setting the n-type well 2 and the p-type well 3 to the voltages Vdd and Vss, respectively.
摘要翻译：具有CMOS电路的集成电路，其通过将n型阱2（其中CMOS电路的p沟道晶体管Tp被置位）与通过开关晶体管Tps的电源线Vdd电连接而构成，并且电连接p型阱如图3所示，其中CMOS电路的n沟道晶体管Tn被设置，电源线Vss通过开关晶体管Tns。当集成电路被测试时，可以通过关断开关晶体管Tps和Tns并从外部单元向n型阱2和p型阱3提供适合于测试的电位来控制由于泄漏电流引起的热失控。通过接通开关晶体管Tps和Tns并分别将n型阱2和p型阱3分别设置为电压Vdd和Vss可以防止闩锁现象和操作速度的波动。

15. 发明授权

US06636075B2 Semiconductor integrated circuit and its fabrication method 失效
公开(公告)号：US06636075B2
公开(公告)日：2003-10-21
申请号：US10060390
申请日：2002-02-01
申请人： Michiaki Nakayama , Masato Hamamoto , Kazutaka Mori , Satoru Isomura
发明人： Michiaki Nakayama , Masato Hamamoto , Kazutaka Mori , Satoru Isomura
IPC分类号： H01P308
CPC分类号： H01L27/1104 , H01L27/0921 , H01L27/0928
摘要： An integrated circuit having a CMOS circuit constituted by electrically connecting an n-type well 2, in which p-channel transistor Tp of the CMOS circuit is set, with a supply line Vdd through switching transistor Tps, and electrically connecting a p-type well 3, in which n-channel transistor Tn of the CMOS circuit is set, with supply line Vss through switching transistor Tns. Thermal runaway due to leakage current can be controlled by turning off switching transistors Tps and Tns and supplying potentials suitable for a test to the n-type well 2 and the p-type well 3 from an external unit when the integrated circuit is being tested. Fluctuations of the latch-up phenomenon and operation speed can be prevented by turning on switching transistors Tps and Tns and setting the n-type well 2 and the p-type well 3 to the voltages Vdd and Vss, respectively.

16. 发明授权

US07576406B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07576406B2
公开(公告)日：2009-08-18
申请号：US10773658
申请日：2004-02-09
申请人： Yoichi Tamaki , Hideaki Nonami , Masato Hamamoto
发明人： Yoichi Tamaki , Hideaki Nonami , Masato Hamamoto
IPC分类号： H01L29/00
CPC分类号： H01L27/0823
摘要： A plurality of the same kind of npn-type bipolar transistors are disposed regularly on a semiconductor layer that is provided over an insulation layer. The plurality of unit bipolar transistors are connected in parallel, thereby to form a plurality of desired bipolar transistors. A deep trench isolation surrounds a group of or the whole of the plurality of unit bipolar transistors that are connected in parallel, for a plurality of desired bipolar transistor that require thermal stability.
摘要翻译：多个相同种类的npn型双极晶体管规则地设置在设置在绝缘层上的半导体层上。多个单位双极晶体管并联连接，从而形成多个希望的双极晶体管。对于需要热稳定性的多个所需双极晶体管，深沟槽隔离围绕并联连接的多个单元双极晶体管的一组或全部。

17. 发明授权

US06922803B2 Test method of semiconductor intergrated circuit and test pattern generator 失效
标题翻译：半导体集成电路和测试模式发生器的测试方法
公开(公告)号：US06922803B2
公开(公告)日：2005-07-26
申请号：US09811435
申请日：2001-03-20
申请人： Michinobu Nakao , Kazumi Hatayama , Koichiro Natsume , Yoshikazu Kiyoshige , Masaki Kouno , Masato Hamamoto , Hidefumi Yoshida , Tomoji Nakamura
发明人： Michinobu Nakao , Kazumi Hatayama , Koichiro Natsume , Yoshikazu Kiyoshige , Masaki Kouno , Masato Hamamoto , Hidefumi Yoshida , Tomoji Nakamura
IPC分类号： G01R31/28 , G01R31/3183 , G06F11/22 , G11C29/10 , G06F11/00
CPC分类号： G01R31/3183 , G11C29/10
摘要： A semiconductor integrated circuit test method which reduces the required data volume for testing and efficiently detects faults in a circuit to be tested, the method comprising means 110 to generate identical pattern sequences repeatedly and means 120 to control flipped bits in pattern sequences, in order to generate neighborhood pattern sequences and use the neighborhood patterns to test the circuit under test 130. The neighborhood patterns include, in whole or in part, such pattern sequences as ones without flipped bits, ones with all or some flipped bits in one pattern and ones with all or some flipped bits in consecutive patterns or patterns at regular intervals, the interval being equivalent to a given number of patterns. Because a test pattern generator is provided independently of the circuit to be tested, the problem of a prolonged design period can be eliminated, a loss in the operating speed of the circuit under test is minimized and a high fault coverage can be achieved with less hardware overhead and a smaller volume of test data.
摘要翻译：一种半导体集成电路测试方法，其减少测试所需的数据量并有效地检测要测试的电路中的故障，该方法包括重复生成相同模式序列的装置110，以及以模式序列控制翻转位的装置120，以便生成邻域模式序列并使用邻域模式来测试被测电路130。相邻图案全部或部分地包括没有翻转位的图案序列，一个具有一个图案中的全部或一些翻转位的图案序列，以及以规则间隔连续的图案或图案中的全部或一些翻转的位，相当于给定数量的图案。由于测试模式发生器独立于要测试的电路提供，可以消除延长设计周期的问题，使被测电路的工作速度损失最小化，并且可以通过较少的硬件实现高故障覆盖开销和较小量的测试数据。

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