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11. 发明授权

US08570197B2 Serializer circuitry for high-speed serial data transmitters on programmable logic device integrated circuits 有权
标题翻译：用于可编程逻辑器件集成电路上的高速串行数据发射器的串行器电路
公开(公告)号：US08570197B2
公开(公告)日：2013-10-29
申请号：US12953766
申请日：2010-11-24
申请人： Toan Thanh Nguyen , Thungoc Tran , Sergey Yuryevich Shumarayev , Arch Zaliznyak , Shoujun Wang , Ramanand Venkata , Chong Lee
发明人： Toan Thanh Nguyen , Thungoc Tran , Sergey Yuryevich Shumarayev , Arch Zaliznyak , Shoujun Wang , Ramanand Venkata , Chong Lee
IPC分类号： H03M9/00
CPC分类号： H03K19/00 , H03K19/17744 , H03M9/00 , H04L1/243 , H04L7/0008 , H04L7/033 , H04L25/0266
摘要： Serializer circuitry for high-speed serial data transmitter circuitry on a programmable logic device (“PLD”) or the like includes circuitry for converting parallel data having any of several data widths to serial data. The circuitry can also operate at any frequency in a wide range of frequencies, and can make use of reference clock signals having any of several relationships to the parallel data rate and/or the serial data rate. The circuitry is configurable/re-configurable in various respects, at least some of which configuration/re-configuration can be dynamically controlled (i.e., during user-mode operation of the PLD).
摘要翻译：用于可编程逻辑器件（“PLD”）等上的高速串行数据发射器电路的串行器电路包括用于将具有若干数据宽度中的任一个的并行数据转换为串行数据的电路。电路还可以在宽频率范围内的任何频率下操作，并且可以利用具有与并行数据速率和/或串行数据速率的几个关系中的任何一个的参考时钟信号。该电路在各个方面是可配置的/可重新配置的，其中至少一些配置/重新配置可被动态地控制（即在PLD的用户模式操作期间）。

12. 发明授权

US07656187B2 Multi-channel communication circuitry for programmable logic device integrated circuits and the like 有权
标题翻译：用于可编程逻辑器件集成电路等的多通道通信电路
公开(公告)号：US07656187B2
公开(公告)日：2010-02-02
申请号：US11288810
申请日：2005-11-28
申请人： Thungoc Tran , Sergey Yuryevich Shumarayev , Tim Tri Hoang , Ning Xue , Chong Lee , Ramanand Venkata
发明人： Thungoc Tran , Sergey Yuryevich Shumarayev , Tim Tri Hoang , Ning Xue , Chong Lee , Ramanand Venkata
IPC分类号： H03K19/173
CPC分类号： H03K19/17736 , H03K19/17744
摘要： An integrated circuit like a programmable logic device (“PLD”) includes multiple channels of data communication circuitry. Circuitry is provided for selectively sharing signals (e.g., control-type signals) among these channels in groupings of various size so that the device can better support communication protocols that require various numbers of channels (e.g., one channel operating relatively independently, four channels working together, eight channels working together, etc.). The signals shared may include a clock signal, a FIFO write enable signal, a FIFO read enable signal, or the like. The circuit arrangements are preferably modular (i.e., the same or substantially the same from one channel to the next and/or from one group of channels to the next) to facilitate such things as circuit design and verification.
摘要翻译：诸如可编程逻辑器件（“PLD”）的集成电路包括多个通道的数据通信电路。提供电路用于在各种尺寸的分组中选择性地共享这些信道中的信号（例如，控制型信号），使得设备可以更好地支持需要各种信道数量的通信协议（例如，一个信道相对独立地操作，四个信道工作一起，八个渠道在一起等）。共享的信号可以包括时钟信号，FIFO写使能信号，FIFO读使能信号等。电路布置优选地是模块化的（即，从一个通道到下一个通道和/或从一组通道到下一个通道相同或基本相同），以便于诸如电路设计和验证之类的事情。

13. 发明申请

US20110068845A1 SERIALIZER CIRCUITRY FOR HIGH-SPEED SERIAL DATA TRANSMITTERS ON PROGRAMMABLE LOGIC DEVICE INTEGRATED CIRCUITS 有权
标题翻译：用于可编程逻辑器件集成电路的高速串行数据传输器的串行电路
公开(公告)号：US20110068845A1
公开(公告)日：2011-03-24
申请号：US12953766
申请日：2010-11-24
申请人： Toan Thanh Nguyen , Thungoc Tran , Sergey Yuryevich Shumarayev , Arch ZaIiznyak , Shoujun Wang , Ramanand Venkata , Chong Lee
发明人： Toan Thanh Nguyen , Thungoc Tran , Sergey Yuryevich Shumarayev , Arch ZaIiznyak , Shoujun Wang , Ramanand Venkata , Chong Lee
IPC分类号： G06F1/04 , H03K3/01
CPC分类号： H03K19/00 , H03K19/17744 , H03M9/00 , H04L1/243 , H04L7/0008 , H04L7/033 , H04L25/0266
摘要： Serializer circuitry for high-speed serial data transmitter circuitry on a programmable logic device (“PLD”) or the like includes circuitry for converting parallel data having any of several data widths to serial data. The circuitry can also operate at any frequency in a wide range of frequencies, and can make use of reference clock signals having any of several relationships to the parallel data rate and/or the serial data rate. The circuitry is configurable/re-configurable in various respects, at least some of which configuration/re-configuration can be dynamically controlled (i.e., during user-mode operation of the PLD).
摘要翻译：用于可编程逻辑器件（“PLD”）等上的高速串行数据发射器电路的串行器电路包括用于将具有若干数据宽度中的任一个的并行数据转换为串行数据的电路。电路还可以在宽频率范围内的任何频率下操作，并且可以利用具有与并行数据速率和/或串行数据速率的几个关系中的任何一个的参考时钟信号。该电路在各个方面是可配置的/可重新配置的，其中至少一些配置/重新配置可被动态地控制（即在PLD的用户模式操作期间）。

14. 发明授权

US07304507B1 Modular buffering circuitry for multi-channel transceiver clock and other signals 有权
标题翻译：用于多通道收发器时钟和其他信号的模块化缓冲电路
公开(公告)号：US07304507B1
公开(公告)日：2007-12-04
申请号：US11288496
申请日：2005-11-28
申请人： Thungoc Tran , Sergey Yuryevich Shumarayev , Tim Tri Hoang
发明人： Thungoc Tran , Sergey Yuryevich Shumarayev , Tim Tri Hoang
IPC分类号： H03K19/00
CPC分类号： H03K19/17736 , H03K19/17744
摘要： Circuitry for distributing signals such as reference clock signals among blocks of transceiver circuitry on an integrated circuit such as a field programmable gate array (“FPGA”) employs bidirectional buffers rather than unidirectional buffers. This allows all buffers to have the same construction regardless of physical location, which facilitates construction of the circuitry using identical or substantially identical modules. The same approach may be used for distributing other types of signals among the transceiver blocks. For example, this approach may be used for distributing calibration control signals.
摘要翻译：在集成电路（例如现场可编程门阵列（“FPGA”）上的收发器电路块之间分配诸如参考时钟信号的信号的电路采用双向缓冲器而不是单向缓冲器。这允许所有缓冲器具有相同的结构，而不管物理位置如何，这有助于使用相同或基本相同的模块构建电路。相同的方法可以用于在收发器块之间分配其他类型的信号。例如，该方法可用于分配校准控制信号。

15. 发明授权

US07539278B2 Programmable transceivers that are able to operate over wide frequency ranges 有权
标题翻译：能够在宽频率范围内工作的可编程收发器
公开(公告)号：US07539278B2
公开(公告)日：2009-05-26
申请号：US11292565
申请日：2005-12-02
申请人： Sergey Yuryevich Shumarayev , Rakesh Patel
发明人： Sergey Yuryevich Shumarayev , Rakesh Patel
IPC分类号： H03D3/24
CPC分类号： H03K19/17744 , H03L7/0995
摘要： A field-programmable gate array (“FPGA”) may include data receiver and/or transmitter circuitry that is adapted to receive and/or transmit data at any frequency(ies) or data rate(s) in a wide range of possible frequencies or data rates. Phase-locked loop (PLL) circuitry may be needed for operation of such receiver and/or transmitter circuitry. For satisfactory operation over the wide frequency range, multiple PLL circuits are provided. One of these PLL circuits may be capable of operating over the entire frequency range, possibly with better jitter performance in some portions of the range than in other portions of the range. One or more other PLL circuits may be provided that are focused on particular parts of the broad range, especially where the jitter performance of the first-mentioned PLL may not be adequate to meet some possible needs.
摘要翻译：现场可编程门阵列（“FPGA”）可以包括数据接收器和/或发射机电路，其适于在宽范围的可能频率中以任何频率或数据速率接收和/或发射数据，或数据速率。可能需要锁相环（PLL）电路来操作这种接收器和/或发射器电路。为了在宽频率范围内的令人满意的操作，提供了多个PLL电路。这些PLL电路中的一个可能能够在整个频率范围内运行，可能在该范围的某些部分中具有比该范围的其他部分更好的抖动性能。可以提供一个或多个其他PLL电路，其集中在宽范围的特定部分上，特别是在首先提到的PLL的抖动性能可能不足以满足一些可能需要的地方。

16. 发明授权

US07782935B1 Half-rate DFE with duplicate path for high data-rate operation 有权
标题翻译：具有高数据速率操作的重复路径的半速率DFE
公开(公告)号：US07782935B1
公开(公告)日：2010-08-24
申请号：US11514490
申请日：2006-08-31
申请人： Wilson Wong , Sergey Yuryevich Shumarayev , Simardeep Maangat , Thungoc M. Tran , Tim Tri Hoang , Tin H. Lai
发明人： Wilson Wong , Sergey Yuryevich Shumarayev , Simardeep Maangat , Thungoc M. Tran , Tim Tri Hoang , Tin H. Lai
IPC分类号： H03H7/30
CPC分类号： H03H11/26 , H04L25/03878 , H04L2025/0349
摘要： Methods and circuits are presented for providing equalization, including decision feedback equalization (DFE), to high data-rate signals. Half-rate delay-chain circuitry produces delayed samples of an input signal using two or more delay-chain circuits operating at a fraction of the input signal data-rate. Two delay-chain circuits operating at one-half the input signal data-rate may be used. More generally, n delay-chain circuits operating at 1/n the input signal data-rate may be used. Multiplexer circuitry combines the outputs of the delay-chain circuits to produce an output signal including samples of the input signal at the input signal data-rate. Duplicate path DFE circuitry includes two paths used to provide DFE equalization while reducing the load of the DFE circuitry on the circuitry that precedes it. A first path produces delayed samples of a DFE signal, while a second path produces the DFE output signal from the delayed samples.
摘要翻译：提出了用于向高数据速率信号提供均衡的方法和电路，包括判决反馈均衡（DFE）。半速率延迟链电路使用以输入信号数据速率的一小部分工作的两个或多个延迟链电路产生输入信号的延迟采样。可以使用以输入信号数据速率的一半工作的两个延迟链电路。更一般地，可以使用以1 / n输入信号数据速率工作的n个延迟链电路。多路复用器电路组合延迟链电路的输出以产生包括输入信号数据速率的输入信号样本的输出信号。重复路径DFE电路包括用于提供DFE均衡的两个路径，同时减少DFE电路之前的电路上的DFE电路的负载。第一路径产生DFE信号的延迟采样，而第二路径产生来自延迟采样的DFE输出信号。

17. 发明授权

US07324031B1 Dynamic bias circuit 有权
标题翻译：动态偏置电路
公开(公告)号：US07324031B1
公开(公告)日：2008-01-29
申请号：US11355678
申请日：2006-02-15
申请人： Tin Lai , Wilson Wong , Sergey Yuryevich Shumarayev
发明人： Tin Lai , Wilson Wong , Sergey Yuryevich Shumarayev
IPC分类号： H03M1/66
CPC分类号： G11C7/12 , G11C7/1045 , H03M1/662
摘要： A bias circuit includes a digital to analog converter (D2A) generating an output representing a voltage level for tuning an analog signal. The D2A is coupled to a primary register frame that is one of a plurality of register frames forming a data chain. The plurality of register frames are serially linked and data within the data chain is shifted among the plurality of register frames. Through a time domain multiplexing scheme, the D2A can be shared by control knobs of the equalization circuit. The bias circuit includes a decoder also coupled to the primary register frame. An output enable logic module is also included. The output enable logic module determines when the primary register has a complete data set as the data within the data chain is shifting according to the clock period. A method for adjusting a signal through a bias circuit is also provided.
摘要翻译：偏置电路包括产生表示用于调谐模拟信号的电压电平的输出的数模转换器（D2A）。 D2A耦合到作为形成数据链的多个寄存器帧之一的主寄存器帧。多个寄存器帧被串行链接，数据链内的数据在多个寄存器帧之间移位。通过时域复用方案，D2A可由均衡电路的控制旋钮共享。偏置电路包括还耦合到主寄存器框架的解码器。还包括一个输出使能逻辑模块。当数据链中的数据根据时钟周期进行移位时，输出使能逻辑模块确定主寄存器何时具有完整的数据集。还提供了一种通过偏置电路调整信号的方法。

18. 发明授权

US08649461B2 Lane-to-lane skew reduction in multi-channel, high-speed, transceiver circuitry 失效
标题翻译：多通道，高速，收发器电路中的车道对车道偏斜减少
公开(公告)号：US08649461B2
公开(公告)日：2014-02-11
申请号：US13299630
申请日：2011-11-18
申请人： Sergey Yuryevich Shumarayev
发明人： Sergey Yuryevich Shumarayev
IPC分类号： H04L27/00
CPC分类号： H04L25/14
摘要： Controllable delay circuitry is included in each channel of multi-channel, high-speed, serial transmitter and/or receiver circuitry to compensate for or to at least help compensate for possible skew (different signal propagation time) between the various channels. In systems employing CDR circuitry, the delay circuitry may be at least partly controlled by a signal derived from the CDR circuitry to make the amount of delay effected by the delay circuitry at least partly responsive to changes in data rate detected by the CDR circuitry.
摘要翻译：可控延迟电路包括在多通道，高速，串行发射器和/或接收器电路的每个通道中，以补偿或至少帮助补偿各个通道之间的可能的偏斜（不同的信号传播时间）。在采用CDR电路的系统中，延迟电路可以由从CDR电路导出的信号至少部分地控制，以使由延迟电路影响的延迟量至少部分地响应由CDR电路检测到的数据速率的变化。

19. 发明授权

US08222967B1 Receiver equalizer circuitry having wide data rate and input common mode voltage ranges 有权
标题翻译：接收机均衡器电路具有宽数据速率和输入共模电压范围
公开(公告)号：US08222967B1
公开(公告)日：2012-07-17
申请号：US12644128
申请日：2009-12-22
申请人： Sangeeta Raman , Tim Tri Hoang , Sergey Yuryevich Shumarayev
发明人： Sangeeta Raman , Tim Tri Hoang , Sergey Yuryevich Shumarayev
IPC分类号： H03H7/30 , H03F3/45
CPC分类号： H03F3/45192 , H03F3/193 , H03F3/45197 , H03F3/45475 , H03F3/72 , H03F2200/405 , H03F2203/45488 , H03F2203/45494 , H03F2203/45686 , H03F2203/7236 , H03H11/1213 , H03H11/48
摘要： Equalizer circuitry on an integrated circuit (“IC”) includes a plurality of NMOS equalizer stages connected in series. Each NMOS stage may include folded active inductor circuitry. Each NMOS stage may also include various circuit elements having controllably variable circuit parameters so that the equalizer can be controllably adapted to perform for any of a wide range of high-speed serial data signal bit rates and other variations of communication protocols and/or communication conditions. For example, each NMOS stage may be programmable to control at least one of bandwidth and power consumption of the equalizer circuitry. The equalizer may also have a first PMOS stage that can be used instead of the first NMOS stage in cases in which the voltage of the incoming signal to be equalized is too low for an initial NMOS stage.
摘要翻译：集成电路（“IC”）上的均衡器电路包括串联连接的多个NMOS均衡器级。每个NMOS级可包括折叠的有源电感电路。每个NMOS级还可以包括具有可控制的可变电路参数的各种电路元件，使得均衡器可被可控地适用于执行宽范围的高速串行数据信号比特率和通信协议和/或通信条件的其它变化。例如，每个NMOS级可以是可编程的，以控制均衡器电路的带宽和功耗中的至少一个。在均衡的输入信号的电压对于初始NMOS级来说太低的情况下，均衡器也可以具有第一PMOS级，而不用第一NMOS级。

20. 发明授权

US07321259B1 Programmable logic enabled dynamic offset cancellation 有权
标题翻译：可编程逻辑使能动态偏移消除
公开(公告)号：US07321259B1
公开(公告)日：2008-01-22
申请号：US11245581
申请日：2005-10-06
申请人： Sergey Yuryevich Shumarayev
发明人： Sergey Yuryevich Shumarayev
IPC分类号： H03F1/02 , H04B1/04
CPC分类号： H03F3/45475 , H03F3/45183 , H03F3/45197 , H03F3/4521 , H03F3/45748 , H03F3/45973 , H03F2203/45136 , H03F2203/45212 , H03F2203/45236 , H03F2203/45366 , H03F2203/45482 , H03F2203/45494 , H03F2203/45681 , H03F2203/45702
摘要： Techniques and circuitry are provided for programmatically controlling signal offsets in integrated circuitry. In one embodiment, a buffer circuit having an offset cancellation circuit receives a signal and transmits the signal to programmable logic circuit. The programmable logic uses programmable resources and/or one or more algorithms to measure integrated circuit operations and/or operational errors associated with the offset. The control signal is fed back to an input of the offset cancellation circuit. In one embodiment, the offset cancellation circuit adjusts the offset of the signal in response to the magnitude of the offset cancellation signal received until changes associated with the offset and/or the magnitude of the operational errors are no longer attributable to the offset.
摘要翻译：提供技术和电路用于以编程方式控制集成电路中的信号偏移。在一个实施例中，具有偏移消除电路的缓冲器电路接收信号并将该信号发送到可编程逻辑电路。可编程逻辑使用可编程资源和/或一个或多个算法来测量与偏移相关联的集成电路操作和/或操作错误。控制信号被反馈到偏移消除电路的输入端。在一个实施例中，偏移消除电路响应于所接收的偏移消除信号的大小来调整信号的偏移，直到与偏移相关联的变化和/或操作误差的大小不再归因于偏移。

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