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1. 发明授权

US07639993B1 Power supply circuitry for data signal transceivers on integrated circuits 有权
标题翻译：集成电路上数据信号收发器的电源电路
公开(公告)号：US07639993B1
公开(公告)日：2009-12-29
申请号：US11295391
申请日：2005-12-05
申请人： Sergey Yuryevich Shumarayev , Rakesh Patel , William Bereza , Wilson Wong , Tim Tri Hoang
发明人： Sergey Yuryevich Shumarayev , Rakesh Patel , William Bereza , Wilson Wong , Tim Tri Hoang
IPC分类号： H04B1/04
CPC分类号： H04L7/033
摘要： The various components of transceiver circuitry on an integrated circuit are put together in various ways for purposes of being supplied with power to help prevent noise propagation between the groups. In the case of multi-channel transceiver circuitry there can be various amounts of power supply sharing between similar groups in multiple channels.
摘要翻译：集成电路中的收发器电路的各种组件以各种方式放在一起，以便被提供电力以帮助防止组之间的噪声传播。在多通道收发器电路的情况下，可以在多个通道中的类似组之间存在各种数量的电源共享。

2. 发明授权

US07539278B2 Programmable transceivers that are able to operate over wide frequency ranges 有权
标题翻译：能够在宽频率范围内工作的可编程收发器
公开(公告)号：US07539278B2
公开(公告)日：2009-05-26
申请号：US11292565
申请日：2005-12-02
申请人： Sergey Yuryevich Shumarayev , Rakesh Patel
发明人： Sergey Yuryevich Shumarayev , Rakesh Patel
IPC分类号： H03D3/24
CPC分类号： H03K19/17744 , H03L7/0995
摘要： A field-programmable gate array (“FPGA”) may include data receiver and/or transmitter circuitry that is adapted to receive and/or transmit data at any frequency(ies) or data rate(s) in a wide range of possible frequencies or data rates. Phase-locked loop (PLL) circuitry may be needed for operation of such receiver and/or transmitter circuitry. For satisfactory operation over the wide frequency range, multiple PLL circuits are provided. One of these PLL circuits may be capable of operating over the entire frequency range, possibly with better jitter performance in some portions of the range than in other portions of the range. One or more other PLL circuits may be provided that are focused on particular parts of the broad range, especially where the jitter performance of the first-mentioned PLL may not be adequate to meet some possible needs.
摘要翻译：现场可编程门阵列（“FPGA”）可以包括数据接收器和/或发射机电路，其适于在宽范围的可能频率中以任何频率或数据速率接收和/或发射数据，或数据速率。可能需要锁相环（PLL）电路来操作这种接收器和/或发射器电路。为了在宽频率范围内的令人满意的操作，提供了多个PLL电路。这些PLL电路中的一个可能能够在整个频率范围内运行，可能在该范围的某些部分中具有比该范围的其他部分更好的抖动性能。可以提供一个或多个其他PLL电路，其集中在宽范围的特定部分上，特别是在首先提到的PLL的抖动性能可能不足以满足一些可能需要的地方。

3. 发明授权

US07355449B1 High-speed serial data transmitter architecture 有权
标题翻译：高速串行数据发射机架构
公开(公告)号：US07355449B1
公开(公告)日：2008-04-08
申请号：US11345709
申请日：2006-02-01
申请人： Thungoc Tran , Sergey Yuryevich Shumarayev , Kazi Asaduzzaman , Wilson Wong , Mei Luo , Rakesh Patel
发明人： Thungoc Tran , Sergey Yuryevich Shumarayev , Kazi Asaduzzaman , Wilson Wong , Mei Luo , Rakesh Patel
IPC分类号： H03K19/094
CPC分类号： H03K19/17744 , H03K19/17732 , H04B1/005 , H04L25/028
摘要： Serial data transmitter circuitry on a PLD includes a number of features that enable the transmitter to support many different communication protocols under a wide range of circuit conditions. Examples of features that the transmitter may include are (1) multiple pre-emphasis circuits of selectable strength and polarity, (2) selectable VOD, (3) selectable slew rate, (4) calibratable termination, (5) selectable common mode voltage, and (6) electrical idle mode.
摘要翻译： PLD上的串行数据发射机电路包括许多功能，使得发射机能够在广泛的电路条件下支持许多不同的通信协议。发射机可以包括的特征的示例是（1）可选强度和极性的多个预加重电路，（2）可选择的VOD，（3）可选择的转换速率，（4）可校准终止，（5）可选择的共模电压，和（6）电气空闲模式。

4. 发明授权

US08416845B1 Decision feedback equalization for variable input amplitude 有权
标题翻译：用于可变输入幅度的判决反馈均衡
公开(公告)号：US08416845B1
公开(公告)日：2013-04-09
申请号：US11484285
申请日：2006-07-11
申请人： Wilson Wong , Sergey Yuryevich Shumarayev , Rakesh Patel , Tim Tri Hoang
发明人： Wilson Wong , Sergey Yuryevich Shumarayev , Rakesh Patel , Tim Tri Hoang
IPC分类号： H03H7/30 , H03H7/40 , H03K5/159
CPC分类号： H04L25/03057 , H03K5/1532
摘要： Methods and circuits for automatic adjustment of equalization are presented that improve the quality of equalization for input signals with varying amplitudes. The methods and circuits may be used in Decision Feedback Equalization (DFE) circuits to maintain a constant equalization boost amplitude despite variations in input signal amplitude. The equalization circuitry measures the amplitude of the equalization input signal and computes tap coefficients to maintain a desired level of boost amplitude. Tap coefficients may be automatically adjusted by the equalization circuitry.
摘要翻译：提出了用于自动调整均衡的方法和电路，其提高具有变化幅度的输入信号的均衡质量。方法和电路可以用于判决反馈均衡（DFE）电路中，以维持恒定的均衡提升幅度，尽管输入信号幅度有变化。均衡电路测量均衡输入信号的幅度并计算抽头系数以维持期望的升压幅度。抽头系数可以由均衡电路自动调整。

5. 发明授权

US07702011B2 High-speed serial data receiver architecture 有权
标题翻译：高速串行数据接收机架构
公开(公告)号：US07702011B2
公开(公告)日：2010-04-20
申请号：US11361192
申请日：2006-02-23
申请人： Thungoc Tran , Sergey Yuryevich Shumarayev , Simardeep Maangat , Wilson Wong , Rakesh Patel
发明人： Thungoc Tran , Sergey Yuryevich Shumarayev , Simardeep Maangat , Wilson Wong , Rakesh Patel
IPC分类号： H03H7/30
CPC分类号： H04L1/243 , H04L25/03878
摘要： Serial data signal receiver circuitry for inclusion on a PLD includes a plurality of equalizer circuits that are connected in series and that are individually controllable so that collectively they can compensate for a wide range of possible input signal attenuation characteristics. Other circuit features may be connected in relation to the equalizer circuits to give the receiver circuitry other capabilities. For example, these other features may include various types of loop-back test circuits, controllable termination resistance, controllable common mode voltage, and a controllable threshold for detection of an input signal. Various aspects of control of the receiver circuitry may be programmable.
摘要翻译：用于包含在PLD中的串行数据信号接收器电路包括串联连接并且可单独控制的多个均衡器电路，使得它们可以统一地补偿宽范围的可能的输入信号衰减特性。其他电路特征可以相对于均衡器电路连接以给予接收机电路其他能力。例如，这些其他特征可以包括各种类型的环回测试电路，可控终端电阻，可控共模电压以及用于检测输入信号的可控阈值。接收器电路的控制的各个方面可以是可编程的。

6. 发明授权

US08743943B2 High-speed data reception circuitry and methods 有权
标题翻译：高速数据接收电路和方法
公开(公告)号：US08743943B2
公开(公告)日：2014-06-03
申请号：US11192539
申请日：2005-07-28
申请人： Sergey Yuryevich Shumarayev , Wilson Wong , Rakesh Patel
发明人： Sergey Yuryevich Shumarayev , Wilson Wong , Rakesh Patel
IPC分类号： H03H7/30 , H03H7/40 , H03K5/159
CPC分类号： H04L25/03057 , H04L2025/0349 , H04L2025/03573
摘要： Equalization circuitry for receiving a digital data signal includes both feed-forward equalizer (“FFE”) circuitry and decision-feedback equalizer (“DFE”) circuitry. The FFE circuitry may be used to give the DFE circuitry a signal that is at least minimally adequate for proper start-up of the DFE circuitry. Thereafter, more of the burden of the equalization task may be shifted from the FFE circuitry to the DFE circuitry.
摘要翻译：用于接收数字数据信号的均衡电路包括前馈均衡器（“FFE”）电路和判决反馈均衡器（“DFE”）电路。 FFE电路可以用于给DFE电路提供至少最不足以适当启动DFE电路的信号。此后，均衡任务的更多负担可能从FFE电路转移到DFE电路。

7. 发明授权

US08189729B2 Wide range and dynamically reconfigurable clock data recovery architecture 有权
标题翻译：宽范围和动态可重构的时钟数据恢复架构
公开(公告)号：US08189729B2
公开(公告)日：2012-05-29
申请号：US11329197
申请日：2006-01-09
申请人： Tim Tri Hoang , Sergey Yuryevich Shumarayev , Wilson Wong , Rakesh Patel
发明人： Tim Tri Hoang , Sergey Yuryevich Shumarayev , Wilson Wong , Rakesh Patel
IPC分类号： H04L7/00
CPC分类号： H03L7/087 , H03K19/17732 , H03K19/17744 , H03L7/10 , H04L7/0004 , H04L7/033
摘要： Wide range and dynamically reprogrammable CDR architecture recovers an embedded clock signal from serial input data with a wide range of operating frequencies. In order to support a wide range of data rates, the CDR architecture includes multiple operating parameters. These parameters include various pre/post divider settings, charge pump currents, loop-filter and bandwidth selections, and VCO gears. The parameters may be dynamically reprogrammed without powering down the circuitry or PLD. This allows the CDR circuitry to switch between various standards and protocols on-the-fly.
摘要翻译：宽范围和动态可重新编程的CDR架构从具有广泛工作频率的串行输入数据中恢复嵌入式时钟信号。为了支持广泛的数据速率，CDR架构包括多个操作参数。这些参数包括各种前/后分频器设置，电荷泵电流，环路滤波器和带宽选择以及VCO齿轮。可以在不关闭电路或PLD的情况下动态重新编程参数。这允许CDR电路在各种标准和协议之间进行即时切换。

8. 发明授权

US10078695B2 Methods and systems for network based video clip generation and management 有权
公开(公告)号：US10078695B2
公开(公告)日：2018-09-18
申请号：US13444630
申请日：2012-04-11
申请人： Vincent Silvestri , Rakesh Patel
发明人： Vincent Silvestri , Rakesh Patel
IPC分类号： G06F17/30 , H04L29/06
CPC分类号： H04N21/231 , G06F16/78 , G06F16/951 , H04L65/4076 , H04L65/4084 , H04L65/604 , H04N21/278
摘要： Methods and system for managing media clips over a data network. Media streams may be received over a data network and stored by a storage server. Metadata regarding the media streams may be generated and stored at a metadata server. A control station can retrieve media frames originating in the stored media streams from the storage server, based on metadata. Media frames from multiple media streams can be retrieved and displayed in synchronization, based on respective timecodes.

9. 发明授权

US09131213B2 Method of generating a blockiness indicator for a video signal 有权
标题翻译：产生视频信号的块效应指示符的方法
公开(公告)号：US09131213B2
公开(公告)日：2015-09-08
申请号：US12203433
申请日：2008-09-03
申请人： Jeff Wei , Rakesh Patel
发明人： Jeff Wei , Rakesh Patel
IPC分类号： H04N7/26 , H04N17/00 , H04N19/86 , H04N19/17 , H04N19/82
CPC分类号： H04N19/176 , H04N7/0155 , H04N17/004 , H04N19/167 , H04N19/17 , H04N19/182 , H04N19/66 , H04N19/82 , H04N19/86 , H04N19/865 , H04N19/88
摘要： The described embodiments relate to methods and systems for detecting the blockiness of a video signal comprised of a number of pixels. The method includes the steps of calculating a total number of pixels in the video signal in flat blocks and visible block edge transitions, and generating a blockiness indicator from the total number of pixels in flat blocks and visible block edge transitions. The step of calculating the total number of pixels in flat blocks and the total number of pixels in visible block edge transitions may include calculating differential values for each pixel in the video signal, analyzing the differential values to determine if the pixel is part of a transition and/or a flat area and then counting the number of pixels in flat blocks and visible block edge transitions to produce a total number of pixels in flat blocks and a total number of pixels in visible block edge transitions.
摘要翻译：所描述的实施例涉及用于检测包括多个像素的视频信号的块效应的方法和系统。该方法包括以下步骤：在平面块和可见块边缘转换中计算视频信号中的像素总数，并从平面块和可见块边缘转换中的像素总数生成块状指示符。计算平面块中的像素总数和可见块边缘转换中的像素总数的步骤可以包括计算视频信号中每个像素的差分值，分析差分值以确定像素是否是转变的一部分和/或平坦区域，然后对平坦块和可见块边缘过渡中的像素数进行计数，以产生平坦块中的像素总数和可见块边缘转换中的像素总数。

10. 发明授权

US08918523B2 Graphical user interface (GUI) for administering a network implementing media aggregation 有权
标题翻译：用于管理实现媒体聚合的网络的图形用户界面（GUI）
公开(公告)号：US08918523B2
公开(公告)日：2014-12-23
申请号：US13469610
申请日：2012-05-11
申请人： Siddhartha Nag , Alfred D'Souza , Naveed Alam , Rakesh Patel
发明人： Siddhartha Nag , Alfred D'Souza , Naveed Alam , Rakesh Patel
IPC分类号： G06F15/16 , H04L12/24 , H04L29/06 , H04M7/00
CPC分类号： H04L41/147 , H04L29/06027 , H04L41/0213 , H04L41/0806 , H04L41/0896 , H04L41/12 , H04L41/145 , H04L41/20 , H04L41/22 , H04L65/1009 , H04L65/1069 , H04L65/80 , H04M7/0081
摘要： A graphical user interface (GUI) is disclosed that allows a user to identify routers, communities, residents and media aggregation managers existing on a network. The user may interactively select a path that includes two media aggregation managers and at least one router. The GUI predicts scheduled bandwidth utilization along the selected path for a variety of residents wishing to communicate across the path. The GUI may be utilized for initializing all media aggregation managers on the network along with provisioning each of the routers on the selected path. The GUI provisions all of the routers and initializes all of the media aggregation managers on the selected path simultaneously in order to accomplish the predicted schedule of usage provided by the GUI to the user and force all communication packets communicated between the residents to travel along the selected path.
摘要翻译：公开了图形用户界面（GUI），其允许用户识别存在于网络上的路由器，社区，居民和媒体聚合管理器。用户可以交互地选择包括两个媒体聚合管理器和至少一个路由器的路径。 GUI预测沿希望通过路径进行通信的各种居民所选路径的预定带宽利用率。 GUI可以用于初始化网络上的所有媒体聚合管理器，同时提供所选路径上的每个路由器。 GUI为所有路由器提供所有路由器并同时初始化所选路径上的所有媒体聚合管理器，以便完成由GUI向用户提供的预测使用时间表，并强制居民之间通信的所有通信包沿所选路径行进路径。

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