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11. 发明申请

US20110114597A1 BARRIER INTEGRATION SCHEME FOR HIGH-RELIABILITY VIAS 审中-公开
标题翻译：用于高可靠性VIAS的障碍整合方案
公开(公告)号：US20110114597A1
公开(公告)日：2011-05-19
申请号：US12834598
申请日：2010-07-12
申请人： Alfred J. Griffin, JR. , Edmund Burke , Asad M. Haider , Kelly J. Taylor , Tae S. Kim
发明人： Alfred J. Griffin, JR. , Edmund Burke , Asad M. Haider , Kelly J. Taylor , Tae S. Kim
IPC分类号： H01L21/00
CPC分类号： H01L21/76802 , H01L21/02063 , H01L21/2855 , H01L21/32131 , H01L21/76805 , H01L21/76829 , H01L21/76844 , H01L21/76846 , H01L21/76847 , H01L21/76867 , H01L23/5226 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： Disclosed is a method of fabricating an integrated circuit comprising patterning a dielectric layer to form a hole having a sidewall and a bottom. The hole can expose an underlying material of an electrically conducting material. The method also includes exposing the sidewall and the exposed underlying material to a plasma etch, depositing a barrier layer on the bottom and the sidewall of the hole after the plasma etch clean, forming a counter-sunk cone in the underlying material by etching through the barrier layer at the bottom of the hole into the conducting metal underneath, flash depositing a thin layer of the barrier material into the hole, and finally depositing a metal seed layer in the hole covering the sidewalls and the bottom of the hole including the cone at the bottom. The hole is finally filled by depositing a metal layer in the hole.
摘要翻译：公开了一种制造集成电路的方法，包括图案化介电层以形成具有侧壁和底部的孔。孔可以暴露导电材料的下层材料。该方法还包括将侧壁和暴露的下层材料暴露于等离子体蚀刻，在等离子体蚀刻清洁之后，在孔的底部和侧壁上沉积阻挡层，在下面的材料中通过蚀刻通过在孔的底部的阻挡层进入下面的导电金属，将阻挡材料的薄层快速沉积到孔中，最后在覆盖包括锥体的孔的侧壁和底部的孔中沉积金属种子层底端。最后通过在孔中沉积金属层来填充孔。

12. 发明授权

US07732324B2 Semiconductor device having improved adhesion and reduced blistering between etch stop layer and dielectric layer 有权
标题翻译：半导体器件具有改善的粘附性并减少蚀刻停止层和电介质层之间的起泡
公开(公告)号：US07732324B2
公开(公告)日：2010-06-08
申请号：US11961464
申请日：2007-12-20
申请人： Ju-Ai Ruan , Sameer K. Ajmera , Changming Jin , Anand J. Reddy , Tae S. Kim
发明人： Ju-Ai Ruan , Sameer K. Ajmera , Changming Jin , Anand J. Reddy , Tae S. Kim
IPC分类号： H01L21/469
CPC分类号： H01L23/53295 , H01L21/76832 , H01L21/76834 , H01L23/5222 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： One aspect of the invention provides a method of forming a semiconductor device (100). One aspect includes forming transistors (120, 125) on a semiconductor substrate (105), forming a first interlevel dielectric layer (165) over the transistors (120, 125), and forming metal interconnects (170, 175) within the first interlevel dielectric layer (165). A carbon-containing gas is used to form a silicon carbon nitride (SiCN) layer (180) over the metal interconnects (170, 175) and the first interlevel dielectric layer (165) within a deposition tool. An adhesion layer (185) is formed on the SiCN layer (180), within the deposition tool, by discontinuing a flow of the carbon-containing gas within the deposition chamber. A second interlevel dielectric layer (190) is formed over the adhesion layer (185).
摘要翻译：本发明的一个方面提供了形成半导体器件（100）的方法。一个方面包括在半导体衬底（105）上形成晶体管（120,125），在晶体管（120,125）之上形成第一层间电介质层（165），并在第一层间电介质内形成金属互连（170,175）层（165）。使用含碳气体在沉积工具内的金属互连（170,175）和第一层间介电层（165）上形成氮化硅（SiCN）层（180）。通过中断沉积室内的含碳气体的流动，在沉积工具内在SiCN层（180）上形成粘附层（185）。第二层间介质层（190）形成在粘合层（185）上方。

13. 发明申请

US20090085120A1 Method for Reduction of Resist Poisoning in Via-First Trench-Last Dual Damascene Process 审中-公开
标题翻译：通过第一次沟槽 - 最后的双镶嵌工艺减少抗蚀剂中毒的方法
公开(公告)号：US20090085120A1
公开(公告)日：2009-04-02
申请号：US11863448
申请日：2007-09-28
申请人： Zhijian Lu , Tae S. Kim
发明人： Zhijian Lu , Tae S. Kim
IPC分类号： H01L21/768 , H01L21/8234 , H01L27/088
CPC分类号： H01L21/7684 , H01L21/31144 , H01L21/76813 , H01L21/76816 , H01L23/522 , H01L2924/0002 , H01L2924/00
摘要： Fabrication of interconnects in integrated circuits (ICs) use low-k dielectric materials, nitrogen containing dielectric materials, copper metal lines, dual damascene processing and amplified photoresists to build features smaller than 100 nm. Regions of an IC with low via density are subject to nitrogen diffusion from nitrogen containing dielectric materials into low-k dielectric material, and subsequent interference with forming patterns in amplified photoresists, a phenomenon known as resist poisoning, which results in defective interconnects. Attempts to solve this problem cause lower IC circuit performance or higher fabrication process cost and complexity. This invention comprises a dummy via and a method of placing dummy vias in a manner that reduces resist poisoning without impairing circuit performance or increasing fabrication process cost or complexity.
摘要翻译：集成电路（IC）中互连的制造使用低k电介质材料，含氮介电材料，铜金属线，双镶嵌处理和放大光致抗蚀剂，以构建小于100nm的特征。具有低通孔密度的IC的区域经受从含氮介电材料的氮扩散到低k电介质材料中，并且随后在放大的光致抗蚀剂中形成图案的干扰，这被称为抗蚀剂中毒，这导致不良互连。解决这个问题的尝试导致IC电路性能降低或者制造工艺成本和复杂性更高。本发明包括虚拟通孔和以减少抗蚀剂中毒而不损害电路性能或增加制造工艺成本或复杂性的方式放置虚拟通孔的方法。

14. 发明授权

US06506616B1 Photolithographic method for fabricating organic light-emitting diodes 有权
标题翻译：用于制造有机发光二极管的光刻方法
公开(公告)号：US06506616B1
公开(公告)日：2003-01-14
申请号：US09714472
申请日：2000-11-16
申请人： Tae S. Kim , Francis G. Celii , Simon J. Jacobs
发明人： Tae S. Kim , Francis G. Celii , Simon J. Jacobs
IPC分类号： H01L2100
CPC分类号： H01L51/56 , H01L51/0018 , H01L51/5253
摘要： A method of photolithographically patterning an organic semiconductor device, comprising the steps of protecting the organic layer of the device by depositing a metal layer thereon, depositing and patterning a photoresist layer on said metal layer, and selectively etching the exposed areas to pattern said metal layer and said organic layer. Specifically, the disclosed method provides the photolithographic fabrication of organic light emitting diodes (OLEDs) and organic lasers diodes (OLDs).
摘要翻译：一种光刻图案化有机半导体器件的方法，包括以下步骤：通过在其上沉积金属层来保护器件的有机层，在所述金属层上沉积和图案化光致抗蚀剂层，并且选择性地蚀刻暴露的区域以图案化所述金属层并说有机层。具体地，所公开的方法提供有机发光二极管（OLED）和有机激光二极管（OLD）的光刻制造。

15. 发明授权

US5342795A Method of fabricating power VFET gate-refill 失效
标题翻译：制造功率VFET栅极补充的方法
公开(公告)号：US5342795A
公开(公告)日：1994-08-30
申请号：US153121
申请日：1993-11-15
申请人： Han-Tzong Yuan , Donald L. Plumton , Tae S. Kim , Jau-Yuann Yang
发明人： Han-Tzong Yuan , Donald L. Plumton , Tae S. Kim , Jau-Yuann Yang
IPC分类号： H01L21/335 , H01L21/337 , H01L29/207 , H01L29/772 , H01L21/44
CPC分类号： H01L29/66454 , H01L29/207 , H01L29/66924 , H01L29/7722 , Y10S148/04
摘要： This is a method of forming a vertical transistor device comprising: forming an n-type first drain/source layer 42; patterning a portion of the first drain/source layer 42 to form a channel 44 and a trench; forming a p-type gate structure 46 in the trench; and forming a n-type second drain/source layer 48 over the gate structure 46 and the channel 44; contacting the gate structure 54; forming p-ohmic contact to the gate structure 56; forming n-ohmic source contact 54; and forming n-ohmic drain contact 58. Other devices and methods are also disclosed.
摘要翻译：这是形成垂直晶体管器件的方法，包括：形成n型第一漏极/源极层42; 图案化第一漏极/源极层42的一部分以形成沟道44和沟槽; 在沟槽中形成p型栅极结构46; 以及在栅极结构46和沟道44上形成n型第二漏极/源极层48; 接触门结构54; 与门结构56形成p欧姆接触; 形成n-欧姆源触点54; 并形成n欧姆漏极触点58.还公开了其它装置和方法。

16. 发明申请

US20090160059A1 Semiconductor Device Having Improved Adhesion and Reduced Blistering Between Etch Stop Layer and Dielectric Layer 有权
标题翻译：具有改进的粘附性和减少在阻止层和介电层之间的起泡的半导体器件
公开(公告)号：US20090160059A1
公开(公告)日：2009-06-25
申请号：US11961464
申请日：2007-12-20
申请人： Ju-Ai Ruan , Sameer K. Ajmera , Changming Jin , Anand J. Reddy , Tae S. Kim
发明人： Ju-Ai Ruan , Sameer K. Ajmera , Changming Jin , Anand J. Reddy , Tae S. Kim
IPC分类号： H01L23/52 , H01L21/4763
CPC分类号： H01L23/53295 , H01L21/76832 , H01L21/76834 , H01L23/5222 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： One aspect of the invention provides a method of forming a semiconductor device (100). One aspect includes forming transistors (120, 125) on a semiconductor substrate (105), forming a first interlevel dielectric layer (165) over the transistors (120, 125), and forming metal interconnects (170, 175) within the first interlevel dielectric layer (165). A carbon-containing gas is used to form a silicon carbon nitride (SiCN) layer (180) over the metal interconnects (170, 175) and the first interlevel dielectric layer (165) within a deposition tool. An adhesion layer (185) is formed on the SiCN layer (180), within the deposition tool, by discontinuing a flow of the carbon-containing gas within the deposition chamber. A second interlevel dielectric layer (190) is formed over the adhesion layer (185).
摘要翻译：本发明的一个方面提供一种形成半导体器件（100）的方法。一个方面包括在半导体衬底（105）上形成晶体管（120,125），在晶体管（120,125）之上形成第一层间电介质层（165），并在第一层间电介质内形成金属互连（170,175）层（165）。使用含碳气体在沉积工具内的金属互连（170,175）和第一层间介电层（165）上形成氮化硅（SiCN）层（180）。通过中断沉积室内的含碳气体的流动，在沉积工具内在SiCN层（180）上形成粘附层（185）。第二层间介质层（190）形成在粘合层（185）上方。

17. 发明授权

US06509574B2 Optocouplers having integrated organic light-emitting diodes 有权
公开(公告)号：US06509574B2
公开(公告)日：2003-01-21
申请号：US09728155
申请日：2000-12-04
申请人： Han-Tzong Yuan , Tae S. Kim , Simon J. Jacobs , Francis G. Celii
发明人： Han-Tzong Yuan , Tae S. Kim , Simon J. Jacobs , Francis G. Celii
IPC分类号： G02B2700
CPC分类号： H01L31/173 , H01L27/3227
摘要： An optocoupler structure comprising a semiconductor chip having an integrated circuit and an optically transparent, electrically insulating layer having first and second surfaces; an organic diode integral with said first surface, said diode operable to emit electromagnetic radiation; and said circuit including a radiation-sensitive semiconductor device integral with said second surface, electrically isolated from said diode, and positioned in the path of said radiation.

18. 发明授权

US5468661A Method of making power VFET device 失效
标题翻译：制造电源VFET器件的方法
公开(公告)号：US5468661A
公开(公告)日：1995-11-21
申请号：US78388
申请日：1993-06-17
申请人： Han-Tzong Yuan , Donald L. Plumton , Tae S. Kim , Jau-Yuann Yang
发明人： Han-Tzong Yuan , Donald L. Plumton , Tae S. Kim , Jau-Yuann Yang
IPC分类号： H01L21/335 , H01L21/337 , H01L29/808 , H01L21/8258
CPC分类号： H01L29/66454 , H01L29/66924 , H01L29/8083
摘要： This is a method of forming a vertical transistor device comprising: forming an n-type first drain/source layer 42; patterning a portion of the first drain/source layer 42 to form a channel 44 and a trench; forming a p-type gate structure 46 in the trench; and forming a n-type second drain/source layer 48 over the gate structure 46 and the channel 44. Other devices and methods are also disclosed.
摘要翻译：这是形成垂直晶体管器件的方法，包括：形成n型第一漏极/源极层42; 图案化第一漏极/源极层42的一部分以形成沟道44和沟槽; 在沟槽中形成p型栅极结构46; 以及在栅极结构46和沟道44上形成n型第二漏极/源极层48.还公开了其它器件和方法。

19. 发明授权

US5244829A Organometallic vapor-phase epitaxy process using (CH.sub.3).sub.3 As and CCl.sub.4 for improving stability of carbon-doped GaAs 失效
标题翻译：使用（CH3）3As和CCl4的有机金属气相外延法改善碳掺杂GaAs的稳定性
公开(公告)号：US5244829A
公开(公告)日：1993-09-14
申请号：US910934
申请日：1992-07-09
申请人： Tae S. Kim
发明人： Tae S. Kim
IPC分类号： C30B25/14 , H01L21/02 , H01L21/205
CPC分类号： H01L21/02579 , H01L21/02395 , H01L21/02546 , H01L21/0262 , Y10S148/11 , Y10S438/925
摘要： The use of trimethylarsine in place of tertiary butyl arsine for low pressure organometallic vapor phase epitaxy of GaAs:C to enhance the carbon doping efficiency of CCl.sub.4. The hole concentration is three times higher with trimethylarsine then with tertiary butyl arsine in the layer grown under similar conditions. As a result, higher growth temperatures can be used with trimethyl arsine, yielding more stable carbon doping. Annealing at 650.degree. C. for 5 minutes does not degrade the trimethyl arsine-grown layers while the tertiary butyl arsine-grown layer shows decreases in both hole concentration and mobility. Also a high level of hydrogen atoms is detected in tertiary butyl arsine-grown GaAs:C. The hydrogen level is about 30 times lower in the layers grown with trimethyl arsine. The reduced hydrogen concentration is an added advantage of using trimethyl arsine since hydrogen is known to neutralize acceptors in GaAs to reduce the carrier concentrations.

20. 发明授权

US5756375A Semiconductor growth method with thickness control 失效
标题翻译：具有厚度控制的半导体生长方法
公开(公告)号：US5756375A
公开(公告)日：1998-05-26
申请号：US664940
申请日：1996-06-14
申请人： Francis G. Celii , Walter M. Duncan , Tae S. Kim
发明人： Francis G. Celii , Walter M. Duncan , Tae S. Kim
IPC分类号： H01L21/205 , H01L21/66 , H01L21/203
CPC分类号： B24B37/013 , H01L22/26 , H01L21/02392 , H01L21/02463 , H01L21/02546
摘要： Molecular beam epitaxy (202) with growing layer thickness and doping control (206) by feedback of sensor signals such as spectrosceopic ellipsometer signals based on a process model. Examples include III-V compound structures with multiple AlAs, InGaAs, and InAs layers as used in resonant tunneling diodes and hetrojunction bipolar transistors with doped and undoped GaAs layers, AlGaAs and InGaAs.
摘要翻译：通过基于过程模型的传感器信号（例如光谱椭偏仪信号）的反馈，分子束外延（202）具有增长的层厚度和掺杂控制（206）。实例包括具有多个AlAs，InGaAs和InAs层的III-V化合物结构，其用于具有掺杂和未掺杂的GaAs层，AlGaAs和InGaAs的谐振隧道二极管和掺杂双极晶体管。

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