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1. 发明授权

US08514919B2 Synthetic instrument unit 有权
标题翻译：合成仪器单元
公开(公告)号：US08514919B2
公开(公告)日：2013-08-20
申请号：US13126127
申请日：2010-08-25
申请人： Anthony J. Estrada , Dana C. Ford , Tae S. Kim , Robert W. Lowdermilk , Dragan Vuletic
发明人： Anthony J. Estrada , Dana C. Ford , Tae S. Kim , Robert W. Lowdermilk , Dragan Vuletic
IPC分类号： H04B17/00
CPC分类号： G01R23/16 , G01R19/2516
摘要： Systems and other embodiments associated with synthetic instrumentation are presented. A reconfigurable synthetic instrumentation unit comprises an input module, with dual input/output ports and conditioning logic to condition an input signal. An RF down converter selectively down converts the conditioned input signal. A sampled RF down converter selectively samples the conditioned input signal. A pair of narrowband A/D converters are configured to convert one of the conditioned signal, the down converted signal and the sampled signal to produce a narrowband digital signal. A pair of broadband A/D converters convert at least one of the conditioned signal, the down converted signal and the sampled signal to produce a broadband digital signal. Signal processing logic selectively performs digital signal processing on the broadband digital signal or the narrow band digital signal.
摘要翻译：介绍了与合成仪器相关的系统和其他实施例。可重构的合成仪表单元包括具有双输入/输出端口和调节逻辑的输入模块，用于调节输入信号。 RF下变频器选择性地降低转换经调节的输入信号。采样的RF下变频器选择性地对经调节的输入信号进行采样。一对窄带A / D转换器被配置为转换调节信号，下变频信号和采样信号中的一个，以产生窄带数字信号。一对宽带A / D转换器将调节信号，下变频信号和采样信号中的至少一个转换成宽带数字信号。信号处理逻辑选择性地对宽带数字信号或窄带数字信号执行数字信号处理。

2. 发明申请

US20080153282A1 METHOD FOR PREPARING A METAL FEATURE SURFACE 审中-公开
标题翻译：制备金属特征表面的方法
公开(公告)号：US20080153282A1
公开(公告)日：2008-06-26
申请号：US11614185
申请日：2006-12-21
申请人： Manoj K. Jain , Tae S. Kim , Stephan Grunow
发明人： Manoj K. Jain , Tae S. Kim , Stephan Grunow
IPC分类号： H01L21/02
CPC分类号： H01L23/53238 , H01L21/02063 , H01L21/02068 , H01L21/76814 , H01L2924/0002 , Y10T29/49002 , H01L2924/00
摘要： Provided is a method for manufacturing an interconnect. The method for manufacturing the interconnect, in one embodiment, includes forming a first metal feature over or within a substrate, the first metal feature having an exposed surface. The method for manufacturing the interconnect may additionally include cleaning the exposed surface using a reactive system with a reducing agent, and subjecting the exposed surface to a plasma etch. The method for manufacturing the interconnect may further include contacting the first metal feature with a second metal feature.
摘要翻译：提供一种制造互连的方法。在一个实施例中，用于制造互连的方法包括在衬底上或衬底内形成第一金属特征，第一金属特征具有暴露表面。用于制造互连的方法可以另外包括使用具有还原剂的反应系统清洁暴露的表面，以及对暴露的表面进行等离子体蚀刻。用于制造互连的方法还可以包括使第一金属特征与第二金属特征接触。

3. 发明授权

US5610085A Method of making a vertical FET using epitaxial overgrowth 失效
标题翻译：使用外延生长制造垂直FET的方法
公开(公告)号：US5610085A
公开(公告)日：1997-03-11
申请号：US483028
申请日：1995-06-07
申请人： Han-Tzong Yuan , Tae S. Kim , Donald L. Plumton
发明人： Han-Tzong Yuan , Tae S. Kim , Donald L. Plumton
IPC分类号： H01L21/335 , H01L27/06 , H01L29/04 , H01L29/10 , H01L29/808 , H01L21/265
CPC分类号： H01L29/66454 , H01L27/0605 , H01L29/045 , H01L29/1066 , H01L29/1075 , H01L29/8083
摘要： A vertical field effect transistor (1700) and fabrication method with buried gates (1704) having spaced apart gate fingers and connecting structure and overgrown with source and channel epilayer followed by a doping connection of the gate fingers and connecting structure is disclosed. The vertical field effect transistor elements (1702, 1704, 1706, 1708, 1720, 1724) are made of III-V semiconductor compound grown on a germanium substrate (1726).
摘要翻译：公开了一种垂直场效应晶体管（1700）和具有间隔开的栅极指和连接结构的掩埋栅极（1704）的制造方法，并且随着源极和沟道外延层上覆盖，随后是栅极指状物和连接结构的掺杂连接。垂直场效应晶体管元件（1702,1704,1706,1708,1720,1724）由在锗衬底（1726）上生长的III-V半导体化合物制成。

4. 发明申请

US20120020397A1 SYNTHETIC INSTRUMENT UNIT 有权
标题翻译：合成仪器单元
公开(公告)号：US20120020397A1
公开(公告)日：2012-01-26
申请号：US13126127
申请日：2010-08-25
申请人： Anthony J. Estrada , Dana C. Ford , Tae S. Kim , Robert W. Lowdermilk , Dragan Vuletic
发明人： Anthony J. Estrada , Dana C. Ford , Tae S. Kim , Robert W. Lowdermilk , Dragan Vuletic
IPC分类号： H04B17/00
CPC分类号： G01R23/16 , G01R19/2516
摘要： Systems and other embodiments associated with synthetic instrumentation are presented. A reconfigurable synthetic instrumentation unit comprises an input module, with dual input/output ports and conditioning logic to condition an input signal. An RF down converter selectively down converts the conditioned input signal. A sampled RF down converter selectively samples the conditioned input signal. A pair of narrowband A/D converters are configured to convert one of the conditioned signal, the down converted signal and the sampled signal to produce a narrowband digital signal. A pair of broadband A/D converters convert at least one of the conditioned signal, the down converted signal and the sampled signal to produce a broadband digital signal. Signal processing logic selectively performs digital signal processing on the broadband digital signal or the narrow band digital signal.
摘要翻译：介绍了与合成仪器相关的系统和其他实施例。可重构的合成仪表单元包括具有双输入/输出端口和调节逻辑的输入模块，用于调节输入信号。 RF下变频器选择性地降低转换经调节的输入信号。采样的RF下变频器选择性地对经调节的输入信号进行采样。一对窄带A / D转换器被配置为转换调节信号，下变频信号和采样信号中的一个，以产生窄带数字信号。一对宽带A / D转换器将调节信号，下变频信号和采样信号中的至少一个转换成宽带数字信号。信号处理逻辑选择性地对宽带数字信号或窄带数字信号执行数字信号处理。

5. 发明授权

US06409828B1 Method and apparatus for achieving a desired thickness profile in a flow-flange reactor 失效
标题翻译：在流动法兰反应器中实现所需厚度分布的方法和装置
公开(公告)号：US06409828B1
公开(公告)日：2002-06-25
申请号：US08526828
申请日：1995-09-12
申请人： Tae S. Kim
发明人： Tae S. Kim
IPC分类号： C30B2516
CPC分类号： C30B25/02 , C23C16/455 , C23C16/52 , C30B25/14 , C30B29/40
摘要： A method and apparatus are disclosed for achieving a desired thickness profile in a semiconductor device (44) using a flow-flange reactor (10), by adjusting input flow ratios in the flow-flange (12) of the reactor (10). A target thickness profile is established. A first set of optimum input flow ratios are then determined in response to the target thickness profile, based upon a first plurality of sample thickness profiles and a first plurality of sets of sample input flow ratios, wherein each of the sample thickness profiles corresponds to one of the first plurality of sets of sample input flow ratios. The input flow ratios of the reactor (10) are then adjusted in response to the first optimum set of input flow ratios.
摘要翻译：公开了一种通过调节反应器（10）的流动凸缘（12）中的输入流量比来使用流动法兰反应器（10）在半导体器件（44）中实现所需厚度分布的方法和装置。建立目标厚度剖面。然后基于第一多个样品厚度分布和第一组多组样品输入流量比来响应于目标厚度分布来确定第一组最佳输入流量比，其中每个样品厚度分布对应于一个的第一组多组样本输入流量比。然后响应于第一最佳输入流量组而调节反应器（10）的输入流量比。

6. 发明授权

US6008519A Vertical transistor and method 失效
标题翻译：垂直晶体管和方法
公开(公告)号：US6008519A
公开(公告)日：1999-12-28
申请号：US990549
申请日：1997-12-15
申请人： Han-Tzong Yuan , Donald L. Plumpton , Jau-Yuann Yang , Tae S. Kim
发明人： Han-Tzong Yuan , Donald L. Plumpton , Jau-Yuann Yang , Tae S. Kim
IPC分类号： H01L21/335 , H01L29/772 , H01L29/76 , H01L29/74 , H01L29/80
CPC分类号： H01L29/66416 , H01L29/7722
摘要： A vertical transistor (70) comprising a first semiconductor layer (14) of a first conductive type. A gate structure (32) of a second conductive type disposed on the first semiconductor layer (14). The gate structure (32) may include a plurality of gates (38) separated by channels (40). A second semiconductor layer (50) of the first conductive type may be disposed over the gate structure (32) and in the channels (40). An arresting element (36) may be disposed between and upper surface of the gates (38) and the second semiconductor layer (50). A void (52) may be formed in the second semiconductor layer (50) over the gate (38).
摘要翻译：一种包括第一导电类型的第一半导体层（14）的垂直晶体管（70）。设置在第一半导体层（14）上的第二导电类型的栅极结构（32）。栅极结构（32）可以包括由通道（40）分开的多个栅极（38）。第一导电类型的第二半导体层（50）可以设置在栅极结构（32）上和通道（40）中。止动元件（36）可以设置在栅极（38）和第二半导体层（50）的上表面之间。可以在栅极（38）上的第二半导体层（50）中形成空穴（52）。

7. 发明授权

US5516722A Method for increasing doping uniformity in a flow flange reactor 失效
标题翻译：在流动法兰反应器中增加掺杂均匀性的方法
公开(公告)号：US5516722A
公开(公告)日：1996-05-14
申请号：US331844
申请日：1994-10-31
申请人： Tae S. Kim
发明人： Tae S. Kim
IPC分类号： C30B25/14 , H01L21/205 , H01L21/20
CPC分类号： C23C16/45561 , C30B25/14 , Y10S438/935
摘要： The present invention comprises a method and apparatus for increasing doping uniformity in semiconductor devices produced in a flow flange reactor. One aspect of the present invention involves dividing the flow flange (12) of the reactor into a plurality of sections (14, 16, 18). Each section (14, 16, 18) is then subdivided into a plurality of subsections (52, 54, 56) including a first subsection (52), a second subsection (54) and a third subsection (56). A group III gas may then be dispersed in the first subsection (52) of at least one section (18). A group V gas may then be dispersed in a second subsection (54) of that section, while a dopant gas may also be dispersed in a third subsection (56) of that section (18).
摘要翻译：本发明包括用于增加在流动法兰反应器中制造的半导体器件中的掺杂均匀性的方法和装置。本发明的一个方面涉及将反应器的流动凸缘（12）分成多个部分（14,16,18）。然后，每个部分（14,16,18）被细分为包括第一子部分（52），第二子部分（54）和第三子部分（56）的多个子部分（52,54,56）。然后可以将III族气体分散在至少一个部分（18）的第一部分（52）中。然后V族气体可以分散在该部分的第二部分（54）中，而掺杂剂气体也可以分散在该部分（18）的第三子部分（56）中。

8. 发明授权

US5231037A Method of making a power VFET device using a p+ carbon doped gate layer 失效
标题翻译：使用p +碳掺杂栅极层制造功率VFET器件的方法
公开(公告)号：US5231037A
公开(公告)日：1993-07-27
申请号：US876252
申请日：1992-04-30
申请人： Han-Tzong Yuan , Tae S. Kim , Francis J. Morris
发明人： Han-Tzong Yuan , Tae S. Kim , Francis J. Morris
IPC分类号： H01L29/80 , H01L21/335 , H01L21/337 , H01L29/207 , H01L29/772
CPC分类号： H01L29/66454 , H01L29/207 , H01L29/66924 , H01L29/7722 , Y10S148/04
摘要： This is a method of forming a vertical transistor device. The method comprises: forming a n-type source layer 12; forming a p+ carbon doped gate layer 14; forming a gate structure from the gate layer; and forming a n-type drain layer 16 over the gate structure to provide a buried carbon doped gate structure. The buried carbon doped gate structure provides a very small device with favorable on-resistance, junction capacitance, gate resistance, and gate driving voltage. Other devices and methods are also disclosed.

9. 发明申请

US20110114597A1 BARRIER INTEGRATION SCHEME FOR HIGH-RELIABILITY VIAS 审中-公开
标题翻译：用于高可靠性VIAS的障碍整合方案
公开(公告)号：US20110114597A1
公开(公告)日：2011-05-19
申请号：US12834598
申请日：2010-07-12
申请人： Alfred J. Griffin, JR. , Edmund Burke , Asad M. Haider , Kelly J. Taylor , Tae S. Kim
发明人： Alfred J. Griffin, JR. , Edmund Burke , Asad M. Haider , Kelly J. Taylor , Tae S. Kim
IPC分类号： H01L21/00
CPC分类号： H01L21/76802 , H01L21/02063 , H01L21/2855 , H01L21/32131 , H01L21/76805 , H01L21/76829 , H01L21/76844 , H01L21/76846 , H01L21/76847 , H01L21/76867 , H01L23/5226 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： Disclosed is a method of fabricating an integrated circuit comprising patterning a dielectric layer to form a hole having a sidewall and a bottom. The hole can expose an underlying material of an electrically conducting material. The method also includes exposing the sidewall and the exposed underlying material to a plasma etch, depositing a barrier layer on the bottom and the sidewall of the hole after the plasma etch clean, forming a counter-sunk cone in the underlying material by etching through the barrier layer at the bottom of the hole into the conducting metal underneath, flash depositing a thin layer of the barrier material into the hole, and finally depositing a metal seed layer in the hole covering the sidewalls and the bottom of the hole including the cone at the bottom. The hole is finally filled by depositing a metal layer in the hole.
摘要翻译：公开了一种制造集成电路的方法，包括图案化介电层以形成具有侧壁和底部的孔。孔可以暴露导电材料的下层材料。该方法还包括将侧壁和暴露的下层材料暴露于等离子体蚀刻，在等离子体蚀刻清洁之后，在孔的底部和侧壁上沉积阻挡层，在下面的材料中通过蚀刻通过在孔的底部的阻挡层进入下面的导电金属，将阻挡材料的薄层快速沉积到孔中，最后在覆盖包括锥体的孔的侧壁和底部的孔中沉积金属种子层底端。最后通过在孔中沉积金属层来填充孔。

10. 发明授权

US07732324B2 Semiconductor device having improved adhesion and reduced blistering between etch stop layer and dielectric layer 有权
标题翻译：半导体器件具有改善的粘附性并减少蚀刻停止层和电介质层之间的起泡
公开(公告)号：US07732324B2
公开(公告)日：2010-06-08
申请号：US11961464
申请日：2007-12-20
申请人： Ju-Ai Ruan , Sameer K. Ajmera , Changming Jin , Anand J. Reddy , Tae S. Kim
发明人： Ju-Ai Ruan , Sameer K. Ajmera , Changming Jin , Anand J. Reddy , Tae S. Kim
IPC分类号： H01L21/469
CPC分类号： H01L23/53295 , H01L21/76832 , H01L21/76834 , H01L23/5222 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： One aspect of the invention provides a method of forming a semiconductor device (100). One aspect includes forming transistors (120, 125) on a semiconductor substrate (105), forming a first interlevel dielectric layer (165) over the transistors (120, 125), and forming metal interconnects (170, 175) within the first interlevel dielectric layer (165). A carbon-containing gas is used to form a silicon carbon nitride (SiCN) layer (180) over the metal interconnects (170, 175) and the first interlevel dielectric layer (165) within a deposition tool. An adhesion layer (185) is formed on the SiCN layer (180), within the deposition tool, by discontinuing a flow of the carbon-containing gas within the deposition chamber. A second interlevel dielectric layer (190) is formed over the adhesion layer (185).
摘要翻译：本发明的一个方面提供了形成半导体器件（100）的方法。一个方面包括在半导体衬底（105）上形成晶体管（120,125），在晶体管（120,125）之上形成第一层间电介质层（165），并在第一层间电介质内形成金属互连（170,175）层（165）。使用含碳气体在沉积工具内的金属互连（170,175）和第一层间介电层（165）上形成氮化硅（SiCN）层（180）。通过中断沉积室内的含碳气体的流动，在沉积工具内在SiCN层（180）上形成粘附层（185）。第二层间介质层（190）形成在粘合层（185）上方。

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