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11. 发明授权

US08984379B2 MRAM field disturb detection and recovery 有权
标题翻译： MRAM场干扰检测和恢复
公开(公告)号：US08984379B2
公开(公告)日：2015-03-17
申请号：US13484509
申请日：2012-05-31
申请人： Thomas Andre , Syed M. Alam , Bradley Engel , Brian Butcher
发明人： Thomas Andre , Syed M. Alam , Bradley Engel , Brian Butcher
IPC分类号： H03M13/00 , G06F11/00 , G06F11/10 , G11C29/44 , H03M13/11
CPC分类号： G06F11/1048 , G11C29/44 , H03M13/11
摘要： A method and memory device is provided for reading data from an ECC word of a plurality of reference bits associated with a plurality of memory device bits and determining if a double bit error in the ECC word exists. The ECC word may be first toggled twice and the reference bits reset upon detecting the double bit error.
摘要翻译：提供一种方法和存储装置，用于从与多个存储器件位相关联的多个参考位的ECC字中读取数据，并确定是否存在ECC字中的双位错误。 ECC字可以首先切换两次，并且在检测到双位错误时参考位复位。

12. 发明申请

US20150019806A1 MEMORY DEVICE WITH PAGE EMULATION MODE 有权
标题翻译：具有页面模拟模式的存储器件
公开(公告)号：US20150019806A1
公开(公告)日：2015-01-15
申请号：US14155816
申请日：2014-01-15
申请人： Syed M. Alam , Thomas Andre
发明人： Syed M. Alam , Thomas Andre
IPC分类号： G06F12/08
CPC分类号： G06F11/1096 , G06F11/1064 , G06F12/0882 , G06F2211/109 , G06F2212/652 , G11C14/0036
摘要： In some examples, a memory device is configured to load multiple pages of an internal page size into a cache in response to receiving an activate command and to write multiple pages of the internal page size into a memory array in response to receiving a precharge command. In some implementations, the memory array is arranged to store multiple pages of the internal page size in a single physical row.
摘要翻译：在一些示例中，存储器设备被配置为响应于接收到激活命令而将内部页面大小的页面加载到高速缓存中，并且响应于接收到预充电命令而将内部页面大小的多页写入存储器阵列。在一些实现中，存储器阵列被布置成在单个物理行中存储内部页面大小的多个页面。

13. 发明授权

US07723207B2 Three dimensional integrated circuit and method of design 失效
标题翻译：三维集成电路及设计方法
公开(公告)号：US07723207B2
公开(公告)日：2010-05-25
申请号：US11737598
申请日：2007-04-19
申请人： Syed M. Alam , Ibrahim M. Elfadel , Kathryn W Guarini , Meikei Ieong , Prabhakar N. Kudva , David S. Kung , Mark A. Lavin , Arifur Rahman
发明人： Syed M. Alam , Ibrahim M. Elfadel , Kathryn W Guarini , Meikei Ieong , Prabhakar N. Kudva , David S. Kung , Mark A. Lavin , Arifur Rahman
IPC分类号： H01L21/30
CPC分类号： H01L27/0688 , H01L21/2007 , H01L21/84 , H01L27/1203
摘要： A three dimensional (3D) integrated circuit (IC), 3D IC chip and method of fabricating a 3D IC chip. The chip includes multiple layers of circuits, e.g., silicon insulator (SOI) CMOS IC layers, each including circuit elements. The layers may be formed in parallel and one layer attached to another to form a laminated 3D chip.
摘要翻译：三维（3D）集成电路（IC），3D IC芯片和3D IC芯片的制造方法。该芯片包括多层电路，例如硅绝缘体（SOI）CMOS IC层，每层包括电路元件。这些层可以平行地形成，并且一层附着到另一层以形成层叠的3D芯片。

14. 发明申请

US20090086524A1 PROGRAMMABLE ROM USING TWO BONDED STRATA AND METHOD OF OPERATION 有权
标题翻译：可编程ROM使用两个绑定的条纹和操作方法
公开(公告)号：US20090086524A1
公开(公告)日：2009-04-02
申请号：US11865991
申请日：2007-10-02
申请人： Syed M. Alam , Robert E. Jones
发明人： Syed M. Alam , Robert E. Jones
IPC分类号： G11C17/00 , H01S4/00
CPC分类号： G11C17/14 , H01L25/18 , H01L27/112 , H01L27/11226 , H01L2225/06513 , H01L2225/06527 , H01L2924/0002 , Y10T29/49002 , H01L2924/00
摘要： A read only memory implemented as a 3D integrated device has a first stratum, a second stratum, and bonded inter-strata connections for coupling the first stratum to the second stratum. The physical bonding between the two strata implements the programming of the read only memory. The stratum may be in wafer form or in die form. The first stratum includes functional active devices and at least one non-programmed active device. The second stratum includes at least conductive routing to be associated with the at least one non-programmed active device. The bonded inter-strata connections include at least one bonded programmable inter-strata connection for programming the at least one non-programmed active device and for providing conductive routing to the programmed active device. The two strata thus form a programmed ROM. Other types of programmable storage devices may be implemented by bonding the two strata.
摘要翻译：实现为3D集成设备的只读存储器具有用于将第一层耦合到第二层的第一层，第二层和粘结层间连接。两层之间的物理绑定实现了只读存储器的编程。层可以是晶片形式或模具形式。第一层包括功能性有源器件和至少一个非编程有源器件。第二层包括至少与至少一个非编程的有源设备相关联的导电路由。所述接合的层间连接包括用于对所述至少一个非编程的有源器件进行编程以及为所述编程的有源器件提供导电路由的至少一个结合的可编程层间连接。因此，这两个层由此形成一个编程的ROM。其他类型的可编程存储设备可以通过键合两个层来实现。

15. 发明申请

US20080113505A1 METHOD OF FORMING A THROUGH-SUBSTRATE VIA 审中-公开
标题翻译：形成通过基底的方法
公开(公告)号：US20080113505A1
公开(公告)日：2008-05-15
申请号：US11558988
申请日：2006-11-13
申请人： Terry G. Sparks , Syed M. Alam , Ritwik Chatterjee , Shahid Rauf
发明人： Terry G. Sparks , Syed M. Alam , Ritwik Chatterjee , Shahid Rauf
IPC分类号： H01L21/768
CPC分类号： H01L21/76898 , H01L23/481 , H01L2924/0002 , H01L2924/00
摘要： A method for achieving a through-substrate via through a substrate having active circuitry on a first major surface begins by forming a hole into the substrate through the first major surface. The hole is lined with a conductive layer. A dielectric layer is deposited over the conductive layer. This deposition is performed in a manner that causes the dielectric layer to be substantially conformal. Conductive material is formed over first dielectric layer. A second major surface of the substrate is etched to expose the conductive material.
摘要翻译：通过在第一主表面上具有有源电路的基板实现贯通基板通孔的方法首先通过第一主表面在基板中形成孔。孔内衬有导电层。介电层沉积在导电层上。这种沉积以使介电层基本上保形的方式进行。导电材料形成在第一介电层上。蚀刻衬底的第二主表面以暴露导电材料。

16. 发明授权

US07715227B2 Programmable ROM using two bonded strata 有权
标题翻译：可编程ROM使用两个粘结层
公开(公告)号：US07715227B2
公开(公告)日：2010-05-11
申请号：US11865991
申请日：2007-10-02
申请人： Syed M. Alam , Robert E. Jones
发明人： Syed M. Alam , Robert E. Jones
IPC分类号： G11C11/50
CPC分类号： G11C17/14 , H01L25/18 , H01L27/112 , H01L27/11226 , H01L2225/06513 , H01L2225/06527 , H01L2924/0002 , Y10T29/49002 , H01L2924/00
摘要： A read only memory implemented as a 3D integrated device has a first stratum, a second stratum, and bonded inter-strata connections for coupling the first stratum to the second stratum. The physical bonding between the two strata implements the programming of the read only memory. The stratum may be in wafer form or in die form. The first stratum includes functional active devices and at least one non-programmed active device. The second stratum includes at least conductive routing to be associated with the at least one non-programmed active device. The bonded inter-strata connections include at least one bonded programmable inter-strata connection for programming the at least one non-programmed active device and for providing conductive routing to the programmed active device. The two strata thus form a programmed ROM. Other types of programmable storage devices may be implemented by bonding the two strata.
摘要翻译：实现为3D集成设备的只读存储器具有用于将第一层耦合到第二层的第一层，第二层和粘结层间连接。两层之间的物理绑定实现了只读存储器的编程。层可以是晶片形式或模具形式。第一层包括功能性有源器件和至少一个非编程有源器件。第二层包括至少与至少一个非编程的有源设备相关联的导电路由。所述接合的层间连接包括用于对所述至少一个非编程的有源器件进行编程以及为所述编程的有源器件提供导电路由的至少一个结合的可编程层间连接。因此，这两个层由此形成一个编程的ROM。其他类型的可编程存储设备可以通过键合两个层来实现。

17. 发明申请

US20140073133A1 METHOD TO MITIGATE THROUGH-SILICON VIA-INDUCED SUBSTRATE NOISE 审中-公开
标题翻译：通过硅氧化膜消除基底噪声的方法
公开(公告)号：US20140073133A1
公开(公告)日：2014-03-13
申请号：US14004472
申请日：2012-03-14
申请人： Nauman H. Kahn , Soha Hassoun , Syed M. Alam
发明人： Nauman H. Kahn , Soha Hassoun , Syed M. Alam
IPC分类号： H01L21/768
CPC分类号： H01L21/768 , H01L23/481 , H01L23/552 , H01L23/585 , H01L25/0657 , H01L2224/16 , H01L2225/06513 , H01L2225/06517 , H01L2225/06544 , H01L2924/13091 , H01L2924/00
摘要： A semiconductor manufacture includes a first semiconductor including a substrate die having a first surface and having a second surface upon which integrated circuitry is disposed; a second semiconductor die; a through-silicon via (TSV) extending through the first semiconductor die and electrically connected to the second semiconductor die; and at least one ground plug including an electrically conductive material, positioned proximally to the TSV and extending into the substrate of the first semiconductor die from one of the first surface or the second surface.
摘要翻译：半导体制造包括：第一半导体，包括具有第一表面并具有第二表面的衬底管芯，集成电路设置在第二表面上; 第二半导体管芯; 穿过所述第一半导体管芯并且电连接到所述第二半导体管芯的穿硅通孔（TSV）; 以及包括导电材料的至少一个接地插头，位于TSV的近侧并从第一表面或第二表面中的一个延伸到第一半导体管芯的衬底中。

18. 发明申请

US20130301346A1 SELF REFERENCING SENSE AMPLIFIER FOR SPIN TORQUE MRAM 有权
标题翻译：自适应感应放大器用于旋转扭矩MRAM
公开(公告)号：US20130301346A1
公开(公告)日：2013-11-14
申请号：US13872993
申请日：2013-04-29
申请人： Chitra K. Subramanian , Syed M. Alam
发明人： Chitra K. Subramanian , Syed M. Alam
IPC分类号： G11C11/16
CPC分类号： G11C11/1673
摘要： Circuitry and a method provide self-referenced sensing of a resistive memory cell by using its characteristic of resistance variation with applied voltage in one state versus a relatively constant resistance regardless of the applied voltage in its opposite state. Based on an initial bias state with equalized resistances, a current comparison at a second bias state between a mock bit line and a bit line is used to determine the state of the memory cell, since a significant difference in current implies that the memory cell state has a significant voltage coefficient of resistance. An offset current applied to the mock bit line optionally may be used to provide symmetry and greater sensing margin.
摘要翻译：电路和方法通过使用其在一个状态下的施加电压与相对恒定电阻的电阻变化的特性来提供电阻式存储器单元的自参考感测，而不管其相反状态下的施加电压如何。基于具有均衡电阻的初始偏置状态，使用模拟位线和位线之间的第二偏置状态下的电流比较来确定存储器单元的状态，因为电流的显着差异意味着存储单元状态具有显着的电阻系数。施加到模拟位线的偏移电流可选地可以用于提供对称性和更大的感测余量。

19. 发明授权

US07358616B2 Semiconductor stacked die/wafer configuration and packaging and method thereof 有权
标题翻译：半导体堆叠晶片/晶片配置及其封装及其方法
公开(公告)号：US07358616B2
公开(公告)日：2008-04-15
申请号：US11226025
申请日：2005-09-14
申请人： Syed M. Alam , Robert E. Jones , Scott K. Pozder
发明人： Syed M. Alam , Robert E. Jones , Scott K. Pozder
IPC分类号： H01L23/48
CPC分类号： H01L25/0657 , H01L2224/16145 , H01L2225/06513 , H01L2225/06527 , H01L2225/06541
摘要： A reciprocal design symmetry allows stacked wafers or die on wafer to use identical designs or designs that vary only by a few layers (e.g. metal interconnect layers). Flipping or rotating one die or wafer allows the stacked die to have a reciprocal orientation with respect to each other which may be used to decrease the interconnect required between the vertically stacked die and or wafers. Flipping and/or rotating may also be used to improve heat dissipation when wafer and/or die are stacked. The stacked wafers or die may then be packaged.
摘要翻译：互易设计对称性允许晶片上的堆叠晶片或晶片使用仅仅几层（例如，金属互连层）变化的相同设计或设计。翻转或旋转一个模具或晶片允许堆叠的模具相对于彼此具有相互的取向，其可用于减小垂直堆叠的模具和/或晶片之间所需的互连。当晶片和/或管芯堆叠时，翻转和/或旋转也可用于改善散热。然后可以包装堆叠的晶片或管芯。

20. 发明授权

US07312487B2 Three dimensional integrated circuit 有权
标题翻译：三维集成电路
公开(公告)号：US07312487B2
公开(公告)日：2007-12-25
申请号：US10919121
申请日：2004-08-16
申请人： Syed M. Alam , Ibrahim M. Elfadel , Kathryn W. Guarini , Meikei Ieong , Prabhakar N. Kudva , David S. Kung , Mark A. Lavin , Arifur Rahman
发明人： Syed M. Alam , Ibrahim M. Elfadel , Kathryn W. Guarini , Meikei Ieong , Prabhakar N. Kudva , David S. Kung , Mark A. Lavin , Arifur Rahman
IPC分类号： H01L29/80
CPC分类号： H01L27/0688 , H01L21/2007 , H01L21/84 , H01L27/1203
摘要： A three dimensional (3D) integrated circuit (IC), 3D IC chip and method of fabricating a 3D IC chip. The chip includes multiple layers of circuits, e.g., silicon insulator (SOI) CMOS IC layers, each including circuit elements. The layers may be formed in parallel and one layer attached to another to form a laminated 3D chip.
摘要翻译：三维（3D）集成电路（IC），3D IC芯片和3D IC芯片的制造方法。该芯片包括多层电路，例如硅绝缘体（SOI）CMOS IC层，每层包括电路元件。这些层可以平行地形成，并且一层附着到另一层以形成层叠的3D芯片。

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