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11. 发明申请

US20070111463A1 STRAINED SILICON-ON-INSULATOR BY ANODIZATION OF A BURIED p+ SILICON GERMANIUM LAYER 失效
标题翻译：通过阳极氧化P +硅锗层的分级制备的绝缘硅绝缘体
公开(公告)号：US20070111463A1
公开(公告)日：2007-05-17
申请号：US11620663
申请日：2007-01-06
申请人： Thomas Adam , Stephen Bedell , Joel de Souza , Keith Fogel , Alexander Reznicek , Devendra Sadana , Ghavam Shahidi
发明人： Thomas Adam , Stephen Bedell , Joel de Souza , Keith Fogel , Alexander Reznicek , Devendra Sadana , Ghavam Shahidi
IPC分类号： H01L21/337 , H01L27/12 , H01L21/76
CPC分类号： H01L21/76259 , Y10S438/967
摘要： A cost efficient and manufacturable method of fabricating strained semiconductor-on-insulator (SSOI) substrates is provided that avoids wafer bonding. The method includes growing various epitaxial semiconductor layers on a substrate, wherein at least one of the semiconductor layers is a doped and relaxed semiconductor layer underneath a strained semiconductor layer; converting the doped and relaxed semiconductor layer into a porous semiconductor via an electrolytic anodization process, and oxidizing to convert the porous semiconductor layer into a buried oxide layer. The method provides a SSOI substrate that includes a relaxed semiconductor layer on a substrate; a high-quality buried oxide layer on the relaxed semiconductor layer; and a strained semiconductor layer on the high-quality buried oxide layer. In accordance with the present invention, the relaxed semiconductor layer and the strained semiconductor layer have identical crystallographic orientations.
摘要翻译：提供了制造应变半导体绝缘体（SSOI）衬底的成本有效和可制造的方法，其避免晶片接合。该方法包括在衬底上生长各种外延半导体层，其中半导体层中的至少一个是在应变半导体层下面的掺杂和弛豫半导体层; 通过电解阳极氧化处理将掺杂和松弛的半导体层转化成多孔半导体，并氧化以将多孔半导体层转化为掩埋氧化物层。该方法提供了在衬底上包括松弛半导体层的SSOI衬底; 在松弛的半导体层上形成高质量的掩埋氧化物层; 以及在高质量掩埋氧化物层上的应变半导体层。根据本发明，松弛半导体层和应变半导体层具有相同的晶体取向。

12. 发明申请

US20060030133A1 Relaxed, low-defect SGOI for strained Si CMOS applications 有权
标题翻译：用于应变Si CMOS应用的轻松，低缺陷SGOI
公开(公告)号：US20060030133A1
公开(公告)日：2006-02-09
申请号：US11208359
申请日：2005-08-19
申请人： Paul Agnello , Stephen Bedell , Robert Dennard , Anthony Domenicucci , Keith Fogel , Devendra Sadana
发明人： Paul Agnello , Stephen Bedell , Robert Dennard , Anthony Domenicucci , Keith Fogel , Devendra Sadana
IPC分类号： H01L21/20 , H01L33/00 , H01L21/36
CPC分类号： H01L21/324 , C30B25/02 , C30B29/52 , H01L21/02378 , H01L21/02381 , H01L21/02532 , H01L21/02664 , H01L21/7624 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L29/66893 , H01L29/78603
摘要： Thermal mixing methods of forming a substantially relaxed and low-defect SGOI substrate material are provided. The methods include a patterning step which is used to form a structure containing at least SiGe islands formed atop a Ge resistant diffusion barrier layer. Patterning of the SiGe layer into islands changes the local forces acting at each of the island edges in such a way so that the relaxation force is greater than the forces that oppose relaxation. The absence of restoring forces at the edges of the patterned layers allows the final SiGe film to relax further than it would if the film was continuous.
摘要翻译：提供形成基本上松弛和低缺陷的SGOI基底材料的热混合方法。所述方法包括图形化步骤，其用于形成至少包含形成在Ge抗蚀扩散阻挡层顶上的SiGe岛的结构。将SiGe层图案化成岛以这样的方式改变作用在每个岛边缘处的局部力，使得松弛力大于抵抗放松的力。在图案化层的边缘处没有恢复力允许最终的SiGe膜比如果膜是连续的那样进一步松弛。

13. 发明申请

US20060001089A1 ULTRA-THIN, HIGH QUALITY STRAINED SILICON-ON-INSULATOR FORMED BY ELASTIC STRAIN TRANSFER 失效
标题翻译：超薄薄膜，高品质应变硅橡胶绝缘子，由弹性应变转移
公开(公告)号：US20060001089A1
公开(公告)日：2006-01-05
申请号：US10883883
申请日：2004-07-02
申请人： Stephen Bedell , Anthony Domenicucci , Keith Fogel , Effendi Leobandung , Devendra Sadana
发明人： Stephen Bedell , Anthony Domenicucci , Keith Fogel , Effendi Leobandung , Devendra Sadana
IPC分类号： H01L31/0392 , H01L21/84
CPC分类号： H01L29/78696 , H01L21/0237 , H01L21/02439 , H01L21/02488 , H01L21/02502 , H01L21/02521 , H01L21/02667 , H01L21/02694 , H01L21/76251 , H01L29/7842
摘要： A method of forming a semiconductor structure comprising a first strained semiconductor layer over an insulating layer is provided in which the first strained semiconductor layer is relatively thin (less than about 500 Å) and has a low defect density (stacking faults and threading defects). The method of the present invention begins with forming a stress-providing layer, such a SiGe alloy layer over a structure comprising a first semiconductor layer that is located atop an insulating layer. The stress-providing layer and the first semiconductor layer are then patterned into at least one island and thereafter the structure containing the at least one island is heated to a temperature that causes strain transfer from the stress-providing layer to the first semiconductor layer. After strain transfer, the stress-providing layer is removed from the structure to form a first strained semiconductor island layer directly atop said insulating layer.
摘要翻译：提供了一种在绝缘层上形成包括第一应变半导体层的半导体结构的方法，其中第一应变半导体层相对较薄（小于约）并且具有低缺陷密度（堆垛层错和穿线缺陷）。本发明的方法开始于在包括位于绝缘层顶部的第一半导体层的结构上形成应力提供层，例如SiGe合金层。然后将应力提供层和第一半导体层图案化成至少一个岛，然后将含有至少一个岛的结构加热到使得应力转移从应力提供层到第一半导体层的温度。在应变转移之后，将应力提供层从结构上去除，以形成直接位于所述绝缘层顶部的第一应变半导体岛层。

14. 发明申请

US20050153487A1 Formation of silicon-germanium-on-insulator (SGOI) by an integral high temperature simox-Ge interdiffusion anneal 失效
标题翻译：通过整体高温simox-Ge相互扩散退火形成绝缘体上硅锗（SGOI）
公开(公告)号：US20050153487A1
公开(公告)日：2005-07-14
申请号：US11039602
申请日：2005-01-19
申请人： Stephen Bedell , Joel de Souza , Keith Fogel , Devendra Sadana , Ghavam Shahidi
发明人： Stephen Bedell , Joel de Souza , Keith Fogel , Devendra Sadana , Ghavam Shahidi
IPC分类号： H01L27/08 , H01L21/02 , H01L21/20 , H01L21/265 , H01L21/762 , H01L27/12 , H01L21/00
CPC分类号： H01L21/76243 , H01L21/26506 , H01L21/76267 , Y10T428/12674 , Y10T428/12681
摘要： A method of forming a substantially relaxed, high-quality SiGe-on-insulator substrate material using SIMOX and Ge interdiffusion is provided. The method includes first implanting ions into a Si-containing substrate to form an implanted-ion rich region in the Si-containing substrate. The implanted-ion rich region has a sufficient ion concentration such that during a subsequent anneal at high temperatures a barrier layer that is resistant to Ge diffusion is formed. Next, a Ge-containing layer is formed on a surface of the Si-containing substrate, and thereafter a heating step is performed at a temperature which permits formation of the barrier layer and interdiffusion of Ge thereby forming a substantially relaxed, single crystal SiGe layer atop the barrier layer.
摘要翻译：提供了使用SIMOX和Ge相互扩散形成基本上松弛的，优质的绝缘体上硅衬底材料的方法。该方法包括首先将离子注入到含Si衬底中以在含Si衬底中形成植入离子富集区。注入离子富集区具有足够的离子浓度，使得在随后的高温退火期间形成耐Ge扩散的阻挡层。接下来，在含Si衬底的表面上形成Ge含有层，然后在允许形成阻挡层和Ge的相互扩散的温度下进行加热步骤，从而形成基本上松弛的单晶SiGe层阻挡层顶部。

15. 发明申请

US20050056352A1 Formation of a silicon germanium-on-insulator structure by oxidation of a buried porous silicon layer 失效
标题翻译：通过掩埋多孔硅层的氧化形成绝缘体上硅结构的结构
公开(公告)号：US20050056352A1
公开(公告)日：2005-03-17
申请号：US10662028
申请日：2003-09-12
申请人： Stephen Bedell , Kwang Choe , Keith Fogel , Devendra Sadana
发明人： Stephen Bedell , Kwang Choe , Keith Fogel , Devendra Sadana
IPC分类号： C22F1/10 , H01L21/20 , H01L21/762 , C22F1/00
CPC分类号： H01L21/76227 , C22F1/10 , H01L21/02378 , H01L21/02381 , H01L21/0245 , H01L21/02532 , H01L21/02667 , H01L21/76245 , H01L29/78603
摘要： A simple and direct method of forming a SiGe-on-insulator that relies on the oxidation of a porous silicon layer (or region) that is created beneath a Ge-containing layer is provided. The method includes the steps of providing a structure comprising a Si-containing substrate having a hole-rich region formed therein and a Ge-containing layer atop the Si-containing substrate; converting the hole-rich region into a porous region; and annealing the structure including the porous region to provide a substantially relaxed SiGe-on-insulator material.
摘要翻译：提供一种形成依赖于在含Ge层下形成的多孔硅层（或区域）的氧化的绝缘体上硅的简单且直接的方法。该方法包括以下步骤：提供包括其中形成有富空穴的含Si衬底和含Si衬底顶部的含Ge层的结构; 将富含孔的区域转化为多孔区域; 并退火包括多孔区域的结构，以提供基本上松弛的绝缘体上的SiGe。

16. 发明授权

US07935612B1 Layer transfer using boron-doped SiGe layer 有权
标题翻译：使用硼掺杂的SiGe层进行层转移
公开(公告)号：US07935612B1
公开(公告)日：2011-05-03
申请号：US12700801
申请日：2010-02-05
申请人： Stephen Bedell , Keith Fogel , Daniel Inns , Jeehwan Kim , Devendra Sadana , James Vichiconti
发明人： Stephen Bedell , Keith Fogel , Daniel Inns , Jeehwan Kim , Devendra Sadana , James Vichiconti
IPC分类号： H01L21/30 , H01L21/02
CPC分类号： H01L21/187
摘要： A method for layer transfer using a boron-doped silicon germanium (SiGe) layer includes forming a boron-doped SiGe layer on a bulk silicon substrate; forming an upper silicon (Si) layer over the boron-doped SiGe layer; hydrogenating the boron-doped SiGe layer; bonding the upper Si layer to an alternate substrate; and propagating a fracture at an interface between the boron-doped SiGe layer and the bulk silicon substrate. A system for layer transfer using a boron-doped silicon germanium (SiGe) layer includes a bulk silicon substrate; a boron-doped SiGe layer formed on the bulk silicon substrate, such that the boron-doped SiGe layer is located underneath an upper silicon (Si) layer, wherein the boron-doped SiGe layer is configured to propagate a fracture at an interface between the boron-doped SiGe layer and the bulk silicon substrate after hydrogenation of the boron-doped SiGe layer; and an alternate substrate bonded to the upper Si layer.
摘要翻译：使用硼掺杂硅锗（SiGe）层进行层转移的方法包括在体硅衬底上形成硼掺杂的SiGe层; 在掺杂硼的SiGe层上形成上硅（Si）层; 氢化硼掺杂的SiGe层; 将上部Si层结合到替代的基底上; 并在硼掺杂的SiGe层和体硅衬底之间的界面处传播断裂。使用硼掺杂硅锗（SiGe）层的层转移系统包括体硅衬底; 形成在本体硅衬底上的硼掺杂SiGe层，使得掺杂硼的SiGe层位于上硅（Si）层的下方，其中掺硼的SiGe层被配置为在硼掺杂的SiGe层和硼硅掺杂SiGe层氢化后的体硅衬底; 以及与上部Si层接合的替代基板。

17. 发明申请

US20060027808A1 METHOD OF FORMING STRAINED SILICON MATERIALS WITH IMPROVED THERMAL CONDUCTIVITY 有权
标题翻译：形成具有改善的导热性的应变硅材料的方法
公开(公告)号：US20060027808A1
公开(公告)日：2006-02-09
申请号：US10710826
申请日：2004-08-05
申请人： Stephen Bedell , Huajie Chen , Keith Fogel , Ryan Mitchell , Devendra Sadana
发明人： Stephen Bedell , Huajie Chen , Keith Fogel , Ryan Mitchell , Devendra Sadana
IPC分类号： H01L29/12 , H01L21/20
CPC分类号： H01L29/1054 , H01L21/02381 , H01L21/0245 , H01L21/02507 , H01L21/02532
摘要： A method is disclosed for forming a strained Si layer on SiGe, where the SiGe layer has improved thermal conductivity. A first layer of Si or Ge is deposited on a substrate in a first depositing step; a second layer of the other element is deposited on the first layer in a second depositing step; and the first and second depositing steps are repeated so as to form a combined SiGe layer having a plurality of Si layers and a plurality of Ge layers. The respective thicknesses of the Si layers and Ge layers are in accordance with a desired composition ratio of the combined SiGe layer (so that a 1:1 ratio typically is realized with Si and Ge layers each about 10 Å thick). The combined SiGe layer is characterized as a digital alloy of Si and Ge having a thermal conductivity greater than that of a random alloy of Si and Ge. This method may further include the step of depositing a Si layer on the combined SiGe layer; the combined SiGe layer is characterized as a relaxed SiGe layer, and the Si layer is a strained Si layer. For still greater thermal conductivity in the SiGe layer, the first layer and second layer may be deposited so that each layer consists essentially of a single isotope.
摘要翻译：公开了一种在SiGe上形成应变Si层的方法，其中SiGe层具有改善的导热性。在第一沉积步骤中将第一层Si或Ge沉积在衬底上; 另一个元件的第二层在第二沉积步骤中沉积在第一层上; 并且重复第一和第二沉积步骤以形成具有多个Si层和多个Ge层的组合SiGe层。 Si层和Ge层的各自的厚度根据组合的SiGe层的期望组成比（使得Si和Ge层的厚度通常为1：1，每个厚度大约为10埃）。组合的SiGe层的特征在于具有大于Si和Ge的随机合金的热导率的Si和Ge的数字合金。该方法还可以包括在组合的SiGe层上沉积Si层的步骤; 组合的SiGe层被表征为弛豫的SiGe层，并且Si层是应变的Si层。对于SiGe层中更高的热导率，可以沉积第一层和第二层，使得每层基本上由单一同位素组成。

18. 发明申请

US20060011906A1 Ion implantation for suppression of defects in annealed SiGe layers 审中-公开
标题翻译：用于抑制退火SiGe层缺陷的离子注入
公开(公告)号：US20060011906A1
公开(公告)日：2006-01-19
申请号：US10890765
申请日：2004-07-14
申请人： Stephen Bedell , Huajie Chen , Keith Fogel , Devendra Sadana , Ghavam Shahidi
发明人： Stephen Bedell , Huajie Chen , Keith Fogel , Devendra Sadana , Ghavam Shahidi
IPC分类号： H01L29/06
CPC分类号： H01L21/26506 , H01L21/02381 , H01L21/02532 , H01L21/02694 , H01L21/2658
摘要： A method for fabricating substantially relaxed SiGe alloy layers with a reduced planar defect density is disclosed. The method of the present invention includes forming a strained Ge-containing layer on a surface of a Si-containing substrate; implanting ions at or below the Ge-containing layer/Si-containing substrate interface and heating to form a substantially relaxed SiGe alloy layer that has a reduced planar defect density. A substantially relaxed SiGe-on-insulator substrate material having a SiGe layer with a reduced planar defect density as well as heterostructures containing the same are also provided.
摘要翻译：公开了一种用于制造具有减小的平面缺陷密度的基本上松弛的SiGe合金层的方法。本发明的方法包括在含Si基材的表面上形成应变的含Ge层; 在含锗层/含Si衬底界面处或下方注入离子，并加热以形成具有减小的平面缺陷密度的基本上松弛的SiGe合金层。还提供了具有具有减小的平面缺陷密度的SiGe层以及含有该SiGe层的异质结构的基本上松弛的绝缘体上硅衬底材料。

19. 发明申请

US20060003555A1 Strained silicon-on-insulator by anodization of a buried p+ silicon germanium layer 有权
公开(公告)号：US20060003555A1
公开(公告)日：2006-01-05
申请号：US10883887
申请日：2004-07-02
申请人： Thomas Adam , Stephen Bedell , Joel de Souza , Keith Fogel , Alexander Reznicek , Devendra Sadana , Ghavam Shahidi
发明人： Thomas Adam , Stephen Bedell , Joel de Souza , Keith Fogel , Alexander Reznicek , Devendra Sadana , Ghavam Shahidi
IPC分类号： H01L31/0328 , H01L31/0336 , H01L31/072 , H01L31/109 , C30B1/00 , H01L21/20 , H01L21/36
CPC分类号： H01L21/76259 , Y10S438/967
摘要： A cost efficient and manufacturable method of fabricating strained semiconductor-on-insulator (SSOI) substrates is provided that avoids wafer bonding. The method includes growing various epitaxial semiconductor layers on a substrate, wherein at least one of the semiconductor layers is a doped and relaxed semiconductor layer underneath a strained semiconductor layer; converting the doped and relaxed semiconductor layer into a porous semiconductor via an electrolytic anodization process, and oxidizing to convert the porous semiconductor layer into a buried oxide layer. The method provides a SSOI substrate that includes a relaxed semiconductor layer on a substrate; a high-quality buried oxide layer on the relaxed semiconductor layer; and a strained semiconductor layer on the high-quality buried oxide layer. In accordance with the present invention, the relaxed semiconductor layer and the strained semiconductor layer have identical crystallographic orientations.

20. 发明申请

US20050221591A1 Method of forming high-quality relaxed SiGe alloy layers on bulk Si substrates 审中-公开
标题翻译：在大量Si衬底上形成高品质的松弛SiGe合金层的方法
公开(公告)号：US20050221591A1
公开(公告)日：2005-10-06
申请号：US10818572
申请日：2004-04-06
申请人： Stephen Bedell , Huajie Chen , Joel de Souza , Keith Fogel , Devendra Sadana , Ghavam Shahidi
发明人： Stephen Bedell , Huajie Chen , Joel de Souza , Keith Fogel , Devendra Sadana , Ghavam Shahidi
IPC分类号： C30B1/00 , H01L21/20 , H01L21/3063 , H01L21/36 , H01L31/0328 , H01L31/0336 , H01L31/072 , H01L31/109
CPC分类号： H01L21/3063 , H01L21/02381 , H01L21/0245 , H01L21/02513 , H01L21/02532 , H01L21/02658
摘要： A method of forming a high-quality relaxed SiGe alloy layer on a bulk Si-containing substrate is provided. The method of the present invention includes growing a strained SiGe alloy layer on a Si-containing substrate that has a porous Si-containing layer at or near the surface of the Si-containing substrate. The porous layer is formed by an electrolytic anodization process. The pores create free volume below the strained SiGe layer which can serve to accommodate strain relaxation during SiGe deposition or a subsequent heating step. The subsequent heating step is optional and is performed to further increase the relaxation of the SiGe alloy layer. The buried porous structure allows for a unique relaxation mechanism compared to prior art methods.
摘要翻译：提供了在体积含Si衬底上形成高品质的弛豫SiGe合金层的方法。本发明的方法包括在含Si衬底上生长应变SiGe合金层，该Si基合金层在含Si衬底的表面处或附近具有多孔含Si层。多孔层通过电解阳极氧化处理形成。孔隙在应变SiGe层之下产生自由体积，其可用于在SiGe沉积或随后的加热步骤期间适应应变松弛。随后的加热步骤是可选的并且进行以进一步增加SiGe合金层的松弛。与现有技术方法相比，埋入的多孔结构允许独特的松弛机制。

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