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11. 发明申请

US20090206469A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件及制造半导体器件的方法
公开(公告)号：US20090206469A1
公开(公告)日：2009-08-20
申请号：US12369456
申请日：2009-02-11
申请人： Takanori MAEBASHI , Nobuaki Miyakawa
发明人： Takanori MAEBASHI , Nobuaki Miyakawa
IPC分类号： H01L23/538 , H01L21/98
CPC分类号： H01L23/481 , H01L21/6835 , H01L21/6836 , H01L21/76898 , H01L25/50 , H01L2221/68327 , H01L2221/6834 , H01L2224/05001 , H01L2224/11 , H01L2224/13 , H01L2224/13009 , H01L2224/13022 , H01L2224/16 , H01L2224/16146 , H01L2225/06513 , H01L2225/06541 , H01L2225/06555 , H01L2225/06575 , H01L2924/1305 , H01L2924/13091 , H01L2924/19041 , H01L2924/00
摘要： A semiconductor device has a plurality of wafers which are laminated to each other, wherein: each wafer includes an lamination surface to which another wafer is laminated and a substrate having an element formed thereon; the lamination surface is provided with an electric signal connecting portion that electrically connects to said another wafer so as to form a semiconductor circuit; at least one of the electrical signal connecting portions facing each other is a protruding connection portion that protrudes from a region which exposes the substrate on the lamination surface; and a reinforcing protruding portion that is insulated from the semiconductor circuit, and is formed of the same material as the substrate to protrude from the lamination surface with a height equal to the length of a gap between the lamination surfaces of wafers facing each other is provided in an area where the protruding connection portion is not disposed on the lamination surface formed with the protruding connection portion.
摘要翻译：半导体器件具有彼此层叠的多个晶片，其中：每个晶片包括层叠另一晶片的层叠表面和形成有元件的衬底; 层叠表面设置有电连接到所述另一晶片的电信号连接部分，以形成半导体电路; 电信号连接部中的至少一个彼此面对的是突出的连接部，其从层叠面上露出基板的区域突出; 和与半导体电路绝缘的加强突出部分，并且由与层叠表面突出的相同材料形成，其高度等于彼此面对的晶片的层叠表面之间的间隙的长度在突起连接部未设置在形成有突出连接部的层叠面上的区域中。

12. 发明申请

US20090174080A1 SEMICONDUCTOR DEVICE 失效
标题翻译：半导体器件
公开(公告)号：US20090174080A1
公开(公告)日：2009-07-09
申请号：US12063606
申请日：2006-08-25
申请人： Toshio Saito , Satoshi Moriya , Morio Nakamura , Goichi Yokoyama , Tatsuyuki Saito , Nobuaki Miyakawa
发明人： Toshio Saito , Satoshi Moriya , Morio Nakamura , Goichi Yokoyama , Tatsuyuki Saito , Nobuaki Miyakawa
IPC分类号： H01L23/522
CPC分类号： H01L25/0657 , H01L21/763 , H01L21/76898 , H01L21/823871 , H01L21/823878 , H01L23/3128 , H01L23/481 , H01L24/45 , H01L24/48 , H01L25/50 , H01L27/0203 , H01L2224/45144 , H01L2224/48227 , H01L2224/48465 , H01L2225/0651 , H01L2225/06513 , H01L2924/00014 , H01L2924/01029 , H01L2924/01078 , H01L2924/01079 , H01L2924/04941 , H01L2924/13091 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/00 , H01L2224/05599 , H01L2924/00012
摘要： In order to improve the manufacturing yield of a semiconductor device having a three-dimensional structure in which a plurality of chips are stacked and attached to each other, the opening shape of each of conductive grooves (4A) formed in each chip (C2) obtained from a wafer (W2) is rectangular, and the number of the conductive grooves (4A) whose long-sides are directed in a Y direction and the number of the conductive grooves (4A) whose long-sides are directed in an X direction perpendicular to the Y direction are made to be approximately equal to each other number in the entire wafer (W2), whereby the film stress upon embedding of a conductive film into the interior of the conductive grooves is reduced, and generation of exfoliation and micro-cracks in the conductive film or warpage and cracks of the wafer (W2) are prevented.
摘要翻译：为了提高具有多个芯片彼此堆叠并附接的三维结构的半导体器件的制造成品，形成在每个芯片（C2）中的每个导电槽（4A）的开口形状获得从晶片（W2）的长方形的长方形的导体槽（4A）的长度方向的长度方向的数量和长边方向的X方向的导体槽的数量使整个晶片（W2）的Y方向大致相等，由此导电膜嵌入导电槽内的膜应力减小，剥离和微裂纹的产生导致膜或翘曲和晶片（W2）的裂纹被阻止。

13. 发明申请

US20090160050A1 SEMICONDUCTOR DEVICE MANUFACTURING METHOD, SEMICONDUCTOR DEVICE AND WAFER 有权
标题翻译：半导体器件制造方法，半导体器件和晶体管
公开(公告)号：US20090160050A1
公开(公告)日：2009-06-25
申请号：US12064762
申请日：2006-08-25
申请人： Nobuaki Miyakawa , Takanori Maebashi , Takahiro Kimura
发明人： Nobuaki Miyakawa , Takanori Maebashi , Takahiro Kimura
IPC分类号： H01L23/48 , H01L21/30
CPC分类号： H01L25/117 , H01L21/6835 , H01L21/76898 , H01L21/823475 , H01L21/823481 , H01L23/481 , H01L25/0657 , H01L25/50 , H01L2224/16145 , H01L2224/81139 , H01L2225/06513 , H01L2225/06524 , H01L2225/06527 , H01L2225/06541 , H01L2225/06582 , H01L2924/01019 , H01L2924/01037 , H01L2924/1305 , H01L2924/13091 , H01L2924/00
摘要： A deep isolation trench extending from the main surface of a substrate to a desired depth is formed on the substrate with an insulating film in buried in it to form a through isolation portion. Subsequently, after a MOSFET is formed on the main surface of the substrate, an interlayer insulating film is deposited on the main surface of the substrate. Then, a deep conduction trench extending from the upper surface of the interlayer insulating film to a depth within the thickness of the substrate is formed in a region surrounded by the through isolation portion. Subsequently, a conductive film is buried in the deep conduction trench to form through interconnect portion. Then, after the undersurface of the substrate is ground and polished to an extent not to expose the through isolation portion and the through interconnect portion, wet etching is performed to an extent to expose parts of the lower portion of each of the through isolation portion and the through interconnect portion.
摘要翻译：在衬底上形成有从衬底的主表面延伸到所需深度的深度隔离沟槽，其中埋置有绝缘膜以形成通过隔离部分。随后，在衬底的主表面上形成MOSFET之后，在衬底的主表面上沉积层间绝缘膜。然后，在由通过隔离部包围的区域中形成从层间绝缘膜的上表面延伸到衬底厚度内的深度的深导电沟槽。随后，将导电膜埋在深导电沟槽中以形成通过互连部分。然后，在将基板的下表面研磨抛光至不暴露通过隔离部分和通过互连部分的程度之后，进行湿法蚀刻，使其暴露于每个通过隔离部分的下部的部分，以及直通互连部分。

14. 发明授权

US5778202A Ring bus multiprocessor system and processor boards for constituting the same 失效
标题翻译：环形总线多处理器系统和处理器板构成相同
公开(公告)号：US5778202A
公开(公告)日：1998-07-07
申请号：US662445
申请日：1996-06-10
申请人： Norihiko Kuroishi , Tetsuro Kawata , Kenichi Kawauchi , Nobuaki Miyakawa , Reiji Aibara , Mitsumasa Koyanagi
发明人： Norihiko Kuroishi , Tetsuro Kawata , Kenichi Kawauchi , Nobuaki Miyakawa , Reiji Aibara , Mitsumasa Koyanagi
IPC分类号： G06F15/173 , G06F13/40 , G06F13/00 , G06F13/38
CPC分类号： G06F13/4095
摘要： A ring bus multiprocessor system whose processors are laid out and connected in such a manner that the system is enhanced in stability and performance, is easy to modify in scale, and is lowered in manufacturing cost. On a processor board, processors are serially connected by communication buses to form a processor group. Each processor board may have an even-numbered plurality of processor groups mounted thereon. A plurality of processor boards are laid out in parallel and are interconnected between adjacent boards by means of inter-processor communication buses. Each of the odd-numbered processor groups is connected from one board to the next up to the most downstream board where the connection is looped back to the adjacent even-numbered processor group. In turn, the even-numbered processor group is connected from one board to the next back to the most upstream board where the connection is again looped back to the adjacent odd-numbered processor group, and so on, whereby a ring bus arrangement is formed.
摘要翻译：一种环形总线多处理器系统，其处理器以这样的方式布置和连接，使得系统的稳定性和性能得到提高，容易在规模上进行修改，并降低制造成本。在处理器板上，处理器通过通信总线串联连接，形成处理器组。每个处理器板可以具有安装在其上的偶数个多个处理器组。多个处理器板并联布置并且通过处理器间通信总线在相邻板之间互连。每个奇数处理器组从一个板连接到下一个板到下游板，其中连接被环回到相邻的偶数处理器组。反过来，偶数处理器组从一个板连接到下一个回到最上游板，其中连接再次环回到相邻的奇数处理器组，依此类推，形成环形总线布置。

15. 发明授权

US5029121A Digital filter processing device 失效
标题翻译：数字滤波处理装置
公开(公告)号：US5029121A
公开(公告)日：1991-07-02
申请号：US512204
申请日：1990-04-20
申请人： Tetsuro Kawata , Eiri Hashimoto , Nobuaki Miyakawa
发明人： Tetsuro Kawata , Eiri Hashimoto , Nobuaki Miyakawa
IPC分类号： H03H17/02 , H03H17/06
CPC分类号： H03H17/06
摘要： A digital filter processing device includes at least a plurality of multipliers each for multiplying data signal by coefficient data, and an adder for adding together the multiplication results derived from the multipliers. The digital filter processing device further includes coefficient registers each for storing the coefficient data as is shifted so that a first effective digit of the coefficient data lies at the left end, shift-quantity registers provided in connection with the coefficient registers, and each for storing a quantity of shift equal to the shift quantity of the coefficient data, and barrel shifters each for shifting the digits of an output data from each of the multipliers by the shift quantity stored in each of the shift-quantity registers, in the opposite direction to that of the shift in each of the coefficient registers. The digital filter processing device may further include a second shift-quantity register for storing a second quantity of shift, and a second barrel shifter for shifting the digits of the output data of the adder by the second shift quantity.
摘要翻译：数字滤波处理装置至少包括用于将数据信号乘以系数数据的多个乘法器和用于将从乘法器导出的相乘结果相加的加法器。数字滤波处理装置还包括系数寄存器，每个系数寄存器用于存储被移位的系数数据，使得系数数据的第一有效数字位于左端，与系数寄存器相关联的移位量寄存器，并且每个用于存储移位量等于系数数据的移位量，以及桶形移位器，用于将存储在每个移位量寄存器中的每个移位量寄存器的输出数据的数字移位到与每个移位量寄存器相反的方向上，每个系数寄存器的移位。数字滤波处理装置还可以包括用于存储第二移位量的第二移位量寄存器和用于将加法器的输出数据的数字移位第二移位量的第二桶形移位器。

16. 发明授权

US4454500A Analog data acquisition device 失效
标题翻译：模拟数据采集装置
公开(公告)号：US4454500A
公开(公告)日：1984-06-12
申请号：US348666
申请日：1982-02-16
申请人： Kazuo Kato , Nobuaki Miyakawa , Makoto Aihara , Kiyoshi Matsubara
发明人： Kazuo Kato , Nobuaki Miyakawa , Makoto Aihara , Kiyoshi Matsubara
IPC分类号： H03M1/38 , G01R19/00 , H03K5/24 , H03M1/00 , H03K13/02
CPC分类号： H03K5/24 , G01R19/0038 , H03M1/40 , H03M1/46
摘要： An analog data acquisition device fetches a plurality of analog data by a multiplexer in time-division, compares the analog data fetched with a reference value applied from a digital-to-analog converter by a two-input comparator, and produces the result of comparison to a data bus. The result of comparison is also applied to a successive approximation register where the analong-to-digital conversion is effected by successively changing the digital data to the digital-to-analog converter, and the digital data converted is read out onto the data bus.The digital data applied to the digital-to-analog converter is either the output from the successive approximation register or the output from the reference register loaded through the data bus, in accordance with the contents of the control register loaded through the data bus. Thus, in which mode the device operates, in the comparing mode or in the analog-to-digital conversion mode, is selected by the control register.
摘要翻译：模拟数据采集装置通过多路复用器分时获取多个模拟数据，将获取的模拟数据与通过双输入比较器从数模转换器施加的参考值进行比较，并产生比较结果到数据总线。比较结果也适用于逐次逼近寄存器，其中通过将数字数据连续地改变为数模转换器来进行分析数字转换，并将数字数据转换到数据总线上。根据通过数据总线加载的控制寄存器的内容，应用于数模转换器的数字数据是来自逐次逼近寄存器的输出或通过数据总线加载的参考寄存器的输出。因此，设备在哪种模式下工作，在比较模式或模数转换模式下，由控制寄存器选择。

17. 发明授权

US4142407A Air flow metering apparatus for internal combustion engines 失效
标题翻译：用于内燃机的气流计量装置
公开(公告)号：US4142407A
公开(公告)日：1979-03-06
申请号：US797690
申请日：1977-05-17
申请人： Hiroshi Kuroiwa , Yoshishige Ohyama , Yutaka Nishimura , Nobuaki Miyakawa
发明人： Hiroshi Kuroiwa , Yoshishige Ohyama , Yutaka Nishimura , Nobuaki Miyakawa
IPC分类号： F02D35/00 , F02D41/18 , G01F1/32 , G01F1/684 , G01F5/00 , G01F7/00
CPC分类号： G01F7/00 , F02D41/185 , G01F1/3209 , G01F1/3272 , G01F1/6842 , G01F5/00 , Y02T10/146
摘要： An air flow metering apparatus for measuring a suction air flow fed to an internal combustion engine comprises at least two Karman' vortex type air flow meters disposed separately in at least two air suction passages, respectively. The output signals from the flow meters are switched in such manner that in a predetermined range of high air flow rates, the output signal from one of the flow meter is utilized for measuring or sensing the air flow rate, while in a predetermined low flow rate range, the output signal from the other flow meter is utilized for the same purpose. Alternatively, in a predetermined low flow rate range, only one of the air suction passages is employed, while both of the air suction passages are employed in a predetermined range of high air flow rates. The air flow metering apparatus assures the detection or measurement of the suction air flow rate over a whole operation range of the engine with a high reliability and enhanced accuracy.
摘要翻译：用于测量供给内燃机的吸入空气流的气流计量装置包括分别设置在至少两个空气吸入通道中的至少两个卡门涡流式空气流量计。来自流量计的输出信号以这样的方式切换，使得在高空气流量的预定范围内，来自流量计中的一个的输出信号用于测量或感测空气流速，而在预定的低流量范围内，来自另一个流量计的输出信号用于相同的目的。或者，在预定的低流量范围内，仅使用一个空气吸入通道，而两个空气吸入通道都以高空气流量的预定范围使用。空气流量计量装置确保在发动机的整个工作范围内以高可靠性和高精度检测或测量吸入空气流量。

18. 发明授权

US4041299A Multiplication apparatus 失效
标题翻译：乘法装置
公开(公告)号：US4041299A
公开(公告)日：1977-08-09
申请号：US671988
申请日：1976-03-30
申请人： Nobuaki Miyakawa
发明人： Nobuaki Miyakawa
IPC分类号： G06G7/16 , G06G7/161 , G06G7/24
CPC分类号： G06G7/161
摘要： A plurality of input signals to be multiplied are applied sequentially to a logarithmic time-width transformer in a form of electric analog signal in a predetermined order. The transformer converts each of the inputs into a signal having a time width in logarithmic relation with the analog value of corresponding input signal in response to the input signal to thereby provide a plurality of converted signals. Each of the converted signals is further converted into a train of pulses, the number thereof corresponding to the time width of the converted signal so as to convert the plurality of converted signals into a plural train of pulses. Each of the plural trains of pulses are applied to a counter so as to count up the number of pulses of the plural trains of pulses to thereby obtain the total amount of the time width of the plurality of counted signals. The total amount of the time width is converted into an electric value in antilogarithmic relation therewith to thereby obtain a multiplied value of the analog value of the plurality of input signals.
摘要翻译：将要乘以的多个输入信号以预定顺序以电模拟信号的形式被顺序地施加到对数时间宽度变换器。变压器响应于输入信号将每个输入转换成具有与对应输入信号的模拟值的对数关系的时间宽度的信号，从而提供多个转换的信号。每个转换的信号被进一步转换成一串脉冲，其数量对应于转换的信号的时间宽度，以便将多个转换的信号转换成多个脉冲串。将多列脉冲中的每一列施加到计数器，以计数多列脉冲的脉冲数，从而获得多个计数信号的时间宽度的总量。将时间宽度的总量转换为与其对数关系的电值，从而获得多个输入信号的模拟值的相乘值。

19. 发明授权

US08354730B2 Manufacturing method of semiconductor device and semiconductor device 失效
标题翻译：半导体器件和半导体器件的制造方法
公开(公告)号：US08354730B2
公开(公告)日：2013-01-15
申请号：US11997436
申请日：2006-08-25
申请人： Satoshi Moriya , Toshio Saito , Goichi Yokoyama , Tsuyoshi Fujiwara , Hidenori Sato , Nobuaki Miyakawa
发明人： Satoshi Moriya , Toshio Saito , Goichi Yokoyama , Tsuyoshi Fujiwara , Hidenori Sato , Nobuaki Miyakawa
IPC分类号： H01L21/70
CPC分类号： H01L21/76898 , H01L21/2007 , H01L21/76232 , H01L21/8221 , H01L23/481 , H01L24/94 , H01L2224/2518 , H01L2924/01004 , H01L2924/04941 , H01L2924/1305 , H01L2924/14 , H01L2924/00
摘要： A structure obtaining a desired integrated circuit by sticking together a plurality of semiconductor substrates and electrically connecting integrated circuits formed on semiconductor chips of the respective semiconductor substrates is provided, and a penetrating electrode penetrating between a main surface and a rear surface of each of the semiconductor substrates and a penetrating separation portion separating the penetrating electrode are separately arranged. Thereby, after forming an insulation trench portion for formation of the penetrating separation portion on the semiconductor substrate, a MIS•FET is formed, and then, a conductive trench portion for formation of the penetrating electrode can be formed. Therefore, element characteristics of a semiconductor device having a three-dimensional structure can be improved.
摘要翻译：提供了通过将形成在各个半导体衬底的半导体芯片上的多个半导体衬底和电连接集成电路粘合在一起而获得所需集成电路的结构，并且穿透电极穿透每个半导体衬底的主表面和后表面分离基板和分离穿透电极的穿透分离部分。因此，在半导体衬底上形成用于形成穿透分离部分的绝缘沟槽部分之后，形成MIS·FET，然后形成用于形成穿透电极的导电沟槽部分。因此，可以提高具有三维结构的半导体器件的元件特性。

20. 发明授权

US08049296B2 Semiconductor wafer 有权
标题翻译：半导体晶圆
公开(公告)号：US08049296B2
公开(公告)日：2011-11-01
申请号：US12718061
申请日：2010-03-05
申请人： Nobuaki Miyakawa , Takanori Maebashi , Takahiro Kimura
发明人： Nobuaki Miyakawa , Takanori Maebashi , Takahiro Kimura
IPC分类号： H01L29/00
CPC分类号： H01L25/117 , H01L21/6835 , H01L21/76898 , H01L21/823475 , H01L21/823481 , H01L23/481 , H01L25/0657 , H01L25/50 , H01L2224/16145 , H01L2224/81139 , H01L2225/06513 , H01L2225/06524 , H01L2225/06527 , H01L2225/06541 , H01L2225/06582 , H01L2924/01019 , H01L2924/01037 , H01L2924/1305 , H01L2924/13091 , H01L2924/00
摘要： A deep isolation trench extending from the main surface of a substrate to a desired depth is formed on the substrate with an insulating film in buried in it to form a through isolation portion. Subsequently, after a MOSFET is formed on the main surface of the substrate, an interlayer insulating film is deposited on the main surface of the substrate. Then, a deep conduction trench extending from the upper surface of the interlayer insulating film to a depth within the thickness of the substrate is formed in a region surrounded by the through isolation portion. Subsequently, a conductive film is buried in the deep conduction trench to form through interconnect portion. Then, after the undersurface of the substrate is ground and polished to an extent not to expose the through isolation portion and the through interconnect portion, wet etching is performed to an extent to expose parts of the lower portion of each of the through isolation portion and the through interconnect portion.
摘要翻译：在衬底上形成有从衬底的主表面延伸到所需深度的深度隔离沟槽，其中埋置有绝缘膜以形成通过隔离部分。随后，在衬底的主表面上形成MOSFET之后，在衬底的主表面上沉积层间绝缘膜。然后，在由通过隔离部包围的区域中形成从层间绝缘膜的上表面延伸至衬底厚度内的深度的深导电沟槽。随后，将导电膜埋在深导电沟槽中以形成通过互连部分。然后，在将基板的下表面研磨抛光至不暴露通过隔离部分和通过互连部分的程度之后，进行湿法蚀刻，使其暴露于每个通过隔离部分的下部的部分，以及直通互连部分。

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