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11. 发明授权

US06300819B1 Circuit including forward body bias from supply voltage and ground nodes 失效
标题翻译：电路包括电源电压和接地节点的正向偏置
公开(公告)号：US06300819B1
公开(公告)日：2001-10-09
申请号：US09078395
申请日：1998-05-13
申请人： Vivek K. De , Ali Keshavarzi , Siva G. Narendra , Shekhar Y. Borkar
发明人： Vivek K. De , Ali Keshavarzi , Siva G. Narendra , Shekhar Y. Borkar
IPC分类号： G05F110
CPC分类号： H01L27/0928 , H01L29/1087 , H03K19/0948
摘要： One embodiment of the invention includes a semiconductor circuit including a ground voltage node to provide a ground voltage and pFET transistors having an n-type body electrically coupled to the ground voltage node to forward body bias the pFET transistors. Another embodiment of the invention includes a semiconductor circuit including a supply voltage node to provide a supply voltage and nFET transistors having a p-type body electrically coupled to the supply voltage node to forward body bias the nFET transistors. Still another embodiment of the invention includes a semiconductor circuit including a ground voltage node to provide a ground voltage and pFET transistors having an n-type body electrically coupled to the ground voltage node to forward body bias the pFET transistors. The circuit also includes a supply voltage node to provide a supply voltage and nFET transistors having a p-type body electrically coupled to the supply voltage node to forward body bias the nFET transistors.
摘要翻译：本发明的一个实施例包括一个半导体电路，该半导体电路包括提供接地电压的接地电压节点和具有电耦合到接地电压节点的n型体的pFET晶体管，以使pFET晶体管的偏置正向。本发明的另一个实施例包括一个半导体电路，其包括提供电源电压的电源电压节点和具有电耦合到电源电压节点的p型体的nFET晶体管，以使nFET晶体管的本体偏置转向。本发明的另一个实施例包括一个包括接地电压节点以提供接地电压的半导体电路，以及具有电耦合到接地电压节点的n型体的pFET晶体管，以使pFET晶体管的偏置正向。该电路还包括用于提供电源电压的电源电压节点和具有电耦合到电源电压节点的p型主体的nFET晶体管，以使nFET晶体管的主体偏置转向。

12. 发明授权

US06100751A Forward body biased field effect transistor providing decoupling capacitance 失效
标题翻译：正向偏置场效应晶体管提供去耦电容
公开(公告)号：US06100751A
公开(公告)日：2000-08-08
申请号：US078432
申请日：1998-05-13
申请人： Vivek K. De , Ali Keshavarzi , Siva G. Narendra , Shekhar Y. Borkar
发明人： Vivek K. De , Ali Keshavarzi , Siva G. Narendra , Shekhar Y. Borkar
IPC分类号： H01L27/092 , H01L29/10 , H03K19/0948 , H03L7/081 , H03L7/099 , G05F1/10
CPC分类号： H03L7/0812 , H01L27/0928 , H01L29/1087 , H03K19/0948 , H03L7/0995
摘要： In one embodiment of the invention, a semiconductor circuit includes a first group of field effect transistors that are forward body biased and have threshold voltages and a second group of field effect transistors that are not forward body biased and have threshold voltages that are higher than the threshold voltages of the first group of field transistors. In another embodiment of the invention, a semiconductor circuit includes first and second groups of field effect transistors. The circuit includes voltage source circuitry to provide voltage signals to bodies of the first group of field effect transistors to forward body bias the transistors of the first group. When the voltage signals are applied, the transistors of the first group have lower threshold voltages than do the transistors of the second group, except that there may be unintentional variations in threshold voltages due to parameter variations. Other aspects of the invention include forward biased decoupling transistors and a method of testing for leakage.
摘要翻译：在本发明的一个实施例中，半导体电路包括正向偏置并具有阈值电压的第一组场效应晶体管和不是正向主体偏置的第二组场效应晶体管，并且具有高于第一组场效应晶体管的阈值电压。在本发明的另一个实施例中，半导体电路包括第一和第二组场效应晶体管。电路包括电压源电路，用于向第一组场效应晶体管的主体提供电压信号，以将第一组的晶体管的体偏置转发。当施加电压信号时，除了由于参数变化引起的阈值电压可能存在无意的变化之外，第一组的晶体管具有比第二组的晶体管低的阈值电压。本发明的其它方面包括正向偏置去耦晶体管和一种测试泄漏的方法。

13. 发明授权

US08288846B2 Power management integrated circuit 有权
标题翻译：电源管理集成电路
公开(公告)号：US08288846B2
公开(公告)日：2012-10-16
申请号：US12660305
申请日：2010-02-24
申请人： Siva G. Narendra , James W. Tschanz , Howard A. Wilson , Donald S. Gardner , Peter Hazucha , Gerhard Schrom , Tanay Karnik , Nitin Borkar , Vivek K. De , Shekhar Y. Borkar
发明人： Siva G. Narendra , James W. Tschanz , Howard A. Wilson , Donald S. Gardner , Peter Hazucha , Gerhard Schrom , Tanay Karnik , Nitin Borkar , Vivek K. De , Shekhar Y. Borkar
IPC分类号： H01L23/495 , H01L23/52 , H01L21/00
CPC分类号： H01L25/0657 , H01L25/18 , H01L2224/0554 , H01L2224/05568 , H01L2224/05573 , H01L2224/16 , H01L2224/16145 , H01L2224/16227 , H01L2225/06513 , H01L2225/06527 , H01L2924/00014 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： An integrated circuit (IC) package is disclosed. The IC package includes a first die; and a second die bonded to the CPU die in a three dimensional packaging layout.
摘要翻译：公开了一种集成电路（IC）封装。 IC封装包括第一裸片; 以及以三维封装布局结合到CPU管芯的第二管芯。

14. 发明授权

US07698576B2 CPU power delivery system 有权
标题翻译： CPU供电系统
公开(公告)号：US07698576B2
公开(公告)日：2010-04-13
申请号：US10955746
申请日：2004-09-30
申请人： Siva G. Narendra , Howard A. Wilson , Donald S. Gardner , Peter Hazucha , Gerhard Schrom , Tanay Karnik , Nitin Borkar , Vivek K. De , Shekhar Y. Borkar
发明人： Siva G. Narendra , Howard A. Wilson , Donald S. Gardner , Peter Hazucha , Gerhard Schrom , Tanay Karnik , Nitin Borkar , Vivek K. De , Shekhar Y. Borkar
IPC分类号： G06F1/26
CPC分类号： H01L25/18 , G06F1/189 , G06F1/26 , H01L25/0657 , H01L2224/16 , H01L2225/06513 , H01L2225/06527 , H01L2924/00011 , H01L2924/00014 , H01L2924/3011 , H01L2224/0401
摘要： A central processing unit (CPU) is disclosed. The CPU includes a CPU die; and a voltage regulator die bonded to the CPU die in a three dimensional packaging layout.
摘要翻译：公开了一种中央处理单元（CPU）。 CPU包括CPU管芯; 以及以三维封装布局结合到CPU裸片的电压调节器芯片。

15. 发明授权

US07444528B2 Component reliability budgeting system 有权
标题翻译：组件可靠性预算系统
公开(公告)号：US07444528B2
公开(公告)日：2008-10-28
申请号：US11295400
申请日：2005-12-06
申请人： Siva G. Narendra , James W. Tschanz , Vivek K. De , Stephen H. Tang
发明人： Siva G. Narendra , James W. Tschanz , Vivek K. De , Stephen H. Tang
IPC分类号： G06F1/26 , G06F1/00
CPC分类号： G06F1/206 , Y02D10/16
摘要： A system may include acquisition of a supply voltage information representing past supply voltages supplied to an electrical component, acquisition of a temperature information representing past temperatures of the electrical component, and control of a performance characteristic of the electrical component based on the supply voltage information and the temperature information. Some embodiments may further include determination of a reliability margin based on the supply voltage information, the temperature information, and on a reliability specification of the electrical component, and change of the performance characteristic based on the reliability margin.
摘要翻译：系统可以包括获取表示提供给电气部件的过去电源电压的电源电压信息，基于电源电压信息获取表示电气部件的过去温度的温度信息和电气部件的性能特性的控制，以及温度信息。一些实施例还可以包括基于电源电压信息，温度信息以及电气部件的可靠性规格以及基于可靠性裕度的性能特性的改变来确定可靠性裕度。

16. 发明授权

US06917237B1 Temperature dependent regulation of threshold voltage 失效
标题翻译：温度依赖调节阈值电压
公开(公告)号：US06917237B1
公开(公告)日：2005-07-12
申请号：US10792262
申请日：2004-03-02
申请人： James W. Tschanz , Mircea R. Stan , Siva G. Narendra , Vivek K. De
发明人： James W. Tschanz , Mircea R. Stan , Siva G. Narendra , Vivek K. De
IPC分类号： G05F3/20 , G05F3/26 , H03K3/01
CPC分类号： G05F3/262 , G05F3/205
摘要： Embodiments circuits provide a transistor body bias voltage so that the ratio of ION to IOFF is constant over a range of temperature, where ION is a transistor current when ON and IOFF is a (leakage) transistor current when OFF. In one embodiment, a nFET is biased to provide ION to a current mirror that sources a current AION to a node, a nFET is biased to provide IOFF to a current mirror that sinks a current BIOFF from the node, and an amplifier provides feedback from the node to the body terminals of the nFETs so that at steady state AION=BIOFF, where A and B are constants independent over a range of temperature. In this way, the ratio ION/IOFF is maintained at B/A for some range of temperatures. Other embodiments are described and claimed.
摘要翻译：实施例电路提供晶体管体偏置电压，使得I ON / OFF与I OFF之间的比率在温度范围内是恒定的，其中I < 是ON时的晶体管电流，当OFF时，I 是晶体管电流（泄漏）。在一个实施例中，nFET被偏置以将电流镜提供给电流反射镜，该电流镜将节点的当前AI导通，nFET被偏置以提供I < OFF 到从节点吸收当前BI OFF的电流镜，并且放大器从节点向nFET的体式终端提供反馈，使得在稳态AI < ON = BI ，其中A和B在温度范围内是常数独立的。以这种方式，在一些温度范围内，比率I ON / OFF / OFF保持在B / A。描述和要求保护其他实施例。

17. 发明授权

US06734498B2 Insulated channel field effect transistor with an electric field terminal region 有权
公开(公告)号：US06734498B2
公开(公告)日：2004-05-11
申请号：US09165483
申请日：1998-10-02
申请人： Ali Keshavarzi , Vivek K. De , Siva G. Narendra
发明人： Ali Keshavarzi , Vivek K. De , Siva G. Narendra
IPC分类号： H01L2701
CPC分类号： H01L29/78603 , H01L21/84 , H01L27/1203 , H01L29/78606 , H01L29/78645 , H01L29/78648
摘要： In one embodiment, the invention includes a field effect transistor having a substrate, a source, and a drain. An electric field terminal region is lower than the source and drain and is in the substrate. A body is above the electric field terminal region between the source and drain. In another embodiment, the invention includes a field effect transistor having an insulator layer and a body above the insulator layer between a source and a drain. A substrate is below the insulator layer. A gate is above the body and between the source and drain. An electric field terminal region is included in the substrate. The body may be undoped and the threshold voltage be set by setting the distance between the insulator layer and a gate insulator. The body, substrate, and electric field terminal region may float or one or more of them may be biased.

18. 发明授权

US06710642B1 Bias generation circuit 有权
标题翻译：偏置电路
公开(公告)号：US06710642B1
公开(公告)日：2004-03-23
申请号：US10334644
申请日：2002-12-30
申请人： Stephen H. Tang , Siva G. Narendra , Vivek K. De
发明人： Stephen H. Tang , Siva G. Narendra , Vivek K. De
IPC分类号： G05F110
CPC分类号： G05F3/205
摘要： According to some embodiments, a bias generation circuit is provided.
摘要翻译：根据一些实施例，提供偏置产生电路。

19. 发明授权

US06632686B1 Silicon on insulator device design having improved floating body effect 失效
标题翻译：硅绝缘体器件设计具有改善的浮体效应
公开(公告)号：US06632686B1
公开(公告)日：2003-10-14
申请号：US09672696
申请日：2000-09-29
申请人： Ali Keshavarzi , Siva G. Narendra , James W. Tschanz , Vivek K. De
发明人： Ali Keshavarzi , Siva G. Narendra , James W. Tschanz , Vivek K. De
IPC分类号： H01L2166
CPC分类号： G06F17/5068 , G06F17/5063 , H01L27/1203
摘要： A method is provided for designing an electronic device. This may include determining a capacitance ratio of a design of the electronic device and altering the design so as to increase the capacitance ratio of said electronic device. The capacitance ratio may be Cdj/(Cdj+Csj+CBOX), where Cdj is a capacitance of a drain-body junction, Csj is a capacitance of a source-body junction and CBOX is a capacitance of a buried oxide layer.
摘要翻译：提供了一种用于设计电子设备的方法。这可以包括确定电子设备的设计的电容比并改变设计以增加所述电子设备的电容比。电容比可以是C dj /（C dj + C sj + C BOX ），其中C dj 是漏 - 体结的电容C sj 是源体结的电容，C BOX 是掩埋氧化物层的电容。

20. 发明授权

US06566914B2 Sense amplifier having reduced Vt mismatch in input matched differential pair 有权
公开(公告)号：US06566914B2
公开(公告)日：2003-05-20
申请号：US10183586
申请日：2002-06-26
申请人： David W. Bruneau , Siva G. Narendra , Vivek K. De
发明人： David W. Bruneau , Siva G. Narendra , Vivek K. De
IPC分类号： G11C706
CPC分类号： G11C7/062
摘要： A sense amplifier in which its output nodes provide a full voltage swing between the supply and return nodes. The sense amplifier further includes a reset circuit to selectively equalize the first and second output nodes. An output of the sense amplifier is coupled to either a digital logic gate or a flip-flop to receive the full swing. Each field effect transistor (FET) of the input pair in the sense amplifier is either zero body biased or forward body biased, so that a bulk-source junction of each FET is either zero biased or forward biased.

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