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    • 9. 发明授权
    • Transistor group mismatch detection and reduction
    • 晶体管组不匹配检测和还原
    • US06272666B1
    • 2001-08-07
    • US09224574
    • 1998-12-30
    • Shekhar Y. BorkarVivek K. DeAli KeshavarziSiva G. Narendra
    • Shekhar Y. BorkarVivek K. DeAli KeshavarziSiva G. Narendra
    • G06F1750
    • G01R31/2882G01R31/3016
    • In some embodiments, the invention includes a system having first and second domains. The system includes a first performance detection circuitry including some transistors of the first domain to provide a first performance rating signal indicative of transistor switching rates of the first domain. The system includes second performance detection circuitry including some transistors of the second domain to provide a second performance rating signal indicative of transistor switching rates the second domain. The system further includes control circuitry to receive the first and second performance rating signals and control a setting for a body bias signal for the first domain and control a setting for a body bias signal for the second domain responsive to the performance rating signals. In some embodiments, the control circuitry also provides supply voltage signals and clock signals responsive to the performance signals. The first and second domains may have clock signals with the same frequency and the bias values are set such that the transistors of the first and second domains can switch properly while the first and second domains have the clock signals and wherein one of the first and second domains operates at less than optimal performance.
    • 在一些实施例中,本发明包括具有第一和第二域的系统。 该系统包括第一性能检测电路,其包括第一域的一些晶体管,以提供指示第一域的晶体管切换速率的第一性能评估信号。 该系统包括第二性能检测电路,其包括第二域的一些晶体管,以提供指示第二域的晶体管切换速率的第二性能评估信号。 该系统还包括控制电路,用于接收第一和第二性能评定信号并且控制针对第一域的体偏置信号的设置,并且响应于性能等级信号来控制针对第二域的体偏置信号的设置。 在一些实施例中,控制电路还响应于性能信号提供电源电压信号和时钟信号。 第一和第二域可以具有相同频率的时钟信号,并且偏置值被设置为使得第一和第二域的晶体管可以正确地切换,而第一和第二域具有时钟信号,并且其中第一和第二域中的一个 域以不到最佳性能运行。
    • 10. 发明授权
    • Multiple well transistor circuits having forward body bias
    • 具有前向偏置的多个阱晶体管电路
    • US06218895B1
    • 2001-04-17
    • US09078424
    • 1998-05-13
    • Vivek K. DeAli KeshavarziSiva G. NarendraShekhar Y. Borkar
    • Vivek K. DeAli KeshavarziSiva G. NarendraShekhar Y. Borkar
    • H01L2976
    • H01L27/0928H01L29/1087H03K19/0948
    • In one embodiment to the invention, a semiconductor circuit includes a substrate and a first well formed in the substrate. A first group of field effect transistors is formed in the first well and has a first body. The circuit includes a first body voltage to the first body to forward body bias the first group of field effect transistors. The circuit includes a first isolation structure to contain the first body voltage in the first well. In another embodiment, the circuit further includes a second group of field effect transistors having a non-forward body bias and the first isolation structure prevents the first body voltage from influencing a voltage of a body of the second group of field effect transistors. In yet another embodiment, a second isolation structure adjacent to the second well contain a second body voltage in a second well holding the second group of field effect transistors.
    • 在本发明的一个实施例中,半导体电路包括衬底和形成在衬底中的第一阱。 在第一阱中形成第一组场效应晶体管,并且具有第一主体。 该电路包括第一体电压,以使第一组场效应晶体管偏转第一体。 电路包括第一隔离结构,以在第一阱中容纳第一体电压。 在另一实施例中,电路还包括具有非正向主体偏置的第二组场效应晶体管,并且第一隔离结构防止第一体电压影响第二组场效应晶体管的主体的电压。 在另一个实施例中,与第二阱相邻的第二隔离结构在保持第二组场效应晶体管的第二阱中包含第二体电压。