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11. 发明授权

US06585830B2 Method for cleaning tungsten from deposition wall chambers 失效
公开(公告)号：US06585830B2
公开(公告)日：2003-07-01
申请号：US09727326
申请日：2000-11-30
申请人： Nace Layadi , Sailesh Mansinh Merchant , Simon John Molloy
发明人： Nace Layadi , Sailesh Mansinh Merchant , Simon John Molloy
IPC分类号： B08B500
CPC分类号： C23C16/4405
摘要： An unwanted tungsten film deposit on a Chemical Vapor Deposition chamber is cleaned by adding a mixture of at least two cleaning gases into the chamber at a predetermined temperature and pressure and in contact with said chamber walls for a sufficient length of time. The cleaning gases and reacted tungsten species are removed from the chamber by vacuum, and unreacted cleaning gases are removed by purging the chamber with an inert gas. At least one cleaning gas is selected from the group consisting of bromomethane, dibromomethane, bromoform and mixtures thereof. The temperature of the chamber is preferably at least about 300 degrees Celsius. The cleaning gases in the chamber are at a pressure in the range from about 100 to 200 Torr and the chamber is purged at a pressure in the range from about 200 to 500 Torr.

12. 发明授权

US06436829B1 Two phase chemical/mechanical polishing process for tungsten layers 有权
标题翻译：钨层的两相化学/机械抛光工艺
公开(公告)号：US06436829B1
公开(公告)日：2002-08-20
申请号：US09632445
申请日：2000-08-04
申请人： Nace Layadi , Arun K. Nanda
发明人： Nace Layadi , Arun K. Nanda
IPC分类号： H01L21302
CPC分类号： H01L21/7684 , H01L21/3212
摘要： The present invention provides a method for polishing a semiconductor substrate comprising: (a) polishing a metal layer located on a semiconductor wafer with a slurry at a first polishing rate, wherein the slurry has a predetermined concentration of an oxidizing agent therein; (b) forming a diluted slurry by diluting the polishing slurry with a diluent to substantially reduce the predetermined concentration of the oxidizing agent; and (c) polishing the metal layer at a second polishing rate less than the first polishing rate and in the presence of the diluted slurry.
摘要翻译：本发明提供了一种用于抛光半导体衬底的方法，包括：（a）以第一抛光速率用浆料抛光位于半导体晶片上的金属层，其中所述浆料具有预定浓度的氧化剂; （b）通过用稀释剂稀释抛光浆料形成稀释的浆料，以显着降低氧化剂的预定浓度; 和（c）以小于第一研磨速率的第二抛光速率和稀释浆料的存在下抛光金属层。

13. 发明授权

US06358790B1 Method of making a capacitor 有权
标题翻译：制作电容器的方法
公开(公告)号：US06358790B1
公开(公告)日：2002-03-19
申请号：US09250501
申请日：1999-02-16
申请人： Larry Bruce Fritzinger , Nace Layadi , Sailesh Mansinh Merchant , Pradip Kumar Roy
发明人： Larry Bruce Fritzinger , Nace Layadi , Sailesh Mansinh Merchant , Pradip Kumar Roy
IPC分类号： H01L218234
CPC分类号： H01L28/60 , H01L21/3212 , H01L21/32136 , H01L27/1085 , H01L28/40 , H01L28/75 , H01L28/90
摘要： The present invention provides a method for fabricating a capacitor, comprising the steps of forming a trench in a substrate, forming a layer of a first material selected from the group consisting of titanium and titanium nitride in the trench, filling the trench with a conductive material to form a plug, planarizing the substrate, patterning the substrate to expose the first material, forming an electrode material layer over the substrate, and patterning the electrode material layer, whereby the first material is substantially encapsulated by the electrode material layer.
摘要翻译：本发明提供一种制造电容器的方法，包括以下步骤：在衬底中形成沟槽，在沟槽中形成从由钛和氮化钛组成的组中选择的第一材料的层，用导电材料填充沟槽以形成插头，使衬底平坦化，图案化衬底以露出第一材料，在衬底上形成电极材料层，以及图案化电极材料层，由此第一材料基本上被电极材料层封装。

14. 发明授权

US07163438B2 Zone polishing using variable slurry solid content 有权
标题翻译：使用可变浆料固体含量进行区域抛光
公开(公告)号：US07163438B2
公开(公告)日：2007-01-16
申请号：US11208829
申请日：2005-08-22
申请人： Alvaro Maury , Jovin Lim , Nace Layadi , Sebastian Ouek
发明人： Alvaro Maury , Jovin Lim , Nace Layadi , Sebastian Ouek
IPC分类号： B24B49/00 , B24B7/00 , B24B1/00
CPC分类号： B24B37/04 , B24B57/02
摘要： A slurry dispensing apparatus for use with a chemical mechanical polishing tool for planarizing semiconductor substrates having irregular topology. The apparatus includes a slurry dispensing manifold with a first end suspended over a polishing pad, and a second end for mounting to the chemical mechanical polishing tool. The slurry dispensing manifold has a linear array of nozzles positioned under the suspended manifold. Each nozzle provides an adjusted slurry mixture that is supplied from bifurcated supply lines. A first branch supplying a slurry, and a second branch supplying deionized water. Each nozzle is capable of providing a particular slurry concentration to either decrease or to increase polishing rate in specific zonal areas on a substrate according to its surface topology.
摘要翻译：一种用于与化学机械抛光工具一起用于平坦化具有不规则拓扑的半导体衬底的浆料分配装置。该设备包括具有悬挂在抛光垫上的第一端的浆料分配歧管和用于安装到化学机械抛光工具的第二端。浆料分配歧管具有位于悬浮歧管下方的线性阵列的喷嘴。每个喷嘴提供从分叉供应管线供应的经调节的浆料混合物。供应浆料的第一分支和供应去离子水的第二分支。根据其表面拓扑结构，每个喷嘴能够提供特定的浆料浓度以降低或提高基材上特定区带区域的抛光速率。

15. 发明授权

US06910907B2 Contact for use in an integrated circuit and a method of manufacture therefor 失效
标题翻译：用于集成电路的接触及其制造方法
公开(公告)号：US06910907B2
公开(公告)日：2005-06-28
申请号：US10716299
申请日：2003-11-18
申请人： Nace Layadi , Alvaro Maury
发明人： Nace Layadi , Alvaro Maury
IPC分类号： H01L21/768 , H01R13/28 , H01R25/00
CPC分类号： H01L21/76877
摘要： The present invention provides a contact for use in an integrated circuit, a method of manufacture therefor, and an integrated circuit including the aforementioned contact. The contact, in accordance with the principles of the present invention, may include a via located in a substrate, and a contact plug located in the via, wherein the contact plug has a first portion having a notch removed therefrom and a second portion filling the notch.
摘要翻译：本发明提供了一种用于集成电路的接点及其制造方法，以及包括上述接触的集成电路。根据本发明的原理的触点可以包括位于基板中的通孔和位于通孔中的接触塞，其中接触插塞具有从其中移除的凹口的第一部分和填充该通孔的第二部分缺口。

16. 发明授权

US06395639B1 Process for improving line width variations between tightly spaced and isolated features in integrated circuits 有权
标题翻译：用于改善集成电路中紧密间隔和隔离特征之间的线宽变化的过程
公开(公告)号：US06395639B1
公开(公告)日：2002-05-28
申请号：US09397458
申请日：1999-09-16
申请人： Thomas Craig Esry , Nace Layadi , Sylvia Marci Luque , Simon John Molloy , Mario Pita
发明人： Thomas Craig Esry , Nace Layadi , Sylvia Marci Luque , Simon John Molloy , Mario Pita
IPC分类号： H01L213065
CPC分类号： H01L21/0337 , H01L21/0338 , H01L21/31116 , H01L21/32139
摘要： A process for forming a patterned film structure within a semiconductor device. The process sequentially forms a pattern within a hardmask film and than within a semiconductor or other film formed beneath the hardmask film. The etch bias of both isolated and nested features formed within the films, is substantially the same with respect to a masking film formed over the hardmask film. The process includes a hardmask film etching sequence including an argon treatment step and a hardmask film etching step which is resistant to localized etching effects and includes O2 and C2F6 as etchant gasses.
摘要翻译：一种用于在半导体器件内形成图案化膜结构的工艺。该过程在硬掩模膜内依次形成图案，而不是形成在硬掩膜下方的半导体或其它膜内。在膜内形成的隔离和嵌套特征的蚀刻偏压对于在硬掩模膜上形成的掩模膜基本相同。该方法包括硬掩模膜蚀刻序列，其包括氩处理步骤和耐局部蚀刻效应的硬掩模膜蚀刻步骤，并且包括作为蚀刻剂气体的O 2和C 2 F 6。

17. 发明授权

US06218255B1 Method of making a capacitor 有权
标题翻译：制作电容器的方法
公开(公告)号：US06218255B1
公开(公告)日：2001-04-17
申请号：US09277778
申请日：1999-03-29
申请人： Larry Bruce Fritzinger , Nace Layadi , Sailesh Mansinh Merchant , Pradip Kumar Roy
发明人： Larry Bruce Fritzinger , Nace Layadi , Sailesh Mansinh Merchant , Pradip Kumar Roy
IPC分类号： H01L2120
CPC分类号： H01L28/60 , H01L21/3212 , H01L21/32136 , H01L27/1085 , H01L28/40 , H01L28/75 , H01L28/90
摘要： The present invention provides a method for fabricating a capacitor, comprising the steps of forming a trench in a substrate, forming a layer of a first material selected from the group consisting of titanium and titanium nitride in the trench, filling the trench with a conductive material to form a conductive plug, planarizing the substrate, patterning the substrate to partially expose the first material and to create a top portion and a bottom portion to the plug, wherein the bottom portion is in the substrate, and removing the first material from the top portion of the plug.
摘要翻译：本发明提供一种制造电容器的方法，包括以下步骤：在衬底中形成沟槽，在沟槽中形成从由钛和氮化钛组成的组中选择的第一材料的层，用导电材料填充沟槽以形成导电插塞，平坦化基板，图案化基板以部分地暴露第一材料并且产生到插头的顶部部分和底部部分，其中底部部分在基板中，并且从顶部移除第一材料插头的一部分。

18. 发明授权

US06180518B2 Method for forming vias in a low dielectric constant material 有权
标题翻译：在低介电常数材料中形成通孔的方法
公开(公告)号：US06180518B2
公开(公告)日：2001-01-30
申请号：US09430226
申请日：1999-10-29
申请人： Nace Layadi , Sailesh Mansinh Merchant , Simon John Molloy , Pradip Kumar Roy
发明人： Nace Layadi , Sailesh Mansinh Merchant , Simon John Molloy , Pradip Kumar Roy
IPC分类号： H01L214763
CPC分类号： H01L21/02063 , H01L21/31138 , H01L21/76802 , H01L21/76814 , H01L21/76831
摘要： A method for making a semiconductor device includes the steps of forming a first conductive layer adjacent a substrate, forming an etch stop layer on the conductive layer, and forming a dielectric layer on the etch stop layer. The dielectric layer includes a material having a low dielectric constant, and a via is formed through the dielectric layer to expose the etch stop layer at the bottom, with porous sidewalls being produced. The exposed etch stop layer is etched using an etchant that cooperates with etched material from the etch stop layer to form a polymeric layer to coat the porous sidewalls of the via. Since the etchant cooperates with the etched material from the etch stop layer to form the polymeric layer coating the porous sidewalls of the via, a separate coating layer deposition step is not required after the via is etched and cleaned. After the porous sidewalls have been coated and polymeric material has been etched from the bottom of the via, a barrier metal layer is formed on the polymeric layer, a seed layer is formed on the barrier metal layer, and a second conductive layer is formed on the seed layer contacting the first conductive layer in the via.
摘要翻译：制造半导体器件的方法包括以下步骤：在衬底附近形成第一导电层，在导电层上形成蚀刻停止层，并在蚀刻停止层上形成介电层。电介质层包括具有低介电常数的材料，并且通过介电层形成通孔以暴露底部的蚀刻停止层，产生多孔侧壁。使用与蚀刻停止层的蚀刻材料配合的蚀刻剂来蚀刻暴露的蚀刻停止层，以形成聚合物层以涂覆通孔的多孔侧壁。由于蚀刻剂与来自蚀刻停止层的蚀刻材料配合以形成涂覆通孔的多孔侧壁的聚合物层，在蚀刻和清洁通孔之后不需要单独的涂层沉积步骤。在已经涂覆多孔侧壁并且已经从通孔的底部蚀刻聚合物材料之后，在聚合物层上形成阻挡金属层，在阻挡金属层上形成种子层，并且在第二导电层上形成第二导电层种子层与通孔中的第一导电层接触。

19. 发明申请

US20050106835A1 Trench isolation structure and method of manufacture therefor 审中-公开
标题翻译：沟槽隔离结构及其制造方法
公开(公告)号：US20050106835A1
公开(公告)日：2005-05-19
申请号：US10716278
申请日：2003-11-18
申请人： Nace Layadi , Alvaro Maury
发明人： Nace Layadi , Alvaro Maury
IPC分类号： H01L21/762 , H01L21/8234 , H01L21/76
CPC分类号： H01L21/76224 , H01L21/823481
摘要： The present invention provides a trench isolation structure, a method for manufacturing a trench isolation structure, and a method for manufacturing an integrated circuit including the trench isolation structure. The trench isolation structure, in accordance with the principles of the present invention, may include a substrate having a trench located therein, and an isolation material located within the trench, wherein the isolation material has no undercut at corners where the isolation material meets the substrate.
摘要翻译：本发明提供一种沟槽隔离结构，一种用于制造沟槽隔离结构的方法，以及一种用于制造包括沟槽隔离结构的集成电路的方法。根据本发明的原理，沟槽隔离结构可以包括其中具有沟槽的衬底和位于沟槽内的隔离材料，其中隔离材料在隔离材料与衬底相遇的拐角处没有底切。

20. 发明授权

US06730600B2 Method of dry etching a semiconductor device in the absence of a plasma 有权
标题翻译：在不存在等离子体的情况下干法蚀刻半导体器件的方法
公开(公告)号：US06730600B2
公开(公告)日：2004-05-04
申请号：US10259256
申请日：2002-09-27
申请人： Nace Layadi , Simon John Molloy , Sailesh Mansinh Merchant , Isik C. Kizilyalli
发明人： Nace Layadi , Simon John Molloy , Sailesh Mansinh Merchant , Isik C. Kizilyalli
IPC分类号： H01L21465
CPC分类号： H01L21/32135 , C23F1/12
摘要： A method for dry etching a material deposited on semiconductor device is performed by chemically reacting the material with an etchant gas. The etching process is conducted in a reaction chamber at a predetermined temperature and predetermined pressure within the reaction chamber and without the need of generating a plasma within the chamber or applying an electrical bias to the semiconductor device. A sufficient amount of gas is introduced into the reaction chamber to selectively remove the material from the semiconductor device.
摘要翻译：通过使材料与蚀刻剂气体化学反应来进行用于干蚀刻沉积在半导体器件上的材料的方法。蚀刻工艺在反应室内以预定温度和预定压力在反应室内进行，而不需要在室内产生等离子体或向半导体器件施加电偏压。将足够量的气体引入反应室以选择性地从半导体器件中去除材料。

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