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11. 发明授权

US07359272B2 Circuit and method for an SRAM with reduced power consumption 有权
标题翻译：具有降低功耗的SRAM的电路和方法
公开(公告)号：US07359272B2
公开(公告)日：2008-04-15
申请号：US11506438
申请日：2006-08-18
申请人： Ping-Wei Wang , Yuh-Jier Mii
发明人： Ping-Wei Wang , Yuh-Jier Mii
IPC分类号： G11C7/00
CPC分类号： G11C11/413 , G11C8/08
摘要： A circuit and method for providing an SRAM memory with reduced power consumption, the SRAM memory particularly useful for embedding SRAM memory with other logic and memory functions in an integrated circuit. A lower supply voltage is provided to the peripheral circuitry for the SRAM memory. A level shifter circuit is provided coupled to the lower power supply and outputting a higher supply voltage. An array of SRAM memory cells that may comprise 4T, 6T or 8T static RAM memory cells are coupled to the higher supply voltage during read and write operations. Operating the peripheral circuitry of the SRAM memory at the lower supply voltage achieves reduced power consumption for the SRAM memory and the integrated circuit.
摘要翻译：一种用于提供具有降低功耗的SRAM存储器的电路和方法，该SRAM存储器特别适用于将具有其他逻辑和存储器功能的SRAM存储器嵌入集成电路中。向SRAM存储器的外围电路提供较低的电源电压。提供电平移位器电路，耦合到下电源并输出较高的电源电压。可以包括4T，6T或8T静态RAM存储器单元的SRAM存储器单元的阵列在读取和写入操作期间耦合到更高的电源电压。在较低电源电压下操作SRAM存储器的外围电路实现了SRAM存储器和集成电路的功耗降低。

12. 发明授权

US6114747A Process design for wafer edge in VLSI 有权
标题翻译： VLSI晶圆边缘的工艺设计
公开(公告)号：US6114747A
公开(公告)日：2000-09-05
申请号：US378500
申请日：1999-08-20
申请人： Zin-Chein Wei , Yuh-Jier Mii
发明人： Zin-Chein Wei , Yuh-Jier Mii
IPC分类号： H01L21/00 , H01L23/31 , H01L23/544 , H01L23/58 , H01L29/06
CPC分类号： H01L21/6715 , H01L23/3192 , H01L2924/0002
摘要： A wafer structure and method of forming a wafer structure with all of the dielectric material and conducting material films removed from the outer periphery of the wafer in order to protect the dielectric and conducting films from damage due to wafer handling, storage, or clamping. The dielectric or conducting material is removed from the wafer edge using wafer edge exposure or edge bead rinse methods. The wafer edge exposure method is carried out at the same time the dielectric or conducting layer is being patterned.
摘要翻译：一种晶片结构和方法，其形成具有从晶片的外周边移除的所有电介质材料和导电材料膜的晶片结构，以便保护电介质和导电膜免受由于晶片处理，存储或夹紧的损坏。使用晶片边缘曝光或边缘珠冲洗方法从晶片边缘去除电介质或导电材料。晶片边缘曝光方法是在电介质层或导电层被图案化的同时进行的。

13. 发明授权

US5966628A Process design for wafer edge in vlsi 失效
标题翻译： vlsi晶圆边缘的工艺设计
公开(公告)号：US5966628A
公开(公告)日：1999-10-12
申请号：US23050
申请日：1998-02-13
申请人： Zin-Chein Wei , Yuh-Jier Mii
发明人： Zin-Chein Wei , Yuh-Jier Mii
IPC分类号： H01L21/00 , H01L23/31 , H01L21/20
CPC分类号： H01L21/6715 , H01L23/3192 , H01L2924/0002
摘要： A wafer structure and method of forming a wafer structure with all of the dielectric material and conducting material films removed from the outer periphery of the wafer in order to protect the dielectric and conducting films from damage due to wafer handling, storage, or clamping. The dielectric or conducting material is removed from the wafer edge using wafer edge exposure or edge bead rinse methods. The wafer edge exposure method is carried out at the same time the dielectric or conducting layer is being patterned.
摘要翻译：一种晶片结构和方法，其形成具有从晶片的外周边移除的所有电介质材料和导电材料膜的晶片结构，以便保护电介质和导电膜免受由于晶片处理，存储或夹紧的损坏。使用晶片边缘曝光或边缘珠冲洗方法从晶片边缘去除电介质或导电材料。晶片边缘曝光方法是在电介质层或导电层被图案化的同时进行的。

14. 发明授权

US08115500B2 Accurate capacitance measurement for ultra large scale integrated circuits 有权
标题翻译：超大规模集成电路的精确电容测量
公开(公告)号：US08115500B2
公开(公告)日：2012-02-14
申请号：US13015117
申请日：2011-01-27
申请人： Yih-Yuh Doong , Keh-Jeng Chang , Yuh-Jier Mii , Sally Liu , Lien Jung Hung , Victor Chih Yuan Chang
发明人： Yih-Yuh Doong , Keh-Jeng Chang , Yuh-Jier Mii , Sally Liu , Lien Jung Hung , Victor Chih Yuan Chang
IPC分类号： G01R31/28
CPC分类号： G01R31/2853 , G01R31/2884 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： Test structures and methods for measuring contact and via parasitic capacitance in an integrated circuit are provided. The accuracy of contact and via capacitance measurements are improved by eliminating not-to-be-measured capacitance from the measurement results. The capacitance is measured on a target test structure that has to-be-measured contact or via capacitance. Measurements are then repeated on a substantially similar reference test structure that is free of to-be-measured contact or via capacitances. By using the capacitance measurements of the two test structures, the to-be-measured contact and via capacitance can be calculated.
摘要翻译：提供了用于测量集成电路中的接触和通过寄生电容的测试结构和方法。通过从测量结果中消除不被测量的电容，提高了接触和通孔电容测量的精度。电容是在必须测量的接触或电容的目标测试结构上测量的。然后在基本相似的参考测试结构上重复测量，该测试结构不受测量的接触或通过电容。通过使用两个测试结构的电容测量，可以计算待测量的接触和通孔电容。

15. 发明授权

US07826252B2 Read-preferred SRAM cell design 有权
标题翻译：读取优先的SRAM单元设计
公开(公告)号：US07826252B2
公开(公告)日：2010-11-02
申请号：US12201725
申请日：2008-08-29
申请人： Ping-Wei Wang , Yuh-Jier Mii , Hung-Jen Liao
发明人： Ping-Wei Wang , Yuh-Jier Mii , Hung-Jen Liao
IPC分类号： G11C11/00
CPC分类号： G11C11/412 , H01L21/26586 , H01L29/66659
摘要： A method for operating a static random access memory (SRAM) cell includes providing the SRAM cell having a static read margin and a static write margin, wherein the static read margin is greater than the static write margin; applying a dynamic power to perform a write operation on the SRAM cell; and applying a static power to perform a read operation on the SRAM cell.
摘要翻译：一种用于操作静态随机存取存储器（SRAM）单元的方法包括提供具有静态读取余量和静态写入裕度的SRAM单元，其中静态读取余量大于静态写入余量; 施加动态功率以对SRAM单元执行写入操作; 并施加静态电力以对SRAM单元执行读取操作。

16. 发明申请

US20060091566A1 Bond pad structure for integrated circuit chip 审中-公开
标题翻译：用于集成电路芯片的焊盘结构
公开(公告)号：US20060091566A1
公开(公告)日：2006-05-04
申请号：US10989481
申请日：2004-11-16
申请人： Chin-Tien Yang , Shou Chang , Min Cao , Yuh-Jier Mii
发明人： Chin-Tien Yang , Shou Chang , Min Cao , Yuh-Jier Mii
IPC分类号： H01L23/48
CPC分类号： H01L24/05 , H01L24/45 , H01L2224/04042 , H01L2224/05093 , H01L2224/05552 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05666 , H01L2224/05681 , H01L2224/05684 , H01L2224/45124 , H01L2224/45144 , H01L2224/48624 , H01L2224/48639 , H01L2224/48644 , H01L2224/48647 , H01L2224/48655 , H01L2224/48666 , H01L2224/48681 , H01L2224/48684 , H01L2224/48724 , H01L2224/48739 , H01L2224/48744 , H01L2224/48747 , H01L2224/48755 , H01L2224/48766 , H01L2224/48781 , H01L2224/48784 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01022 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01073 , H01L2924/01074 , H01L2924/01079 , H01L2924/01327 , H01L2924/014 , H01L2924/14 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/30105 , H01L2924/00014 , H01L2924/00012 , H01L2924/00
摘要： An integrated circuit chip is provided, which includes a bond pad structure, a low-k dielectric layer, and active circuits. The bond pad structure includes a conductive bond pad, an Mtop solid conductive plate, and an Mtop−1 solid conductive plate. The Mtop solid conductive plate is located under the bond pad. The Mtop plate is electrically coupled to the bond pad. The Mtop−1 solid conductive plate is located under the Mtop plate. A low-k dielectric layer is located under the bond pad of the bond pad structure. At least part of an active circuit is located under the bond pad of the bond pad structure.
摘要翻译：提供了一种集成电路芯片，其包括接合焊盘结构，低k电介质层和有源电路。接合焊盘结构包括导电接合焊盘，M＆lt;顶部＆lt;固体导电板和M＆lt;顶1实心导电板。 M＆lt;＆gt;顶部<！ - SIPO - >固体导电板位于接合焊盘下方。 M＆lt;顶部板电连接到接合焊盘。 M＆lt; 1＆gt;顶部实体导电板位于M＆lt;顶部板下方。低k电介质层位于接合焊盘结构的接合焊盘下方。有源电路的至少一部分位于接合焊盘结构的接合焊盘的下方。

17. 发明授权

US09496217B2 Method and apparatus of forming a via 有权
标题翻译：形成通孔的方法和装置
公开(公告)号：US09496217B2
公开(公告)日：2016-11-15
申请号：US12478619
申请日：2009-06-04
申请人： Hsin-Yi Tsai , Chih-Hao Chen , Ming-Chung Liang , Chii-Ping Chen , Lai Chien Wen , Yuh-Jier Mii
发明人： Hsin-Yi Tsai , Chih-Hao Chen , Ming-Chung Liang , Chii-Ping Chen , Lai Chien Wen , Yuh-Jier Mii
IPC分类号： H01L23/522 , H01L21/768
CPC分类号： H01L23/5226 , H01L21/76804 , H01L21/76811 , H01L21/76813 , H01L21/76816 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： The present disclosure provides a semiconductor device that includes, a substrate; a first conductive line located over the substrate and extending along a first axis, the first conductive line having a first length and a first width, the first length being measured along the first axis; a second conductive line located over the first conductive line and extending along a second axis different from the first axis, the second conductive line having a second length and a second width, the second length being measured along the second axis; and a via coupling the first and second conductive lines, the via having an upper surface that contacts the second conductive line and a lower surface that contacts the first conductive line. The via has an approximately straight edge at the upper surface, the straight edge extending along the second axis and being substantially aligned with the second conductive line.
摘要翻译：本公开提供一种半导体器件，其包括：衬底; 第一导电线，位于所述衬底上并且沿着第一轴线延伸，所述第一导电线具有第一长度和第一宽度，所述第一长度沿着所述第一轴线被测量; 第二导电线，位于第一导电线之上并沿着不同于第一轴的第二轴延伸，第二导线具有第二长度和第二宽度，第二长度沿第二轴线测量; 以及耦合所述第一和第二导线的通孔，所述通孔具有接触所述第二导电线的上表面和接触所述第一导线的下表面。通孔在上表面具有大致直边，直边沿第二轴线延伸并与第二导线基本对准。

18. 发明申请

US20120074498A1 METHOD AND APPARATUS FOR IMPROVING GATE CONTACT 有权
标题翻译：改善门接触的方法和装置
公开(公告)号：US20120074498A1
公开(公告)日：2012-03-29
申请号：US12890995
申请日：2010-09-27
申请人： Harry Hak-Lay Chuang , Chih-Yang Yeh , Bao-Ru Young , Yuh-Jier Mii
发明人： Harry Hak-Lay Chuang , Chih-Yang Yeh , Bao-Ru Young , Yuh-Jier Mii
IPC分类号： H01L21/762 , H01L27/088
CPC分类号： H01L29/78 , H01L21/76224 , H01L21/76232 , H01L21/823456 , H01L21/823475 , H01L21/823481 , H01L27/088
摘要： A method of fabricating a semiconductor device includes providing a substrate having a first surface, forming an isolation structure disposed partly in the substrate and having an second surface higher than the first surface by a step height, removing a portion of the isolation structure to form a recess therein having a bottom surface disposed below the first surface, and forming a contact engaging the gate structure over the recess. A different aspect involves an apparatus that includes a substrate having a first surface, an isolation structure disposed partly in the substrate and having a second surface higher than the first surface by a step height, a recess extending downwardly from the second surface, the recess having a bottom surface disposed below the first surface, a gate structure, and a contact engaging the gate structure over the recess.
摘要翻译：一种制造半导体器件的方法包括提供具有第一表面的衬底，形成部分地设置在衬底中的隔离结构，并且具有高于第一表面的第二表面，台阶高度，去除隔离结构的一部分以形成在其中具有设置在第一表面下方的底表面的凹槽，以及形成在凹部上方接合栅极结构的触点。不同的方面涉及一种装置，其包括具有第一表面的衬底，部分地设置在衬底中的隔离结构，并且具有比第一表面高的台阶高度的第二表面;从第二表面向下延伸的凹部，凹部具有设置在第一表面下方的底表面，栅极结构，以及在凹部上接合栅极结构的触点。

19. 发明申请

US20110140203A1 NOVEL CONTACT IMPLEMENT STRUCTURE FOR HIGH DENSITY DESIGN 有权
标题翻译：高密度设计的新型接触实施结构
公开(公告)号：US20110140203A1
公开(公告)日：2011-06-16
申请号：US12701649
申请日：2010-02-08
申请人： Yung-Chin Hou , Yuh-Jier Mii , Kuo-Tung Sung , Li-Chun Tien
发明人： Yung-Chin Hou , Yuh-Jier Mii , Kuo-Tung Sung , Li-Chun Tien
IPC分类号： H01L27/06
CPC分类号： H01L27/0207 , H01L21/823871 , H01L29/4238 , Y10S257/90
摘要： The present disclosure provides a device in an integrated circuit. The device includes an active region in a semiconductor substrate; an isolation region adjacent the active region; a gate disposed on the active region and extending to the isolation region in a first direction; and a gate contact disposed within the isolation region, having a portion directly overlying and contacting the gate, and having a geometry horizontally extending to a first dimension in the first direction and a second dimension in a second direction approximately perpendicular to the first direction. The first dimension is greater than the second dimension.
摘要翻译：本公开提供了一种集成电路中的器件。该器件包括半导体衬底中的有源区; 邻近有源区的隔离区; 设置在所述有源区上并在第一方向延伸到所述隔离区的栅极; 以及设置在所述隔离区域内的栅极接触件，其具有直接覆盖并接触所述栅极的部分，并且具有水平延伸到所述第一方向上的第一尺寸的几何形状，以及大致垂直于所述第一方向的第二方向的第二尺寸。第一个维度大于第二个维度。

20. 发明授权

US07880494B2 Accurate capacitance measurement for ultra large scale integrated circuits 有权
标题翻译：超大规模集成电路的精确电容测量
公开(公告)号：US07880494B2
公开(公告)日：2011-02-01
申请号：US12715739
申请日：2010-03-02
申请人： Yih-Yuh Doong , Keh-Jeng Chang , Yuh-Jier Mii , Sally Liu , Lien Jung Hung , Victor Chih Yuan Chang
发明人： Yih-Yuh Doong , Keh-Jeng Chang , Yuh-Jier Mii , Sally Liu , Lien Jung Hung , Victor Chih Yuan Chang
IPC分类号： G01R31/26
CPC分类号： G01R31/2853 , G01R31/2884 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： Test structures and methods for measuring contact and via parasitic capacitance in an integrated circuit are provided. The accuracy of contact and via capacitance measurements are improved by eliminating not-to-be-measured capacitance from the measurement results. The capacitance is measured on a target test structure that has to-be-measured contact or via capacitance. Measurements are then repeated on a substantially similar reference test structure that is free of to-be-measured contact or via capacitances. By using the capacitance measurements of the two test structures, the to-be-measured contact and via capacitance can be calculated.
摘要翻译：提供了用于测量集成电路中的接触和通过寄生电容的测试结构和方法。通过从测量结果中消除不被测量的电容，提高了接触和通孔电容测量的精度。电容是在必须测量的接触或电容的目标测试结构上测量的。然后在基本相似的参考测试结构上重复测量，该测试结构不受测量的接触或通过电容。通过使用两个测试结构的电容测量，可以计算待测量的接触和通孔电容。

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