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1. 发明授权

US08115500B2 Accurate capacitance measurement for ultra large scale integrated circuits 有权
标题翻译：超大规模集成电路的精确电容测量
公开(公告)号：US08115500B2
公开(公告)日：2012-02-14
申请号：US13015117
申请日：2011-01-27
申请人： Yih-Yuh Doong , Keh-Jeng Chang , Yuh-Jier Mii , Sally Liu , Lien Jung Hung , Victor Chih Yuan Chang
发明人： Yih-Yuh Doong , Keh-Jeng Chang , Yuh-Jier Mii , Sally Liu , Lien Jung Hung , Victor Chih Yuan Chang
IPC分类号： G01R31/28
CPC分类号： G01R31/2853 , G01R31/2884 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： Test structures and methods for measuring contact and via parasitic capacitance in an integrated circuit are provided. The accuracy of contact and via capacitance measurements are improved by eliminating not-to-be-measured capacitance from the measurement results. The capacitance is measured on a target test structure that has to-be-measured contact or via capacitance. Measurements are then repeated on a substantially similar reference test structure that is free of to-be-measured contact or via capacitances. By using the capacitance measurements of the two test structures, the to-be-measured contact and via capacitance can be calculated.
摘要翻译：提供了用于测量集成电路中的接触和通过寄生电容的测试结构和方法。通过从测量结果中消除不被测量的电容，提高了接触和通孔电容测量的精度。电容是在必须测量的接触或电容的目标测试结构上测量的。然后在基本相似的参考测试结构上重复测量，该测试结构不受测量的接触或通过电容。通过使用两个测试结构的电容测量，可以计算待测量的接触和通孔电容。

2. 发明授权

US07880494B2 Accurate capacitance measurement for ultra large scale integrated circuits 有权
标题翻译：超大规模集成电路的精确电容测量
公开(公告)号：US07880494B2
公开(公告)日：2011-02-01
申请号：US12715739
申请日：2010-03-02
申请人： Yih-Yuh Doong , Keh-Jeng Chang , Yuh-Jier Mii , Sally Liu , Lien Jung Hung , Victor Chih Yuan Chang
发明人： Yih-Yuh Doong , Keh-Jeng Chang , Yuh-Jier Mii , Sally Liu , Lien Jung Hung , Victor Chih Yuan Chang
IPC分类号： G01R31/26
CPC分类号： G01R31/2853 , G01R31/2884 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： Test structures and methods for measuring contact and via parasitic capacitance in an integrated circuit are provided. The accuracy of contact and via capacitance measurements are improved by eliminating not-to-be-measured capacitance from the measurement results. The capacitance is measured on a target test structure that has to-be-measured contact or via capacitance. Measurements are then repeated on a substantially similar reference test structure that is free of to-be-measured contact or via capacitances. By using the capacitance measurements of the two test structures, the to-be-measured contact and via capacitance can be calculated.
摘要翻译：提供了用于测量集成电路中的接触和通过寄生电容的测试结构和方法。通过从测量结果中消除不被测量的电容，提高了接触和通孔电容测量的精度。电容是在必须测量的接触或电容的目标测试结构上测量的。然后在基本相似的参考测试结构上重复测量，该测试结构不受测量的接触或通过电容。通过使用两个测试结构的电容测量，可以计算待测量的接触和通孔电容。

3. 发明申请

US20100156453A1 Accurate Capacitance Measurement for Ultra Large Scale Integrated Circuits 有权
标题翻译：超大规模集成电路的精确电容测量
公开(公告)号：US20100156453A1
公开(公告)日：2010-06-24
申请号：US12715739
申请日：2010-03-02
申请人： Yih-Yuh Doong , Keh-Jeng Chang , Yuh-Jier Mii , Sally Liu , Lien Jung Hung , Victor Chih Yuan Chang
发明人： Yih-Yuh Doong , Keh-Jeng Chang , Yuh-Jier Mii , Sally Liu , Lien Jung Hung , Victor Chih Yuan Chang
IPC分类号： G01R31/26 , G01R27/26
CPC分类号： G01R31/2853 , G01R31/2884 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： Test structures and methods for measuring contact and via parasitic capacitance in an integrated circuit are provided. The accuracy of contact and via capacitance measurements are improved by eliminating not-to-be-measured capacitance from the measurement results. The capacitance is measured on a target test structure that has to-be-measured contact or via capacitance. Measurements are then repeated on a substantially similar reference test structure that is free of to-be-measured contact or via capacitances. By using the capacitance measurements of the two test structures, the to-be-measured contact and via capacitance can be calculated.
摘要翻译：提供了用于测量集成电路中的接触和通过寄生电容的测试结构和方法。通过从测量结果中消除不被测量的电容，提高了接触和通孔电容测量的精度。电容是在必须测量的接触或电容的目标测试结构上测量的。然后在基本相似的参考测试结构上重复测量，该测试结构不受测量的接触或通过电容。通过使用两个测试结构的电容测量，可以计算待测量的接触和通孔电容。

4. 发明申请

US20110168995A1 Accurate Capacitance Measurement for Ultra Large Scale Integrated Circuits 有权
标题翻译：超大规模集成电路的精确电容测量
公开(公告)号：US20110168995A1
公开(公告)日：2011-07-14
申请号：US13015117
申请日：2011-01-27
申请人： Yih-Yuh Doong , Keh-Jeng Chang , Yuh-Jier Mii , Sally Liu , Lien Jung Hung , Victor Chih Yuan Chang
发明人： Yih-Yuh Doong , Keh-Jeng Chang , Yuh-Jier Mii , Sally Liu , Lien Jung Hung , Victor Chih Yuan Chang
IPC分类号： H01L23/544
CPC分类号： G01R31/2853 , G01R31/2884 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： Test structures and methods for measuring contact and via parasitic capacitance in an integrated circuit are provided. The accuracy of contact and via capacitance measurements are improved by eliminating not-to-be-measured capacitance from the measurement results. The capacitance is measured on a target test structure that has to-be-measured contact or via capacitance. Measurements are then repeated on a substantially similar reference test structure that is free of to-be-measured contact or via capacitances. By using the capacitance measurements of the two test structures, the to-be-measured contact and via capacitance can be calculated.
摘要翻译：提供了用于测量集成电路中的接触和通过寄生电容的测试结构和方法。通过从测量结果中消除不被测量的电容，提高了接触和通孔电容测量的精度。电容是在必须测量的接触或电容的目标测试结构上测量的。然后在基本相似的参考测试结构上重复测量，该测试结构不受测量的接触或通过电容。通过使用两个测试结构的电容测量，可以计算待测量的接触和通孔电容。

5. 发明授权

US07772868B2 Accurate capacitance measurement for ultra large scale integrated circuits 有权
标题翻译：超大规模集成电路的精确电容测量
公开(公告)号：US07772868B2
公开(公告)日：2010-08-10
申请号：US11966653
申请日：2007-12-28
申请人： Yih-Yuh Doong , Keh-Jeng Chang , Yuh-Jier Mii , Sally Liu , Lien Jung Hung , Victor Chih Yuan Chang
发明人： Yih-Yuh Doong , Keh-Jeng Chang , Yuh-Jier Mii , Sally Liu , Lien Jung Hung , Victor Chih Yuan Chang
IPC分类号： G01R31/26
CPC分类号： G01R31/2853 , G01R31/2884 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： Test structures and methods for measuring contact and via parasitic capacitance in an integrated circuit are provided. The accuracy of contact and via capacitance measurements are improved by eliminating not-to-be-measured capacitance from the measurement results. The capacitance is measured on a target test structure that has to-be-measured contact or via capacitance. Measurements are then repeated on a substantially similar reference test structure that is free of to-be-measured contact or via capacitances. By using the capacitance measurements of the two test structures, the to-be-measured contact and via capacitance can be calculated.
摘要翻译：提供了用于测量集成电路中的接触和通过寄生电容的测试结构和方法。通过从测量结果中消除不被测量的电容，提高了接触和通孔电容测量的精度。电容是在必须测量的接触或电容的目标测试结构上测量的。然后在基本相似的参考测试结构上重复测量，该测试结构不受测量的接触或通过电容。通过使用两个测试结构的电容测量，可以计算待测量的接触和通孔电容。

6. 发明申请

US20090002012A1 Accurate Capacitance Measurement for Ultra Large Scale Integrated Circuits 有权
标题翻译：超大规模集成电路的精确电容测量
公开(公告)号：US20090002012A1
公开(公告)日：2009-01-01
申请号：US11966653
申请日：2007-12-28
申请人： Yih-Yuh Doong , Keh-Jeng Chang , Yuh-Jier Mii , Sally Liu , Lien Jung Hung , Victor Chih Yuan Chang
发明人： Yih-Yuh Doong , Keh-Jeng Chang , Yuh-Jier Mii , Sally Liu , Lien Jung Hung , Victor Chih Yuan Chang
IPC分类号： G01R31/26 , H01L23/58
CPC分类号： G01R31/2853 , G01R31/2884 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： Test structures and methods for measuring contact and via parasitic capacitance in an integrated circuit are provided. The accuracy of contact and via capacitance measurements are improved by eliminating not-to-be-measured capacitance from the measurement results. The capacitance is measured on a target test structure that has to-be-measured contact or via capacitance. Measurements are then repeated on a substantially similar reference test structure that is free of to-be-measured contact or via capacitances. By using the capacitance measurements of the two test structures, the to-be-measured contact and via capacitance can be calculated.
摘要翻译：提供了用于测量集成电路中的接触和通过寄生电容的测试结构和方法。通过从测量结果中消除不被测量的电容，提高了接触和通孔电容测量的精度。电容是在必须测量的接触或电容的目标测试结构上测量的。然后在基本相似的参考测试结构上重复测量，该测试结构不受测量的接触或通过电容。通过使用两个测试结构的电容测量，可以计算待测量的接触和通孔电容。

7. 发明申请

US20130032799A1 Apparatus and Methods for De-Embedding Through Substrate Vias 有权
标题翻译：通过基板通孔去嵌入的装置和方法
公开(公告)号：US20130032799A1
公开(公告)日：2013-02-07
申请号：US13197602
申请日：2011-08-03
申请人： Hsiao-Tsung Yen , Yu-Ling Lin , Chin-Wei Kuo , Victor Chih Yuan Chang , Min-Chie Jeng
发明人： Hsiao-Tsung Yen , Yu-Ling Lin , Chin-Wei Kuo , Victor Chih Yuan Chang , Min-Chie Jeng
IPC分类号： H01L23/528 , H01L21/66
CPC分类号： G01R31/2644 , H01L22/34 , H01L23/481 , H01L2924/0002 , H01L2924/00
摘要： A method includes providing on a substrate having at least two through substrate vias (“TSVs”) a plurality of test structures for de-embedding the measurement of the intrinsic characteristics of a device under test (DUT) including at least two of the TSVs; measuring the intrinsic characteristics [L] for a first and a second test structure on the substrate including two pads coupled with a transmission line of length L; using simultaneous solutions of ABCD matrix or T matrix form equations, and the measured intrinsic characteristics, solving for the intrinsic characteristics of the pads and the transmission lines; de-embedding the measurements of the third and fourth test structures using the intrinsic characteristics of the pads and the transmission lines; and using simultaneous solutions of ABCD matrix or T matrix form equations for BM_L and BM_LX, and the measured intrinsic characteristics, solving for the intrinsic characteristics of the TSVs.
摘要翻译：一种方法包括在具有至少两个通过衬底通孔（TSV）的衬底上提供多个测试结构，用于对包括至少两个TSV的被测器件（DUT）的固有特性的测量进行解嵌入; 测量包括与长度为L的传输线耦合的两个焊盘的衬底上的第一和第二测试结构的固有特性[L] 使用ABCD矩阵或T矩阵形式方程的同时解，以及测量的固有特性，求解焊盘和传输线的固有特性; 使用焊盘和传输线的固有特性来解嵌第三和第四测试结构的测量; 并且对于BM_L和BM_LX使用ABCD矩阵或T矩阵形式方程的同时解，以及测量的固有特性，求解TSV的固有特性。

8. 发明授权

US08809073B2 Apparatus and methods for de-embedding through substrate vias 有权
标题翻译：用于通过衬底通孔去嵌入的装置和方法
公开(公告)号：US08809073B2
公开(公告)日：2014-08-19
申请号：US13197602
申请日：2011-08-03
申请人： Hsiao-Tsung Yen , Yu-Ling Lin , Chin-Wei Kuo , Victor Chih Yuan Chang , Min-Chie Jeng
发明人： Hsiao-Tsung Yen , Yu-Ling Lin , Chin-Wei Kuo , Victor Chih Yuan Chang , Min-Chie Jeng
IPC分类号： H01L21/66 , G01R31/26
CPC分类号： G01R31/2644 , H01L22/34 , H01L23/481 , H01L2924/0002 , H01L2924/00
摘要： A method includes providing on a substrate having at least two through substrate vias (“TSVs”) a plurality of test structures for de-embedding the measurement of the intrinsic characteristics of a device under test (DUT) including at least two of the TSVs; measuring the intrinsic characteristics [L] for a first and a second test structure on the substrate including two pads coupled with a transmission line of length L; using simultaneous solutions of ABCD matrix or T matrix form equations, and the measured intrinsic characteristics, solving for the intrinsic characteristics of the pads and the transmission lines; de-embedding the measurements of the third and fourth test structures using the intrinsic characteristics of the pads and the transmission lines; and using simultaneous solutions of ABCD matrix or T matrix form equations for BM_L and BM_LX, and the measured intrinsic characteristics, solving for the intrinsic characteristics of the TSVs.
摘要翻译：一种方法包括在具有至少两个通过衬底通孔（“TSV”）的衬底上提供多个测试结构，用于对包括至少两个TSV的待测器件（DUT）的固有特性的测量进行解嵌入; 测量包括与长度为L的传输线耦合的两个焊盘的衬底上的第一和第二测试结构的固有特性[L] 使用ABCD矩阵或T矩阵形式方程的同时解，以及测量的固有特性，求解焊盘和传输线的固有特性; 使用焊盘和传输线的固有特性来解嵌第三和第四测试结构的测量; 并且对于BM_L和BM_LX使用ABCD矩阵或T矩阵形式方程的同时解，以及测量的固有特性，求解TSV的固有特性。

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