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11. 发明授权

US07045436B2 Method to engineer the inverse narrow width effect (INWE) in CMOS technology using shallow trench isolation (STI) 有权
公开(公告)号：US07045436B2
公开(公告)日：2006-05-16
申请号：US10899664
申请日：2004-07-27
申请人： Amitava Chatterjee , Alwin Tsao , Manuel Quevedo-Lopez , Jong Yoon , Shaoping Tang
发明人： Amitava Chatterjee , Alwin Tsao , Manuel Quevedo-Lopez , Jong Yoon , Shaoping Tang
IPC分类号： H01L21/762
CPC分类号： H01L21/76237 , H01L21/823878
摘要： A method (200) of forming an isolation structure is disclosed, and includes forming an isolation trench in a semiconductor body (214) associated with an isolation region, and filling a bottom portion of the isolation trench with an implant masking material (216). An angled ion implant is performed into the isolation trench (218) after having the bottom portion thereof filled with the implant masking material, thereby forming a threshold voltage compensation region in the semiconductor body. Subsequently, the isolation trench is filled with a dielectric material (220).

12. 发明申请

US20050059228A1 Integration of pre-S/D anneal selective nitride/oxide composite cap for improving transistor performance 有权
公开(公告)号：US20050059228A1
公开(公告)日：2005-03-17
申请号：US10662850
申请日：2003-09-15
申请人： Haowen Bu , Shashank Ekbote , Rajesh Khamankar , Shaoping Tang , Freidoon Mehrad
发明人： Haowen Bu , Shashank Ekbote , Rajesh Khamankar , Shaoping Tang , Freidoon Mehrad
IPC分类号： H01L21/00 , H01L21/3205 , H01L21/336 , H01L21/44 , H01L21/4763 , H01L21/8238 , H01L21/84 , H01L29/08 , H01L29/76 , H01L29/78
CPC分类号： H01L29/0847 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/7833 , H01L29/7845 , Y10S438/902
摘要： The present invention facilitates semiconductor device operation and fabrication by providing a cap-annealing process that improves channel electron mobility without substantially degrading PMOS transistor devices. The process uses an oxide/nitride composite-cap to alter the active dopant profile across the channel regions. During an annealing process, dopants migrate out of the Si/SiO2 in a channel region thereby altering the dopant profile of the channel region. This altered profile generally improves channel mobility thereby improving transistor performance and permitting smaller density designs.

13. 发明授权

US5830532A Method to produce ultrathin porous silicon-oxide layer 失效
标题翻译：生产超薄多孔氧化硅层的方法
公开(公告)号：US5830532A
公开(公告)日：1998-11-03
申请号：US819279
申请日：1997-03-18
申请人： Shaoping Tang , Robert M. Wallace , Yi Wei
发明人： Shaoping Tang , Robert M. Wallace , Yi Wei
IPC分类号： C23C8/10 , H01L21/316 , C23C16/40
CPC分类号： H01L21/02203 , C23C8/10 , H01L21/02238 , H01L21/02255 , H01L21/31695
摘要： A method for producing a porous film on a silicon substrate is described. The substrate 14 is placed in a vacuum chamber in the presence of oxygen at specified pressure and temperature for a period of time to form a thin oxide film 10 thereon. Then the conditions in the chamber are altered so that voids 14 of a desired dimension are formed in the oxide film 10. Alternatively, a substrate 20 is subjected to specific conditions in the vacuum chamber whereat oxide islands 22 nucleate on the surface. As the islands grow, they eventually cover most of the surface leaving voids 24 of the desired size.
摘要翻译：对硅基板上的多孔膜的制造方法进行说明。在特定压力和温度的氧气存在下将衬底14放置在真空室中一段时间以在其上形成薄氧化膜10。然后，改变腔室中的条件，使得在氧化物膜10中形成所需尺寸的空隙14.或者，衬底20在真空室中经受特定条件，其中氧化物岛22在表面上成核。当岛生长时，它们最终覆盖大部分表面，留下所需尺寸的空隙24。

14. 发明授权

US07691700B2 Multi-stage implant to improve device characteristics 有权
标题翻译：多级植入物以改善装置特性
公开(公告)号：US07691700B2
公开(公告)日：2010-04-06
申请号：US11769058
申请日：2007-06-27
申请人： Manoj Mehrotra , Stan Ashburn , Shaoping Tang
发明人： Manoj Mehrotra , Stan Ashburn , Shaoping Tang
IPC分类号： H01L21/8238
CPC分类号： G11C11/412 , H01L21/26513 , H01L21/823807 , H01L21/823814 , H01L27/11 , H01L27/1104 , H01L29/1083 , H01L29/7833
摘要： One aspect of the inventors' concept relates to a method of forming a semiconductor device. In this method, a gate structure is formed over a semiconductor body. A source/drain mask is patterned over the semiconductor body implanted source and drain regions are formed that are associated with the gate structure. After forming the implanted source and drain regions, a multi-stage implant is performed on the source and drain regions that comprises at least two implants where the dose and energy of the first implant varies from the dose and energy of the second implant. Other methods and devices are also disclosed.
摘要翻译：本发明人的概念的一个方面涉及形成半导体器件的方法。在该方法中，在半导体本体上形成栅极结构。源极/漏极掩模在半导体本体注入源上形成图案，并且形成与栅极结构相关联的漏极区。在形成植入的源区和漏区之后，在包括至少两个植入物的源极和漏极区域上执行多级注入，其中第一注入的剂量和能量与第二植入物的剂量和能量不同。还公开了其它方法和装置。

15. 发明授权

US07601575B2 Integration of pre-S/D anneal selective nitride/oxide composite cap for improving transistor performance 有权
标题翻译：用于改善晶体管性能的前S / D退火选择性氮化物/氧化物复合帽的集成
公开(公告)号：US07601575B2
公开(公告)日：2009-10-13
申请号：US11072779
申请日：2005-03-04
申请人： Haowen Bu , Shashank Ekbote , Rajesh Khamankar , Shaoping Tang , Freidoon Mehrad
发明人： Haowen Bu , Shashank Ekbote , Rajesh Khamankar , Shaoping Tang , Freidoon Mehrad
IPC分类号： H01L21/336 , H01L21/8234 , H01L21/44
CPC分类号： H01L29/0847 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/7833 , H01L29/7845 , Y10S438/902
摘要： The present invention facilitates semiconductor device operation and fabrication by providing a cap-annealing process that improves channel electron mobility without substantially degrading PMOS transistor devices. The process uses an oxide/nitride composite cap to alter the active dopant profile across the channel regions. During an annealing process, dopants migrate out of the Si/SiO2 in a channel region thereby altering the dopant profile of the channel region. This altered profile generally improves channel mobility thereby improving transistor performance and permitting smaller density designs.
摘要翻译：本发明通过提供一种提高沟道电子迁移率而不会使PMOS晶体管器件基本上衰减的帽退火工艺来促进半导体器件的操作和制造。该方法使用氧化物/氮化物复合帽来改变通道区域上的活性掺杂剂分布。在退火过程中，掺杂剂在沟道区中迁移出Si / SiO 2，从而改变沟道区的掺杂物分布。这种改变的形状通常改善了沟道迁移率，从而提高了晶体管的性能并允许更小的密度设计。

16. 发明授权

US06794730B2 High performance PNP bipolar device fully compatible with CMOS process 有权
标题翻译：高性能PNP双极器件完全兼容CMOS工艺
公开(公告)号：US06794730B2
公开(公告)日：2004-09-21
申请号：US10028002
申请日：2001-12-20
申请人： Youngmin Kim , Shaoping Tang , Seetharaman Sridhar , Amitava Chatterjee
发明人： Youngmin Kim , Shaoping Tang , Seetharaman Sridhar , Amitava Chatterjee
IPC分类号： H01L27082
CPC分类号： H01L29/66272 , H01L21/8249 , H01L29/0804
摘要： A pnp bipolar junction transistor is formed with improved emitter efficiency by reducing the depth of the p well implant to increase carrier concentration in the emitter and making the emitter junction deeper to increase minority lifetime in the emitter. The high gain BJT is formed without added mask steps to the process flow. A blanket high energy boron implant is used to suppress the isolation leakage in SRAM in the preferred embodiment.
摘要翻译：通过减小p阱注入的深度以增加发射极中的载流子浓度并使发射极结更深以增加发射极中的少数寿命，形成pnp双极结型晶体管，其具有改善的发射极效率。形成高增益BJT，而不对工艺流程添加掩模步骤。在优选实施例中，使用覆盖的高能量硼注入来抑制SRAM中的隔离泄漏。

17. 发明授权

US09773793B2 Transistor performance modification with stressor structures 有权
公开(公告)号：US09773793B2
公开(公告)日：2017-09-26
申请号：US12576310
申请日：2009-10-09
申请人： Scott R. Summerfelt , Rajni J. Aggarwal , Shaoping Tang
发明人： Scott R. Summerfelt , Rajni J. Aggarwal , Shaoping Tang
IPC分类号： H01L21/02 , H01L21/00 , H01L27/11507 , H01L49/02 , H01L29/78
CPC分类号： H01L27/11507 , H01L28/55 , H01L29/7833 , H01L29/7843
摘要： A transistor structure with stress enhancement geometry aligned above the channel region. Also, a transistor structure with stress enhancement geometries located above and aligned with opposite sides of the channel region. Furthermore, methods for fabricating integrated circuits containing transistors with stress enhancement geometries.

18. 发明授权

US08530298B2 Radiation hardened integrated circuit 有权
标题翻译：辐射硬化集成电路
公开(公告)号：US08530298B2
公开(公告)日：2013-09-10
申请号：US13286293
申请日：2011-11-01
申请人： Richard G. Roybal , Shariq Arshad , Shaoping Tang , James Fred Salzman
发明人： Richard G. Roybal , Shariq Arshad , Shaoping Tang , James Fred Salzman
IPC分类号： H01L21/8238 , H01L21/70
CPC分类号： H01L21/823892 , H01L27/0921 , H01L27/0928
摘要： A method of forming an integrated circuit (IC) includes providing a substrate having a topside semiconductor surface, wherein the topside semiconductor surface includes at least one of N+ buried layer regions and P+ buried layer regions. An epitaxial layer is grown on the topside semiconductor surface. Pwells are formed in the epitaxial layer. Nwells are formed in the epitaxial layer. NMOS devices are formed in and over the pwells, and PMOS devices are formed in and over the nwells.
摘要翻译：形成集成电路（IC）的方法包括提供具有顶侧半导体表面的衬底，其中顶侧半导体表面包括N +掩埋层区域和P +掩埋层区域中的至少一个。在顶侧半导体表面上生长外延层。孔在外延层中形成。 N外延层形成。 NMOS器件形成在阱的内部和上方，并且PMOS器件形成在n阱中和上方。

19. 发明申请

US20110084323A1 Transistor Performance Modification with Stressor Structures 有权
标题翻译：晶体管性能改进与应力结构
公开(公告)号：US20110084323A1
公开(公告)日：2011-04-14
申请号：US12576310
申请日：2009-10-09
申请人： Scott R. Summerfelt , Rajni J. Aggarwal , Shaoping Tang
发明人： Scott R. Summerfelt , Rajni J. Aggarwal , Shaoping Tang
IPC分类号： H01L27/06 , H01L21/02
CPC分类号： H01L27/11507 , H01L28/55 , H01L29/7833 , H01L29/7843
摘要： A transistor structure with stress enhancement geometry aligned above the channel region. Also, a transistor structure with stress enhancement geometries located above and aligned with opposite sides of the channel region. Furthermore, methods for fabricating integrated circuits containing transistors with stress enhancement geometries.
摘要翻译：具有应力增强几何形状的晶体管结构在通道区域上方对准。此外，具有应力增强几何形状的晶体管结构位于沟道区域的相对侧上方并与其对准。此外，制造含有具有应力增强几何形状的晶体管的集成电路的方法。

20. 发明授权

US07795085B2 Intentional pocket shadowing to compensate for the effects of cross-diffusion in SRAMs 有权
标题翻译：有意义的口袋阴影以补偿SRAM中交叉扩散的影响
公开(公告)号：US07795085B2
公开(公告)日：2010-09-14
申请号：US11451264
申请日：2006-06-12
申请人： Jong Shik Yoon , Amitava Chatterjee , Kayvan Sadra , Shaoping Tang
发明人： Jong Shik Yoon , Amitava Chatterjee , Kayvan Sadra , Shaoping Tang
IPC分类号： H01L21/8238
CPC分类号： H01L27/1104 , H01L27/11
摘要： Methods are disclosed for forming an SRAM cell having symmetrically implanted active regions and reduced cross-diffusion therein. One method comprises patterning a resist layer overlying a semiconductor substrate to form resist structures about symmetrically located on opposite sides of active regions of the cell, implanting one or more dopant species using a first implant using the resist structures as an implant mask, rotating the semiconductor substrate relative to the first implant by about 180 degrees, and implanting one or more dopant species into the semiconductor substrate with a second implant using the resist structures as an implant mask. A method of performing a symmetric angle implant is also disclosed to provide reduced cross-diffusion within the cell, comprising patterning equally spaced resist structures on opposite sides of the active regions of the cell to equally shadow laterally opposed first and second angled implants.
摘要翻译：公开了用于形成具有对称注入的有源区并在其中减少的交叉扩散的SRAM单元的方法。一种方法包括图案化覆盖在半导体衬底上的抗蚀剂层，以形成对称地位于电池的有源区的相对侧上的抗蚀剂结构，使用第一注入使用抗蚀剂结构作为注入掩模注入一种或多种掺杂物种，衬底，相对于第一注入约180度，以及使用抗蚀剂结构作为植入掩模，用第二注入将一种或多种掺杂剂物质注入到半导体衬底中。还公开了执行对称角度注入的方法，以在电池内提供减小的交叉扩散，包括在电池的有源区域的相对侧上图案化等间隔的抗蚀剂结构，以同样地遮蔽横向相对的第一和第二倾斜植入物。

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