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11. 发明授权

US07413959B2 Semiconductor device including a planarized surface and method thereof 失效
标题翻译：包括平面化表面的半导体器件及其方法
公开(公告)号：US07413959B2
公开(公告)日：2008-08-19
申请号：US10419076
申请日：2003-04-21
申请人： Jae-Dong Lee , Yong-Pil Han , Chang-Ki Hong
发明人： Jae-Dong Lee , Yong-Pil Han , Chang-Ki Hong
IPC分类号： H01L21/00
CPC分类号： H01L21/76224
摘要： A method of planarizing the surface of a semiconductor substrate to reduce the occurrence of a dishing phenomenon. A patterned etch stop layer defining a trench region is formed on a substrate. The substrate is etched to form a trench region, and a medium material layer and an oxide layer are subsequently formed on the substrate, filling the trench region. Chemical mechanical polishing (CMP) is performed on the oxide layer until the medium material layer is exposed. CMP is then performed until the patterned etch stop layer is exposed and a planarized oxide layer is formed. Because the medium material layer has a higher removal rate during CMP than the oxide layer, occurrences of the dishing phenomenon are reduced. A slurry including an anionic surfactant is used to increase the CMP removal ratio of the medium material layer to the oxide layer.
摘要翻译：平面化半导体衬底的表面以减少凹陷现象的发生的方法。限定沟槽区域的图案化蚀刻停止层形成在衬底上。蚀刻衬底以形成沟槽区域，随后在衬底上形成介质材料层和氧化物层，填充沟槽区域。在氧化物层上进行化学机械抛光（CMP），直到介质材料层露出。然后执行CMP直到图案化的蚀刻停止层被暴露并且形成平坦化的氧化物层。由于介质材料层在CMP期间具有比氧化物层更高的去除率，所以凹陷现象的发生减少。使用包含阴离子表面活性剂的浆料来提高介质材料层与氧化物层的CMP去除率。

12. 发明授权

US07338352B2 Slurry delivery system, chemical mechanical polishing apparatus and method for using the same 有权
标题翻译：浆料输送系统，化学机械抛光装置及其使用方法
公开(公告)号：US07338352B2
公开(公告)日：2008-03-04
申请号：US11434215
申请日：2006-05-16
申请人： Choong-Kee Seong , Chang-Ki Hong , Jae-Dong Lee
发明人： Choong-Kee Seong , Chang-Ki Hong , Jae-Dong Lee
IPC分类号： B24B1/00
CPC分类号： B01F5/0256 , B01F3/12 , B01F5/0413 , B01F5/0646 , B01F5/0654 , B01F5/0682 , B01F5/0688
摘要： A slurry delivery system, a chemical mechanical polishing (CMP) apparatus, and method for using the same are provided. An apparatus for supplying slurry to a polishing unit may include a first feed line through which an abrasive may be supplied at a first velocity. A velocity-changing member may be connected to the first feed line, and/or a velocity of the abrasive may be changed from the first velocity to. the second velocity different from the first velocity by the velocity-changing member. A second feed line may be connected to the velocity-changing member and/or an additive may be supplied through the second feed line. A supply line may be connected to the velocity-changing member. A slurry, which may be a mixture of the abrasive and/or the additive, may be supplied to a polishing unit through the supply line. Accordingly, the slurry may be more uniformly mixed and/or supplied to a polishing unit.
摘要翻译：提供浆料输送系统，化学机械抛光（CMP）装置及其使用方法。用于将浆料供应到抛光单元的装置可以包括第一进料管线，研磨剂可以通过第一进料管线以第一速度被供给。速度改变构件可以连接到第一进料管线，和/或磨料的速度可以从第一速度改变到。第二速度与速度变化构件的第一速度不同。第二进料管线可以连接到速度变化部件和/或可以通过第二进料管线供应添加剂。供应管线可以连接到速度变化构件。可以将研磨剂和/或添加剂的混合物的浆料通过供应管线供应到抛光单元。因此，浆料可以被更均匀地混合和/或提供给抛光单元。

13. 发明申请

US20050014330A1 Method of planarizing an interlayer dielectric layer 审中-公开
标题翻译：平面化层间电介质层的方法
公开(公告)号：US20050014330A1
公开(公告)日：2005-01-20
申请号：US10777864
申请日：2004-02-12
申请人： Young-Rae Park , Jae-Dong Lee , Joon Park , Chang-Ki Hong
发明人： Young-Rae Park , Jae-Dong Lee , Joon Park , Chang-Ki Hong
IPC分类号： H01L21/02 , H01L21/3105 , H01L21/4763 , H01L21/768 , H01L21/8242 , H01L27/108
CPC分类号： H01L27/10897 , H01L21/31053 , H01L21/76819 , H01L27/10817 , H01L27/10852 , H01L27/10894 , H01L28/91
摘要： A method of planarizing an interlayer dielectric layer formed over a one cylinder storage (OCS) capacitor including applying two or three interlayer dielectric layers over the capacitor and planarizing the interlayer dielectric layers using CMP having a different etching selectivity according to the layers.
摘要翻译：平面化在单缸存储（OCS）电容器上形成的层间电介质层的方法，包括在电容器上施加两个或三个层间电介质层，并使用根据层的具有不同蚀刻选择性的CMP平坦化层间电介质层。

14. 发明申请

US20090155991A1 Methods of fabricating a semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20090155991A1
公开(公告)日：2009-06-18
申请号：US12292195
申请日：2008-11-13
申请人： Jong-Won Lee , Sang-Yeob Han , Chang-Ki Hong , Bo-Un Yoon , Jae-Dong Lee
发明人： Jong-Won Lee , Sang-Yeob Han , Chang-Ki Hong , Bo-Un Yoon , Jae-Dong Lee
IPC分类号： H01L21/4763
CPC分类号： H01L21/76897 , H01L27/10855 , H01L27/10873 , H01L27/10888 , H01L29/6653
摘要： A method of fabricating a contact plug of a semiconductor device is provided, the method includes forming a gate pattern on a substrate, forming a capping pattern to cover an upper surface and sidewalls of the gate pattern, forming an interlayer insulation layer on the substrate such that the interlayer insulation layer exposes an upper surface of the capping pattern, and removing a portion of the capping pattern and the interlayer insulation layer such that the upper surface of the capping pattern is planarized.
摘要翻译：提供了制造半导体器件的接触插塞的方法，该方法包括在衬底上形成栅极图案，形成覆盖图案的上表面和侧壁的封盖图案，在衬底上形成层间绝缘层，如层间绝缘层暴露封盖图案的上表面，并且去除封盖图案和层间绝缘层的一部分，使得封盖图案的上表面被平坦化。

15. 发明申请

US20050075052A1 Method and system for planarizing integrated circuit material 有权
标题翻译：用于平面化集成电路材料的方法和系统
公开(公告)号：US20050075052A1
公开(公告)日：2005-04-07
申请号：US10947458
申请日：2004-09-22
申请人： Kwang-Bok Kim , Jae-Kwang Choi , Yong-Sun Ko , Chang-Ki Hong , Kyung-Hyun Kim , Jae-Dong Lee
发明人： Kwang-Bok Kim , Jae-Kwang Choi , Yong-Sun Ko , Chang-Ki Hong , Kyung-Hyun Kim , Jae-Dong Lee
IPC分类号： H01L21/304 , B24B37/04 , B24B49/16 , B24B57/02 , C09G1/02 , B24B1/00 , B24B7/19
CPC分类号： C09G1/02 , B24B37/044 , B24B49/16 , B24B57/02
摘要： For planarizing an IC (integrate circuit) material, a first slurry is dispensed for a first planarization of the IC material using the first slurry, and a second slurry is dispensed for a second planarization of the IC material using the second slurry. The first and second slurries are different. For example, the first slurry is silica based for faster planarization during the first planarization. Thereafter, the second planarization is performed with the second slurry that is ceria based with higher planarity for attaining sufficient planarization of the IC material.
摘要翻译：为了平坦化IC（集成电路）材料，使用第一浆料分配第一浆料以使IC材料的第一平面化，并且使用第二浆料分配第二浆料以进行IC材料的第二平面化。第一和第二种浆料是不同的。例如，第一浆料是二氧化硅基，用于在第一平面化期间更快的平坦化。此后，利用二氧化铈为基础，以更高的平面度进行第二平坦化，以获得IC材料的充分平坦化。

16. 发明授权

US08110499B2 Method of forming a contact structure 有权
标题翻译：形成接触结构的方法
公开(公告)号：US08110499B2
公开(公告)日：2012-02-07
申请号：US12437390
申请日：2009-05-07
申请人： Dae-Hyuk Kang , Young-Hoo Kim , Chang-Ki Hong , Kun-Tack Lee , Jae-Dong Lee , Dae-Hong Eom , Jeong-Nam Han
发明人： Dae-Hyuk Kang , Young-Hoo Kim , Chang-Ki Hong , Kun-Tack Lee , Jae-Dong Lee , Dae-Hong Eom , Jeong-Nam Han
IPC分类号： H01L21/44
CPC分类号： H01L21/76843 , H01L21/28518 , H01L21/76814 , H01L21/76846 , H01L21/76855 , H01L23/485 , H01L27/24 , H01L2924/0002 , H01L2924/09701 , H01L2924/00
摘要： An insulation layer may be formed on an object having a contact region. The insulation layer may be partially etched to form an opening exposing the contact region. A material layer including silicon and oxygen may be formed on the exposed contact region. A metal layer may be formed on the material layer including silicon and oxygen. The material layer including silicon and oxygen may be reacted with the metal layer to form a metal oxide silicide layer at least on the contact region. A conductive layer may be formed on the metal oxide silicide layer to fill up the opening.
摘要翻译：可以在具有接触区域的物体上形成绝缘层。绝缘层可以被部分蚀刻以形成暴露接触区域的开口。可以在暴露的接触区域上形成包括硅和氧的材料层。可以在包括硅和氧的材料层上形成金属层。包括硅和氧的材料层可以与金属层反应，以至少在接触区域上形成金属氧化物硅化物层。可以在金属氧化物硅化物层上形成导电层以填充开口。

17. 发明申请

US20120007018A1 SLURRY COMPOSITIONS FOR SELECTIVELY POLISHING SILICON NITRIDE RELATIVE TO SILICON OXIDE, METHODS OF POLISHING A SILICON NITRIDE LAYER AND METHODS OF MANUFACTURING A SEMICONDUCTOR DEVICE USING THE SAME 审中-公开
标题翻译：用于选择性地氧化硅氧化物的硅酸盐组合物，用于抛光氮化硅层的方法和使用其制造半导体器件的方法
公开(公告)号：US20120007018A1
公开(公告)日：2012-01-12
申请号：US13240271
申请日：2011-09-22
申请人： Jong-Won LEE , Sang-Yeob Han , Chang-Ki Hong , Jae-Dong Lee
发明人： Jong-Won LEE , Sang-Yeob Han , Chang-Ki Hong , Jae-Dong Lee
IPC分类号： C09K13/00 , B82Y30/00
CPC分类号： H01L21/31053 , C09G1/02 , H01L29/66583 , H01L29/66795 , H01L29/7851
摘要： Slurry compositions for selectively polishing silicon nitride relative to silicon oxide, methods of polishing a silicon nitride layer and methods of manufacturing a semiconductor device using the same are provided. The slurry compositions include a first agent for reducing an oxide polishing rate, an abrasive particle and water. The first agent includes poly(acrylic acid), The slurry composition may have a high polishing selectivity of silicon nitride relative to silicon oxide to be employed in selectively polishing a silicon nitride layer in a semiconductor manufacturing process.
摘要翻译：提供了相对于氧化硅选择性研磨氮化硅的浆料组合物，研磨氮化硅层的方法和使用其制造半导体器件的方法。浆料组合物包括用于降低氧化物抛光速率的第一试剂，磨料颗粒和水。第一种试剂包括聚（丙烯酸）。在半导体制造过程中，浆料组合物可以具有相对于氧化硅的氮化硅的高抛光选择性，以选择性地研磨氮化硅层。

18. 发明授权

US08084344B2 Methods of fabricating a semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08084344B2
公开(公告)日：2011-12-27
申请号：US12292195
申请日：2008-11-13
申请人： Jong-Won Lee , Sang-Yeob Han , Chang-Ki Hong , Bo-Un Yoon , Jae-Dong Lee
发明人： Jong-Won Lee , Sang-Yeob Han , Chang-Ki Hong , Bo-Un Yoon , Jae-Dong Lee
IPC分类号： H01L21/4763
CPC分类号： H01L21/76897 , H01L27/10855 , H01L27/10873 , H01L27/10888 , H01L29/6653
摘要： A method of fabricating a contact plug of a semiconductor device is provided, the method includes forming a gate pattern on a substrate, forming a capping pattern to cover an upper surface and sidewalls of the gate pattern, forming an interlayer insulation layer on the substrate such that the interlayer insulation layer exposes an upper surface of the capping pattern, and removing a portion of the capping pattern and the interlayer insulation layer such that the upper surface of the capping pattern is planarized.
摘要翻译：提供了制造半导体器件的接触插塞的方法，该方法包括在衬底上形成栅极图案，形成覆盖图案的上表面和侧壁的封盖图案，在衬底上形成层间绝缘层，如层间绝缘层暴露封盖图案的上表面，并且去除封盖图案和层间绝缘层的一部分，使得封盖图案的上表面被平坦化。

19. 发明申请

US20100127398A1 Wiring structure of a semiconductor device 审中-公开
标题翻译：半导体器件的接线结构
公开(公告)号：US20100127398A1
公开(公告)日：2010-05-27
申请号：US12592042
申请日：2009-11-18
申请人： Young-Hoo Kim , Chang-Ki Hong , Jae-Dong Lee
发明人： Young-Hoo Kim , Chang-Ki Hong , Jae-Dong Lee
IPC分类号： H01L23/498
CPC分类号： H01L21/76831 , H01L21/76885 , H01L27/10855 , H01L27/10888
摘要： In a wiring structure of a semiconductor device and a method of manufacturing the same, a wiring structure includes a contact pad, a contact plug, a spacer and an insulation interlayer pattern. The contact pad is electrically connected to a contact region of a substrate. The contact plug is provided on the contact pad and is electrically connected to the contact pad. The spacer faces an upper side surface of the contact pad and sidewalls of the contact plug. The insulation interlayer pattern has an opening, the contact plug and the spacer being provided in the opening. The spacer of the wiring structure may prevent the contact pad from being damaged by a cleaning solution while forming a contact plug to be connected to a capacitor.
摘要翻译：在半导体器件的布线结构及其制造方法中，布线结构包括接触焊盘，接触插塞，间隔物和绝缘夹层图案。接触垫电连接到基板的接触区域。接触插头设置在接触垫上并且电连接到接触垫。隔离物面向接触垫的上侧表面和接触插塞的侧壁。绝缘夹层图案具有开口，接触插塞和间隔件设置在开口中。布线结构的间隔件可以防止接触垫在形成要连接到电容器的接触插塞时被清洁溶液损坏。

20. 发明授权

US07718535B2 Slurry compositions and CMP methods using the same 有权
标题翻译：浆料组合物和使用其的CMP方法
公开(公告)号：US07718535B2
公开(公告)日：2010-05-18
申请号：US11984399
申请日：2007-11-16
申请人： Jaekwang Choi , Jae-Dong Lee , Chang-Ki Hong
发明人： Jaekwang Choi , Jae-Dong Lee , Chang-Ki Hong
IPC分类号： H01L21/306
CPC分类号： H01L21/3212 , C09G1/02 , C09K3/1463 , H01L21/7684
摘要： The exemplary embodiments of the present invention providing new slurry compositions suitable for use in processes involving the chemical mechanical polishing (CMP) of a polysilicon layer. The slurry compositions include one or more non-ionic polymeric surfactants that will selectively form a passivation layer on an exposed polysilicon surface in order to suppress the polysilicon removal rate relative to silicon oxide and silicon nitride and improve the planarity of the polished substrate. Exemplary surfactants include alkyl and aryl alcohols of ethylene oxide (EO) and propylene oxide (PO) block copolymers and may be present in the slurry compositions in an amount of up to about 5 wt %, although much smaller concentrations may be effective. Other slurry additives may include viscosity modifiers, pH modifiers, dispersion agents, chelating agents, and amine or imine surfactants suitable for modifying the relative removal rates of silicon nitride and silicon oxide.
摘要翻译：提供适用于涉及多晶硅层的化学机械抛光（CMP）的工艺的新的浆料组合物的本发明的示例性实施方案。浆料组合物包括一种或多种非离子聚合物表面活性剂，其将在暴露的多晶硅表面上选择性地形成钝化层，以便抑制相对于氧化硅和氮化硅的多晶硅去除速率并提高抛光的基材的平面度。示例性的表面活性剂包括环氧乙烷（EO）和环氧丙烷（PO）嵌段共聚物的烷基和芳基醇，并且可以以高达约5重量％的量存在于浆料组合物中，尽管更小的浓度可能是有效的。其它浆料添加剂可以包括粘度调节剂，pH调节剂，分散剂，螯合剂和适于改变氮化硅和氧化硅的相对去除速率的胺或亚胺表面活性剂。

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