专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07144301B2 Method and system for planarizing integrated circuit material 有权
标题翻译：用于平面化集成电路材料的方法和系统
公开(公告)号：US07144301B2
公开(公告)日：2006-12-05
申请号：US10947458
申请日：2004-09-22
申请人： Kwang-Bok Kim , Jae-Kwang Choi , Yong-Sun Ko , Chang-Ki Hong , Kyung-Hyun Kim , Jae-Dong Lee
发明人： Kwang-Bok Kim , Jae-Kwang Choi , Yong-Sun Ko , Chang-Ki Hong , Kyung-Hyun Kim , Jae-Dong Lee
IPC分类号： B24B7/22
CPC分类号： C09G1/02 , B24B37/044 , B24B49/16 , B24B57/02
摘要： For planarizing an IC (integrate circuit) material, a first slurry is dispensed for a first planarization of the IC material using the first slurry, and a second slurry is dispensed for a second planarization of the IC material using the second slurry. The first and second slurries are different. For example, the first slurry is silica based for faster planarization during the first planarization. Thereafter, the second planarization is performed with the second slurry that is ceria based with higher planarity for attaining sufficient planarization of the IC material.
摘要翻译：为了平坦化IC（集成电路）材料，使用第一浆料分配第一浆料以使IC材料的第一平面化，并且使用第二浆料分配第二浆料以进行IC材料的第二平面化。第一和第二种浆料是不同的。例如，第一浆料是二氧化硅基，用于在第一平面化期间更快的平坦化。此后，利用二氧化铈为基础，以更高的平面度进行第二平坦化，以获得IC材料的充分平坦化。

2. 发明申请

US20050075052A1 Method and system for planarizing integrated circuit material 有权
标题翻译：用于平面化集成电路材料的方法和系统
公开(公告)号：US20050075052A1
公开(公告)日：2005-04-07
申请号：US10947458
申请日：2004-09-22
申请人： Kwang-Bok Kim , Jae-Kwang Choi , Yong-Sun Ko , Chang-Ki Hong , Kyung-Hyun Kim , Jae-Dong Lee
发明人： Kwang-Bok Kim , Jae-Kwang Choi , Yong-Sun Ko , Chang-Ki Hong , Kyung-Hyun Kim , Jae-Dong Lee
IPC分类号： H01L21/304 , B24B37/04 , B24B49/16 , B24B57/02 , C09G1/02 , B24B1/00 , B24B7/19
CPC分类号： C09G1/02 , B24B37/044 , B24B49/16 , B24B57/02
摘要： For planarizing an IC (integrate circuit) material, a first slurry is dispensed for a first planarization of the IC material using the first slurry, and a second slurry is dispensed for a second planarization of the IC material using the second slurry. The first and second slurries are different. For example, the first slurry is silica based for faster planarization during the first planarization. Thereafter, the second planarization is performed with the second slurry that is ceria based with higher planarity for attaining sufficient planarization of the IC material.
摘要翻译：为了平坦化IC（集成电路）材料，使用第一浆料分配第一浆料以使IC材料的第一平面化，并且使用第二浆料分配第二浆料以进行IC材料的第二平面化。第一和第二种浆料是不同的。例如，第一浆料是二氧化硅基，用于在第一平面化期间更快的平坦化。此后，利用二氧化铈为基础，以更高的平面度进行第二平坦化，以获得IC材料的充分平坦化。

3. 发明申请

US20060115950A1 Methods of fabricating trench type capacitors including protective layers for electrodes and capacitors so formed 审中-公开
标题翻译：制造沟槽型电容器的方法包括如此形成的用于电极和电容器的保护层
公开(公告)号：US20060115950A1
公开(公告)日：2006-06-01
申请号：US11284678
申请日：2005-11-22
申请人： Kwang-Bok Kim , Yong-Sun Ko , Kyung-Hyun Kim
发明人： Kwang-Bok Kim , Yong-Sun Ko , Kyung-Hyun Kim
IPC分类号： H01L21/20
CPC分类号： H01L28/91 , H01L21/3212
摘要： A method of forming a capacitor can include forming a protective layer on a metal layer in a trench in an insulating layer and outside thereof. A surface of the protective layer and the metal layer beneath can be planarized using a chemical mechanical polishing (CMP) process to expose a surface of the insulating layer outside the trench. Related structures are also disclosed.
摘要翻译：形成电容器的方法可以包括在绝缘层和其外部的沟槽中的金属层上形成保护层。可以使用化学机械抛光（CMP）工艺将保护层的表面和下面的金属层平坦化，以使沟槽外部的绝缘层的表面露出。还公开了相关结构。

4. 发明授权

US06709920B2 Method of fabricating a non-volatile memory device having a tunnel-insulating layer including more than two portions of different thickness 有权
标题翻译：制造具有包括不同厚度的两个以上部分的隧道绝缘层的非易失性存储器件的方法
公开(公告)号：US06709920B2
公开(公告)日：2004-03-23
申请号：US09902243
申请日：2001-07-10
申请人： Jae-Phil Boo , Soo-Young Tak , Kwang-Bok Kim , Kyung-Hyun Kim , Chang-Ki Hong
发明人： Jae-Phil Boo , Soo-Young Tak , Kwang-Bok Kim , Kyung-Hyun Kim , Chang-Ki Hong
IPC分类号： H01L218242
CPC分类号： H01L27/11526 , H01L27/11531
摘要： A method of fabricating a non-volatile memory device, which has a tunnel insulating layer consisting of two or more portions of different thickness, cell transistors, and auxiliary transistors for applying external voltage and for interfacing with peripheral circuits is described. According to the method, the tunnel insulating layer, a conductive layer, and a first insulating layer are sequentially deposited over a semiconductor substrate. The resultant structure is selectively etched to a given depth to form trenches. A second insulating layer is deposited over the substrate including the trenches, and the second insulating layer is selectively removed so as to form element isolation regions consisting of the trenches filled with the second insulating layer. The first insulating layer is selectively removed, and the second insulating layer is selectively removed by a CMP process to expose the conductive layer. The conductive layer is used as the stopping layer during the CMP process.
摘要翻译：描述了制造具有由不同厚度的两个或更多个部分组成的隧道绝缘层的单元晶体管和用于施加外部电压并与外围电路接口的辅助晶体管的非易失性存储器件的制造方法。根据该方法，隧道绝缘层，导电层和第一绝缘层依次沉积在半导体衬底上。将所得结构选择性地蚀刻到给定的深度以形成沟槽。在包括沟槽的衬底上沉积第二绝缘层，并且选择性地去除第二绝缘层，以便形成由填充有第二绝缘层的沟槽组成的元件隔离区域。选择性地去除第一绝缘层，并且通过CMP工艺选择性地去除第二绝缘层以暴露导电层。在CMP工艺期间，导电层用作停止层。

5. 发明授权

US06649471B2 Method of planarizing non-volatile memory device 有权
公开(公告)号：US06649471B2
公开(公告)日：2003-11-18
申请号：US10206511
申请日：2002-07-25
申请人： Min-Soo Cho , Dong-Jun Kim , Eui-Youl Ryu , Dai-Goun Kim , Young-Hee Kim , Sang-Rok Hah , Kwang-Bok Kim , Jeong-Lim Nam , Kyung-Hyun Kim
发明人： Min-Soo Cho , Dong-Jun Kim , Eui-Youl Ryu , Dai-Goun Kim , Young-Hee Kim , Sang-Rok Hah , Kwang-Bok Kim , Jeong-Lim Nam , Kyung-Hyun Kim
IPC分类号： H01L21336
CPC分类号： H01L27/115 , H01L27/11521 , H01L29/66553
摘要： Disclosed is a method of planarizing a non-volatile memory device. After forming a floating gate structure on a cell area of a semiconductor substrate, a conductive layer, a hard mask layer and a first insulating layer are sequentially formed on the entire surface of the resultant structure. After removing the first insulating layer of the cell area to leave a first insulating layer pattern only on the peripheral circuit area, the hard mask layer of the cell area is removed. A second insulating layer is formed on the conductive layer and the insulating layer pattern to increase the height of the insulating layer on the peripheral circuit area. The second insulating layer and the first insulating layer pattern are removed until the floating gate structure is exposed, thereby planarizing the cell area and the peripheral circuit area. The conductive layer is patterned to form wordlines on both sidewalls of the floating gate structure and simultaneously, to form a gate of a logic device on the peripheral circuit area. When a CMP process for forming the wordline is carried out, the excessive polishing of the cell area adjacent to the peripheral circuit area can be prevented.

6. 发明申请

US20060017094A1 Non-volatile memory devices with improved insulation layers and methods of manufacturing such devices 审中-公开
标题翻译：具有改进的绝缘层的非易失性存储器件和制造这种器件的方法
公开(公告)号：US20060017094A1
公开(公告)日：2006-01-26
申请号：US11183650
申请日：2005-07-18
申请人： Kwang-Bok Kim , Kyung-Hyun Kim , Young-Sun Ko
发明人： Kwang-Bok Kim , Kyung-Hyun Kim , Young-Sun Ko
IPC分类号： H01L29/788
CPC分类号： H01L27/115 , H01L27/11519 , H01L27/11521 , H01L27/11524
摘要： Non-volatile memory devices are provided which include a plurality of gate structures on a substrate. In these devices, a first insulation interlayer is on both the substrate and on the plurality of gate structures, and includes an opening therein. A common source line is in the opening in the first insulation interlayer. A top surface of the common source line is recessed below the top surface of the first insulation interlayer. A second insulation interlayer is on the first insulation interlayer and on the common source line.
摘要翻译：提供了非易失性存储器件，其包括在衬底上的多个栅极结构。在这些器件中，第一绝缘夹层位于衬底和多个栅极结构上，并且在其中包括开口。共同的源极线在第一绝缘中间层的开口处。公共源极线的顶表面凹陷在第一绝缘中间层的顶表面下方。第二绝缘夹层位于第一绝缘中间层和公共源极线上。

7. 发明授权

US09343326B2 CMP slurry composition for polishing an organic layer and method of forming a semiconductor device using the same 有权
标题翻译：用于研磨有机层的CMP浆料组合物和使用其制备半导体器件的方法
公开(公告)号：US09343326B2
公开(公告)日：2016-05-17
申请号：US14825846
申请日：2015-08-13
申请人： Yun-Jeong Kim , Sang-Kyun Kim , Kwang-Bok Kim , Ye-Hwan Kim , Jung-Sik Choi , Choong-Ho Han , Gi-Sik Hong
发明人： Yun-Jeong Kim , Sang-Kyun Kim , Kwang-Bok Kim , Ye-Hwan Kim , Jung-Sik Choi , Choong-Ho Han , Gi-Sik Hong
IPC分类号： H01L21/302 , H01L21/3105 , C09K3/14 , H01L21/033 , H01L21/311 , H01L21/3213 , H01L27/115
CPC分类号： H01L21/31058 , C09G1/02 , C09K3/1463 , H01L21/0337 , H01L21/0338 , H01L21/31055 , H01L21/31144 , H01L21/32139 , H01L27/11582
摘要： A chemical mechanical polishing (CMP) slurry composition for polishing an organic layer and a method of forming a semiconductor device using the same are disclosed. The CMP slurry composition may include from 0.001% to 5% by weight of oxide-polishing particles; from 0.1% to 5% by weight of an oxidant; from 0% to 5% by weight of a polishing regulator; from 0% to 3% by weight of a surfactant; from 0% to 3% by weight of a pH regulator; and from 79% to 99.889% by weight of deionized water. The use of the CMP slurry composition makes it possible to allow a silicon-free organic layer to be polished with a selectivity higher than 6:1 with respect to an oxide layer.
摘要翻译：公开了一种用于抛光有机层的化学机械抛光（CMP）浆料组合物和使用其形成半导体器件的方法。 CMP浆料组合物可以包含0.001重量％至5重量％的氧化物抛光颗粒; 0.1至5重量％的氧化剂; 0〜5重量％的抛光调节剂; 0〜3重量％的表面活性剂; 0至3重量％的pH调节剂; 和79-99889重量％的去离子水。使用CMP浆料组合物可以使无硅有机层相对于氧化物层以高于6:1的选择性进行抛光。

8. 发明申请

US20150348798A1 CMP SLURRY COMPOSITION FOR POLISHING AN ORGANIC LAYER AND METHOD OF FORMING A SEMICONDUCTOR DEVICE USING THE SAME 审中-公开
标题翻译：用于抛光有机层的CMP浆料组合物及其形成使用其的半导体器件的方法
公开(公告)号：US20150348798A1
公开(公告)日：2015-12-03
申请号：US14825846
申请日：2015-08-13
申请人： Yun-Jeong KIM , Sang-Kyun Kim , Kwang-Bok Kim , Ye-Hwan Kim , Jung-Sik Choi , Choong-Ho Han , Gi-Sik Hong
发明人： Yun-Jeong KIM , Sang-Kyun Kim , Kwang-Bok Kim , Ye-Hwan Kim , Jung-Sik Choi , Choong-Ho Han , Gi-Sik Hong
IPC分类号： H01L21/3105 , H01L27/115 , H01L21/311
CPC分类号： H01L21/31058 , C09G1/02 , C09K3/1463 , H01L21/0337 , H01L21/0338 , H01L21/31055 , H01L21/31144 , H01L21/32139 , H01L27/11582
摘要： A chemical mechanical polishing (CMP) slurry composition for polishing an organic layer and a method of forming a semiconductor device using the same are disclosed. The CMP slurry composition may include from 0.001% to 5% by weight of oxide-polishing particles; from 0.1% to 5% by weight of an oxidant; from 0% to 5% by weight of a polishing regulator; from 0% to 3% by weight of a surfactant; from 0% to 3% by weight of a pH regulator; and from 79% to 99.889% by weight of deionized water. The use of the CMP slurry composition makes it possible to allow a silicon-free organic layer to be polished with a selectivity higher than 6:1 with respect to an oxide layer.
摘要翻译：公开了一种用于抛光有机层的化学机械抛光（CMP）浆料组合物和使用其形成半导体器件的方法。 CMP浆料组合物可以包含0.001重量％至5重量％的氧化物抛光颗粒; 0.1至5重量％的氧化剂; 0〜5重量％的抛光调节剂; 0〜3重量％的表面活性剂; 0至3重量％的pH调节剂; 和79-99889重量％的去离子水。使用CMP浆料组合物可以使无硅有机层相对于氧化物层以高于6:1的选择性进行抛光。

9. 发明申请

US20130201638A1 Flexible Display Device 审中-公开
标题翻译：灵活显示设备
公开(公告)号：US20130201638A1
公开(公告)日：2013-08-08
申请号：US13594251
申请日：2012-08-24
申请人： Kwang-Bok Kim
发明人： Kwang-Bok Kim
IPC分类号： H05K7/00
CPC分类号： G06F1/1652 , G02F1/133305
摘要： A flexible display device includes a display main body having flexibility; a first supporter which evenly supports a first side of the display main body; and a second supporter which evenly supports a second side of the display main body joined to the first side. During carrying, the display main body of the flexible display device is flexibly deformed and kept, and during use, the flexible display device is evenly unfolded and viewed. Accordingly, the flexible display device provides improved convenience in carrying and use.
摘要翻译：柔性显示装置包括具有柔性的显示主体; 第一支撑件，其均匀地支撑显示器主体的第一侧; 以及第二支撑件，其均匀地支撑结合到第一侧的显示器主体的第二侧。在携带期间，柔性显示装置的显示器主体被灵活地变形和保持，并且在使用期间，柔性显示装置被均匀展开和观看。因此，柔性显示装置提供了便于携带和使用的改进。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式