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1. 发明申请

US20050075052A1 Method and system for planarizing integrated circuit material 有权
标题翻译：用于平面化集成电路材料的方法和系统
公开(公告)号：US20050075052A1
公开(公告)日：2005-04-07
申请号：US10947458
申请日：2004-09-22
申请人： Kwang-Bok Kim , Jae-Kwang Choi , Yong-Sun Ko , Chang-Ki Hong , Kyung-Hyun Kim , Jae-Dong Lee
发明人： Kwang-Bok Kim , Jae-Kwang Choi , Yong-Sun Ko , Chang-Ki Hong , Kyung-Hyun Kim , Jae-Dong Lee
IPC分类号： H01L21/304 , B24B37/04 , B24B49/16 , B24B57/02 , C09G1/02 , B24B1/00 , B24B7/19
CPC分类号： C09G1/02 , B24B37/044 , B24B49/16 , B24B57/02
摘要： For planarizing an IC (integrate circuit) material, a first slurry is dispensed for a first planarization of the IC material using the first slurry, and a second slurry is dispensed for a second planarization of the IC material using the second slurry. The first and second slurries are different. For example, the first slurry is silica based for faster planarization during the first planarization. Thereafter, the second planarization is performed with the second slurry that is ceria based with higher planarity for attaining sufficient planarization of the IC material.
摘要翻译：为了平坦化IC（集成电路）材料，使用第一浆料分配第一浆料以使IC材料的第一平面化，并且使用第二浆料分配第二浆料以进行IC材料的第二平面化。第一和第二种浆料是不同的。例如，第一浆料是二氧化硅基，用于在第一平面化期间更快的平坦化。此后，利用二氧化铈为基础，以更高的平面度进行第二平坦化，以获得IC材料的充分平坦化。

2. 发明授权

US07144301B2 Method and system for planarizing integrated circuit material 有权
标题翻译：用于平面化集成电路材料的方法和系统
公开(公告)号：US07144301B2
公开(公告)日：2006-12-05
申请号：US10947458
申请日：2004-09-22
申请人： Kwang-Bok Kim , Jae-Kwang Choi , Yong-Sun Ko , Chang-Ki Hong , Kyung-Hyun Kim , Jae-Dong Lee
发明人： Kwang-Bok Kim , Jae-Kwang Choi , Yong-Sun Ko , Chang-Ki Hong , Kyung-Hyun Kim , Jae-Dong Lee
IPC分类号： B24B7/22
CPC分类号： C09G1/02 , B24B37/044 , B24B49/16 , B24B57/02
摘要： For planarizing an IC (integrate circuit) material, a first slurry is dispensed for a first planarization of the IC material using the first slurry, and a second slurry is dispensed for a second planarization of the IC material using the second slurry. The first and second slurries are different. For example, the first slurry is silica based for faster planarization during the first planarization. Thereafter, the second planarization is performed with the second slurry that is ceria based with higher planarity for attaining sufficient planarization of the IC material.
摘要翻译：为了平坦化IC（集成电路）材料，使用第一浆料分配第一浆料以使IC材料的第一平面化，并且使用第二浆料分配第二浆料以进行IC材料的第二平面化。第一和第二种浆料是不同的。例如，第一浆料是二氧化硅基，用于在第一平面化期间更快的平坦化。此后，利用二氧化铈为基础，以更高的平面度进行第二平坦化，以获得IC材料的充分平坦化。

3. 发明申请

US20060115950A1 Methods of fabricating trench type capacitors including protective layers for electrodes and capacitors so formed 审中-公开
标题翻译：制造沟槽型电容器的方法包括如此形成的用于电极和电容器的保护层
公开(公告)号：US20060115950A1
公开(公告)日：2006-06-01
申请号：US11284678
申请日：2005-11-22
申请人： Kwang-Bok Kim , Yong-Sun Ko , Kyung-Hyun Kim
发明人： Kwang-Bok Kim , Yong-Sun Ko , Kyung-Hyun Kim
IPC分类号： H01L21/20
CPC分类号： H01L28/91 , H01L21/3212
摘要： A method of forming a capacitor can include forming a protective layer on a metal layer in a trench in an insulating layer and outside thereof. A surface of the protective layer and the metal layer beneath can be planarized using a chemical mechanical polishing (CMP) process to expose a surface of the insulating layer outside the trench. Related structures are also disclosed.
摘要翻译：形成电容器的方法可以包括在绝缘层和其外部的沟槽中的金属层上形成保护层。可以使用化学机械抛光（CMP）工艺将保护层的表面和下面的金属层平坦化，以使沟槽外部的绝缘层的表面露出。还公开了相关结构。

4. 发明授权

US06709920B2 Method of fabricating a non-volatile memory device having a tunnel-insulating layer including more than two portions of different thickness 有权
标题翻译：制造具有包括不同厚度的两个以上部分的隧道绝缘层的非易失性存储器件的方法
公开(公告)号：US06709920B2
公开(公告)日：2004-03-23
申请号：US09902243
申请日：2001-07-10
申请人： Jae-Phil Boo , Soo-Young Tak , Kwang-Bok Kim , Kyung-Hyun Kim , Chang-Ki Hong
发明人： Jae-Phil Boo , Soo-Young Tak , Kwang-Bok Kim , Kyung-Hyun Kim , Chang-Ki Hong
IPC分类号： H01L218242
CPC分类号： H01L27/11526 , H01L27/11531
摘要： A method of fabricating a non-volatile memory device, which has a tunnel insulating layer consisting of two or more portions of different thickness, cell transistors, and auxiliary transistors for applying external voltage and for interfacing with peripheral circuits is described. According to the method, the tunnel insulating layer, a conductive layer, and a first insulating layer are sequentially deposited over a semiconductor substrate. The resultant structure is selectively etched to a given depth to form trenches. A second insulating layer is deposited over the substrate including the trenches, and the second insulating layer is selectively removed so as to form element isolation regions consisting of the trenches filled with the second insulating layer. The first insulating layer is selectively removed, and the second insulating layer is selectively removed by a CMP process to expose the conductive layer. The conductive layer is used as the stopping layer during the CMP process.
摘要翻译：描述了制造具有由不同厚度的两个或更多个部分组成的隧道绝缘层的单元晶体管和用于施加外部电压并与外围电路接口的辅助晶体管的非易失性存储器件的制造方法。根据该方法，隧道绝缘层，导电层和第一绝缘层依次沉积在半导体衬底上。将所得结构选择性地蚀刻到给定的深度以形成沟槽。在包括沟槽的衬底上沉积第二绝缘层，并且选择性地去除第二绝缘层，以便形成由填充有第二绝缘层的沟槽组成的元件隔离区域。选择性地去除第一绝缘层，并且通过CMP工艺选择性地去除第二绝缘层以暴露导电层。在CMP工艺期间，导电层用作停止层。

5. 发明申请

US20060017094A1 Non-volatile memory devices with improved insulation layers and methods of manufacturing such devices 审中-公开
标题翻译：具有改进的绝缘层的非易失性存储器件和制造这种器件的方法
公开(公告)号：US20060017094A1
公开(公告)日：2006-01-26
申请号：US11183650
申请日：2005-07-18
申请人： Kwang-Bok Kim , Kyung-Hyun Kim , Young-Sun Ko
发明人： Kwang-Bok Kim , Kyung-Hyun Kim , Young-Sun Ko
IPC分类号： H01L29/788
CPC分类号： H01L27/115 , H01L27/11519 , H01L27/11521 , H01L27/11524
摘要： Non-volatile memory devices are provided which include a plurality of gate structures on a substrate. In these devices, a first insulation interlayer is on both the substrate and on the plurality of gate structures, and includes an opening therein. A common source line is in the opening in the first insulation interlayer. A top surface of the common source line is recessed below the top surface of the first insulation interlayer. A second insulation interlayer is on the first insulation interlayer and on the common source line.
摘要翻译：提供了非易失性存储器件，其包括在衬底上的多个栅极结构。在这些器件中，第一绝缘夹层位于衬底和多个栅极结构上，并且在其中包括开口。共同的源极线在第一绝缘中间层的开口处。公共源极线的顶表面凹陷在第一绝缘中间层的顶表面下方。第二绝缘夹层位于第一绝缘中间层和公共源极线上。

6. 发明授权

US06649471B2 Method of planarizing non-volatile memory device 有权
公开(公告)号：US06649471B2
公开(公告)日：2003-11-18
申请号：US10206511
申请日：2002-07-25
申请人： Min-Soo Cho , Dong-Jun Kim , Eui-Youl Ryu , Dai-Goun Kim , Young-Hee Kim , Sang-Rok Hah , Kwang-Bok Kim , Jeong-Lim Nam , Kyung-Hyun Kim
发明人： Min-Soo Cho , Dong-Jun Kim , Eui-Youl Ryu , Dai-Goun Kim , Young-Hee Kim , Sang-Rok Hah , Kwang-Bok Kim , Jeong-Lim Nam , Kyung-Hyun Kim
IPC分类号： H01L21336
CPC分类号： H01L27/115 , H01L27/11521 , H01L29/66553
摘要： Disclosed is a method of planarizing a non-volatile memory device. After forming a floating gate structure on a cell area of a semiconductor substrate, a conductive layer, a hard mask layer and a first insulating layer are sequentially formed on the entire surface of the resultant structure. After removing the first insulating layer of the cell area to leave a first insulating layer pattern only on the peripheral circuit area, the hard mask layer of the cell area is removed. A second insulating layer is formed on the conductive layer and the insulating layer pattern to increase the height of the insulating layer on the peripheral circuit area. The second insulating layer and the first insulating layer pattern are removed until the floating gate structure is exposed, thereby planarizing the cell area and the peripheral circuit area. The conductive layer is patterned to form wordlines on both sidewalls of the floating gate structure and simultaneously, to form a gate of a logic device on the peripheral circuit area. When a CMP process for forming the wordline is carried out, the excessive polishing of the cell area adjacent to the peripheral circuit area can be prevented.

7. 发明授权

US08053751B2 Phase-change semiconductor device and methods of manufacturing the same 有权
标题翻译：相变半导体器件及其制造方法
公开(公告)号：US08053751B2
公开(公告)日：2011-11-08
申请号：US12591531
申请日：2009-11-23
申请人： Tae-Won Kim , Yong-Sun Ko , Ki-Jong Park , Kyung-Hyun Kim
发明人： Tae-Won Kim , Yong-Sun Ko , Ki-Jong Park , Kyung-Hyun Kim
IPC分类号： H01L21/4763
CPC分类号： H01L45/06 , H01L27/2436 , H01L45/1233 , H01L45/126 , H01L45/1273 , H01L45/143 , H01L45/144 , H01L45/148 , H01L45/1675
摘要： In a phase-change semiconductor device and methods of manufacturing the same, an example method may include forming a metal layer pattern on a substrate, the metal layer pattern including an opening that exposes a portion of the substrate, forming an etch stop layer on the metal layer pattern, a sidewall of the opening and the exposed portion of the substrate, the etch stop layer formed with a thickness less than an upper thickness threshold, and reducing at least a portion of the etch stop layer, the reduced portion of the etch stop layer forming an electrical connection with the substrate.
摘要翻译：在相变半导体器件及其制造方法中，示例性方法可以包括在衬底上形成金属层图案，金属层图案包括露出衬底的一部分的开口，在其上形成蚀刻停止层金属层图案，开口的侧壁和衬底的暴露部分，蚀刻停止层形成为具有小于上部厚度阈值的厚度，以及减少至少一部分蚀刻停止层，蚀刻部分的蚀刻停止层与基底形成电连接。

8. 发明授权

US08048809B2 Polishing method using chemical mechanical slurry composition 有权
标题翻译：抛光方法采用化学机械浆料组成
公开(公告)号：US08048809B2
公开(公告)日：2011-11-01
申请号：US11898850
申请日：2007-09-17
申请人： Hyo-Jin Lee , Kyung-Hyun Kim , Yong-Sun Ko
发明人： Hyo-Jin Lee , Kyung-Hyun Kim , Yong-Sun Ko
IPC分类号： H01L21/302
CPC分类号： H01L21/7684 , C09G1/02 , C09K3/1463 , H01L21/28123 , H01L21/3212
摘要： A slurry composition includes about 4.25 to about 18.5 weight percent of an abrasive, about 80 to about 95 weight percent of deionized water, and about 0.05 to about 1.5 weight percent of an additive. The slurry composition may further include a surfactant. In a polishing method using the slurry composition, a polysilicon layer may be rapidly polished, and also dishing and erosion of the polysilicon layer may be suppressed.
摘要翻译：浆料组合物包括约4.25至约18.5重量％的研磨剂，约80至约95重量％的去离子水和约0.05至约1.5重量％的添加剂。浆料组合物还可以包括表面活性剂。在使用浆料组合物的抛光方法中，可以快速抛光多晶硅层，并且可以抑制多晶硅层的凹陷和侵蚀。

9. 发明授权

US07781346B2 Methods of forming patterns and capacitors for semiconductor devices using the same 失效
标题翻译：使用其形成用于半导体器件的图案和电容器的方法
公开(公告)号：US07781346B2
公开(公告)日：2010-08-24
申请号：US11455815
申请日：2006-06-20
申请人： Cheol-Woo Park , Byoung-Moon Yoon , Yong-Sun Ko , Kyung-Hyun Kim , Kwang-Wook Lee
发明人： Cheol-Woo Park , Byoung-Moon Yoon , Yong-Sun Ko , Kyung-Hyun Kim , Kwang-Wook Lee
IPC分类号： H01L21/302
CPC分类号： H01L21/31111 , H01L21/0206 , H01L21/02068 , H01L27/10852 , H01L28/91
摘要： A semiconductor structure may be formed by a wet etching process using an etchant containing water. The semiconductor structure may include a plurality of patterns having an increased or higher aspect ratio and may be arranged closer to one another. A dry cleaning process may be performed using hydrogen fluoride gas on the semiconductor structure.
摘要翻译：可以通过使用含有蚀刻剂的湿法蚀刻工艺形成半导体结构。半导体结构可以包括具有增加的或更高的纵横比的多个图案，并且可以彼此更靠近地布置。可以在半导体结构上使用氟化氢气体进行干法处理。

10. 发明申请

US20100072446A1 Phase-change semiconductor device and methods of manufacturing the same 有权
标题翻译：相变半导体器件及其制造方法
公开(公告)号：US20100072446A1
公开(公告)日：2010-03-25
申请号：US12591531
申请日：2009-11-23
申请人： Tae-Won Kim , Yong-Sun Ko , Ki-Jong Park , Kyung-Hyun Kim
发明人： Tae-Won Kim , Yong-Sun Ko , Ki-Jong Park , Kyung-Hyun Kim
IPC分类号： H01L45/00 , H01L21/768
CPC分类号： H01L45/06 , H01L27/2436 , H01L45/1233 , H01L45/126 , H01L45/1273 , H01L45/143 , H01L45/144 , H01L45/148 , H01L45/1675
摘要： In a phase-change semiconductor device and methods of manufacturing the same, an example method may include forming a metal layer pattern on a substrate, the metal layer pattern including an opening that exposes a portion of the substrate, forming an etch stop layer on the metal layer pattern, a sidewall of the opening and the exposed portion of the substrate, the etch stop layer formed with a thickness less than an upper thickness threshold, and reducing at least a portion of the etch stop layer, the reduced portion of the etch stop layer forming an electrical connection with the substrate.
摘要翻译：在相变半导体器件及其制造方法中，示例性方法可以包括在衬底上形成金属层图案，金属层图案包括露出衬底的一部分的开口，在其上形成蚀刻停止层金属层图案，开口的侧壁和衬底的暴露部分，蚀刻停止层形成为具有小于上部厚度阈值的厚度，以及减少至少一部分蚀刻停止层，蚀刻部分的蚀刻停止层与基底形成电连接。

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