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1. 发明申请

US20090280641A1 METHOD OF FORMING A CONTACT STRUCTURE 有权
标题翻译：形成接触结构的方法
公开(公告)号：US20090280641A1
公开(公告)日：2009-11-12
申请号：US12437390
申请日：2009-05-07
申请人： Dae-Hyuk Kang , Young-Hoo Kim , Chang-Ki Hong , Kun-Tack Lee , Jae-Dong Lee , Dae-Hong Eom , Jeong-Nam Han
发明人： Dae-Hyuk Kang , Young-Hoo Kim , Chang-Ki Hong , Kun-Tack Lee , Jae-Dong Lee , Dae-Hong Eom , Jeong-Nam Han
IPC分类号： H01L21/3205
CPC分类号： H01L21/76843 , H01L21/28518 , H01L21/76814 , H01L21/76846 , H01L21/76855 , H01L23/485 , H01L27/24 , H01L2924/0002 , H01L2924/09701 , H01L2924/00
摘要： An insulation layer may be formed on an object having a contact region. The insulation layer may be partially etched to form an opening exposing the contact region. A material layer including silicon and oxygen may be formed on the exposed contact region. A metal layer may be formed on the material layer including silicon and oxygen. The material layer including silicon and oxygen may be reacted with the metal layer to form a metal oxide silicide layer at least on the contact region. A conductive layer may be formed on the metal oxide silicide layer to fill up the opening.
摘要翻译：可以在具有接触区域的物体上形成绝缘层。绝缘层可以被部分蚀刻以形成暴露接触区域的开口。可以在暴露的接触区域上形成包括硅和氧的材料层。可以在包括硅和氧的材料层上形成金属层。包括硅和氧的材料层可以与金属层反应，以至少在接触区域上形成金属氧化物硅化物层。可以在金属氧化物硅化物层上形成导电层以填充开口。

2. 发明授权

US08110499B2 Method of forming a contact structure 有权
标题翻译：形成接触结构的方法
公开(公告)号：US08110499B2
公开(公告)日：2012-02-07
申请号：US12437390
申请日：2009-05-07
申请人： Dae-Hyuk Kang , Young-Hoo Kim , Chang-Ki Hong , Kun-Tack Lee , Jae-Dong Lee , Dae-Hong Eom , Jeong-Nam Han
发明人： Dae-Hyuk Kang , Young-Hoo Kim , Chang-Ki Hong , Kun-Tack Lee , Jae-Dong Lee , Dae-Hong Eom , Jeong-Nam Han
IPC分类号： H01L21/44
CPC分类号： H01L21/76843 , H01L21/28518 , H01L21/76814 , H01L21/76846 , H01L21/76855 , H01L23/485 , H01L27/24 , H01L2924/0002 , H01L2924/09701 , H01L2924/00
摘要： An insulation layer may be formed on an object having a contact region. The insulation layer may be partially etched to form an opening exposing the contact region. A material layer including silicon and oxygen may be formed on the exposed contact region. A metal layer may be formed on the material layer including silicon and oxygen. The material layer including silicon and oxygen may be reacted with the metal layer to form a metal oxide silicide layer at least on the contact region. A conductive layer may be formed on the metal oxide silicide layer to fill up the opening.
摘要翻译：可以在具有接触区域的物体上形成绝缘层。绝缘层可以被部分蚀刻以形成暴露接触区域的开口。可以在暴露的接触区域上形成包括硅和氧的材料层。可以在包括硅和氧的材料层上形成金属层。包括硅和氧的材料层可以与金属层反应，以至少在接触区域上形成金属氧化物硅化物层。可以在金属氧化物硅化物层上形成导电层以填充开口。

3. 发明申请

US20110287625A1 METHODS OF FORMING A PATTERN, METHODS OF FORMING A GATE STRUCTURE AND METHODS OF MANUFACTURING A SEMICONDUCTOR DEVICE USING THE SAME 审中-公开
标题翻译：形成图案的方法，形成门结构的方法和使用该方法制造半导体器件的方法
公开(公告)号：US20110287625A1
公开(公告)日：2011-11-24
申请号：US13079202
申请日：2011-04-04
申请人： Dae-Hyuk Kang , Kun-Tack Lee , Dae-Hong Eom , Bo-Un Yoon , Jeong-Nam Han
发明人： Dae-Hyuk Kang , Kun-Tack Lee , Dae-Hong Eom , Bo-Un Yoon , Jeong-Nam Han
IPC分类号： H01L21/336
CPC分类号： H01L21/28123 , H01L21/3081 , H01L21/31111 , H01L21/31116 , H01L21/31144 , H01L21/32139 , H01L27/11524 , H01L29/40114
摘要： A method of forming a pattern in a semiconductor device includes forming an etching object layer on a substrate, the etching object layer is an oxide that is substantially free of impurities. A mask is formed on the etching object layer, the mask is an oxide that includes impurities. The etching object layer is patterned using the mask as an etching mask and then the mask is removed. The mask is removed using an etchant having an etching selectivity to an oxide that is substantially free of impurities and an oxide that includes impurities during removing of the mask to limit damage to the patterned etching object layer during removal of the mask.
摘要翻译：在半导体器件中形成图案的方法包括在基板上形成蚀刻对象层，蚀刻对象层是基本上不含杂质的氧化物。在蚀刻对象层上形成掩模，掩模是包含杂质的氧化物。使用掩模将蚀刻对象层图案化为蚀刻掩模，然后去除掩模。使用具有对基本上不含杂质的氧化物的蚀刻选择性的蚀刻剂去除掩模，以及在除去掩模期间包括杂质的氧化物，以限制在去除掩模期间对图案化的蚀刻对象层的损伤。

4. 发明申请

US20070264793A1 Methods of Manufacturing Semiconductor Memory Devices with Unit Cells Having Charge Trapping Layers 失效
标题翻译：制造具有电荷陷阱层的单元电池的半导体存储器件的方法
公开(公告)号：US20070264793A1
公开(公告)日：2007-11-15
申请号：US11746761
申请日：2007-05-10
申请人： Jung-Min Oh , Jeong-Nam Han , Chang-Ki Hong , Kun-Tack Lee , Dae-Hyuk Kang , Woo-Gwam Shim , Jong-Won Lee
发明人： Jung-Min Oh , Jeong-Nam Han , Chang-Ki Hong , Kun-Tack Lee , Dae-Hyuk Kang , Woo-Gwam Shim , Jong-Won Lee
IPC分类号： H01L21/76
CPC分类号： H01L27/115 , H01L21/76229 , H01L27/11568
摘要： In a method of manufacturing a semiconductor device such as a SONOS type semiconductor device, a trench is formed on a substrate. An isolation layer protruding from the substrate is formed to fill the trench. After a first layer is formed on the substrate, a preliminary second layer pattern is formed on the first layer. The preliminary second layer pattern has an upper face substantially lower than or substantially equal to an upper face of the isolation layer. A third layer is formed on the preliminary second layer and the isolation layer. A fourth layer is formed on the third layer. The fourth layer, the third layer, the preliminary second layer pattern and the first layer are partially etched to form a gate structure on the substrate. Source/drain regions are formed at portions of the substrate adjacent to the gate structure.
摘要翻译：在制造诸如SONOS型半导体器件的半导体器件的方法中，在衬底上形成沟槽。形成从衬底突出的隔离层以填充沟槽。在基板上形成第一层之后，在第一层上形成预备的第二层图案。预备的第二层图案具有基本上低于或基本上等于隔离层的上表面的上表面。在初步第二层和隔离层上形成第三层。在第三层上形成第四层。部分蚀刻第四层，第三层，初步第二层图案和第一层，以在基板上形成栅极结构。源极/漏极区域形成在与栅极结构相邻的衬底的部分处。

5. 发明授权

US07704828B2 Method of fabricating a semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US07704828B2
公开(公告)日：2010-04-27
申请号：US11741639
申请日：2007-04-27
申请人： Jung-Min Oh , Jeong-Nam Han , Chang-Ki Hong , Kun-Tack Lee , Dae-Hyuk Kang , Sung-Il Cho
发明人： Jung-Min Oh , Jeong-Nam Han , Chang-Ki Hong , Kun-Tack Lee , Dae-Hyuk Kang , Sung-Il Cho
IPC分类号： H01L21/8242
CPC分类号： H01L28/91
摘要： A method of fabricating a semiconductor device is provided. The method includes forming a mold for forming a storage electrode, forming sacrificial spacers at side walls of openings in the mold, forming a conductive film for a storage electrode along the inside of the openings, removing the mold by a wet etching process, removing the sacrificial spacers by a dry etching process, and sequentially forming a dielectric film and an upper electrode on the storage electrode.
摘要翻译：提供一种制造半导体器件的方法。该方法包括形成用于形成存储电极的模具，在模具的开口的侧壁处形成牺牲隔离物，沿着开口的内部形成用于存储电极的导电膜，通过湿法蚀刻工艺移除模具，牺牲隔离物，并且在存储电极上依次形成电介质膜和上电极。

6. 发明授权

US07498217B2 Methods of manufacturing semiconductor memory devices with unit cells having charge trapping layers 失效
标题翻译：制造具有电荷捕获层的单元电池的半导体存储器件的方法
公开(公告)号：US07498217B2
公开(公告)日：2009-03-03
申请号：US11746761
申请日：2007-05-10
申请人： Jung-Min Oh , Jeong-Nam Han , Chang-Ki Hong , Kun-Tack Lee , Dae-Hyuk Kang , Woo-Gwan Shim , Jong-Won Lee
发明人： Jung-Min Oh , Jeong-Nam Han , Chang-Ki Hong , Kun-Tack Lee , Dae-Hyuk Kang , Woo-Gwan Shim , Jong-Won Lee
IPC分类号： H01L21/8238 , H01L21/8242 , H01L21/336
CPC分类号： H01L27/115 , H01L21/76229 , H01L27/11568
摘要： In a method of manufacturing a semiconductor device such as a SONOS type semiconductor device, a trench is formed on a substrate. An isolation layer protruding from the substrate is formed to fill the trench. After a first layer is formed on the substrate, a preliminary second layer pattern is formed on the first layer. The preliminary second layer pattern has an upper face substantially lower than or substantially equal to an upper face of the isolation layer. A third layer is formed on the preliminary second layer and the isolation layer. A fourth layer is formed on the third layer. The fourth layer, the third layer, the preliminary second layer pattern and the first layer are partially etched to form a gate structure on the substrate. Source/drain regions are formed at portions of the substrate adjacent to the gate structure.
摘要翻译：在制造诸如SONOS型半导体器件的半导体器件的方法中，在衬底上形成沟槽。形成从衬底突出的隔离层以填充沟槽。在基板上形成第一层之后，在第一层上形成预备的第二层图案。预备的第二层图案具有基本上低于或基本上等于隔离层的上表面的上表面。在初步第二层和隔离层上形成第三层。在第三层上形成第四层。部分蚀刻第四层，第三层，初步第二层图案和第一层，以在基板上形成栅极结构。源极/漏极区域形成在与栅极结构相邻的衬底的部分处。

7. 发明申请

US20120064680A1 METHODS OF FORMING A CAPACITOR STRUCTURE AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES USING THE SAME 审中-公开
标题翻译：形成电容器结构的方法和使用其制造半导体器件的方法
公开(公告)号：US20120064680A1
公开(公告)日：2012-03-15
申请号：US13228867
申请日：2011-09-09
申请人： Jung-Min Oh , Bo-Un Yoon , Gyu-Wan Choi , Kun-Tack Lee , Dae-Hyuk Kang , Im-Soo Park , Dong-Seok Lee , Young-Hoo Kim
发明人： Jung-Min Oh , Bo-Un Yoon , Gyu-Wan Choi , Kun-Tack Lee , Dae-Hyuk Kang , Im-Soo Park , Dong-Seok Lee , Young-Hoo Kim
IPC分类号： H01L21/336 , H01G13/06
CPC分类号： H01G13/06
摘要： A method of forming a capacitor structure and manufacturing a semiconductor device, the method of forming a capacitor structure including sequentially forming a first mold layer, a supporting layer, a second mold layer, an anti-bowing layer, and a third mold layer on a substrate having a conductive region thereon; partially removing the third mold layer, the anti-bowing layer, the second mold layer, the supporting layer, and the first mold layer to form a first opening exposing the conductive region; forming a lower electrode on a sidewall and bottom of the first opening, the lower electrode being electrically connected to the conductive region; further removing the third mold layer, the anti-bowing layer, and the second mold layer; partially removing the supporting layer to form a supporting layer pattern; removing the first mold layer; and sequentially forming a dielectric layer and upper electrode on the lower electrode and the supporting layer pattern.
摘要翻译：一种形成电容器结构并制造半导体器件的方法，形成电容器结构的方法包括：依次形成第一模具层，支撑层，第二模具层，抗弯曲层和第三模具层衬底，其上具有导电区域; 部分地去除第三模具层，抗弯曲层，第二模具层，支撑层和第一模具层，以形成暴露导电区域的第一开口; 在所述第一开口的侧壁和底部形成下电极，所述下电极电连接到所述导电区域; 进一步去除第三模具层，抗弯曲层和第二模具层; 部分地去除支撑层以形成支撑层图案; 去除第一模具层; 并且在下电极和支撑层图案上依次形成电介质层和上电极。

8. 发明申请

US20110159660A1 Methods of Forming Integrated Circuit Capacitors Having Sidewall Supports and Capacitors Formed Thereby 有权
标题翻译：形成具有侧壁支撑和形成电容器的集成电路电容器的方法
公开(公告)号：US20110159660A1
公开(公告)日：2011-06-30
申请号：US12906184
申请日：2010-10-18
申请人： Dae-Hyuk Kang , Bo-Un Yoon , Kun-Tack Lee , Woo-Gwan Shim , Ji-Hoon Cha , Im-Soo Park , Hyo-San Lee , Young-Hoo Kim , Jung-Min Oh
发明人： Dae-Hyuk Kang , Bo-Un Yoon , Kun-Tack Lee , Woo-Gwan Shim , Ji-Hoon Cha , Im-Soo Park , Hyo-San Lee , Young-Hoo Kim , Jung-Min Oh
IPC分类号： H01L21/02 , H01G13/00
CPC分类号： H01L28/91 , H01L27/10817 , H01L27/10852 , H01L28/87
摘要： In a method of forming a capacitor, a first mold layer pattern including a first insulating material may be formed on a substrate. The first mold layer pattern may have a trench. A supporting layer including a second insulating material may be formed in the trench. The second insulating material may have an etching selectivity with respect to the first insulating material. A second mold layer may be formed on the first mold layer pattern and the supporting layer pattern. A lower electrode may be formed through the second mold layer and the first mold layer pattern. The lower electrode may make contact with a sidewall of the supporting layer pattern. The first mold layer pattern and the second mold layer may be removed. A dielectric layer and an upper electrode may be formed on the lower electrode and the supporting layer pattern.
摘要翻译：在形成电容器的方法中，可以在基板上形成包括第一绝缘材料的第一模层图案。第一模层图案可以具有沟槽。可以在沟槽中形成包括第二绝缘材料的支撑层。第二绝缘材料可以具有相对于第一绝缘材料的蚀刻选择性。可以在第一模层图案和支撑层图案上形成第二模层。可以通过第二模具层和第一模具层图案形成下部电极。下电极可以与支撑层图案的侧壁接触。可以去除第一模层图案和第二模层。电介质层和上电极可以形成在下电极和支撑层图案上。

9. 发明申请

US20110306197A1 Methods of Manufacturing Semiconductor Devices 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：US20110306197A1
公开(公告)日：2011-12-15
申请号：US13156729
申请日：2011-06-09
申请人： Young-Hoo Kim , Bo-Un Yoon , Kun-Tack Lee , Dae-Hyuk Kang , Im-Soo Park
发明人： Young-Hoo Kim , Bo-Un Yoon , Kun-Tack Lee , Dae-Hyuk Kang , Im-Soo Park
IPC分类号： H01L21/3205
CPC分类号： H01L28/82
摘要： Method of manufacturing semiconductor device are provided including forming an insulation layer having a pad on a substrate; forming an etch stop layer on the insulation layer and the pad; forming a mold structure having at least one mold layer on the etch stop layer; forming a first supporting layer on the mold structure; etching the first supporting layer and the mold structure to form a first opening exposing the etch stop layer; forming a spacer on a sidewall of the first opening; etching the etch stop layer using the spacer as an etching mask to form a second opening, different from the first opening, exposing a first portion of the pad having a first associated area; etching the etch stop layer using the spacer as an etching mask to form a third opening exposing a second portion of the pad having a second associated area, the second associated area being larger than the first associated area; and etching the mold structure to form a fourth opening having a width larger than a width of the third opening.
摘要翻译：提供制造半导体器件的方法，包括在衬底上形成具有衬垫的绝缘层; 在所述绝缘层和所述焊盘上形成蚀刻停止层; 形成在所述蚀刻停止层上具有至少一个模制层的模具结构; 在模具结构上形成第一支撑层; 蚀刻第一支撑层和模具结构以形成暴露蚀刻停止层的第一开口; 在所述第一开口的侧壁上形成间隔件; 使用所述间隔物作为蚀刻掩模来蚀刻所述蚀刻停止层，以形成不同于所述第一开口的第二开口，暴露所述焊盘的具有第一相关区域的第一部分; 使用所述间隔物作为蚀刻掩模来蚀刻所述蚀刻停止层，以形成暴露所述焊盘的具有第二相关区域的第二部分的第三开口，所述第二相关区域大于所述第一相关区域; 并且蚀刻所述模具结构以形成宽度大于所述第三开口的宽度的第四开口。

10. 发明授权

US08766343B2 Integrated circuit capacitors having sidewall supports 有权
标题翻译：具有侧壁支撑件的集成电路电容器
公开(公告)号：US08766343B2
公开(公告)日：2014-07-01
申请号：US13356032
申请日：2012-01-23
申请人： Dae-Hyuk Kang , Bo-Un Yoon , Kun-Tack Lee , Woo-Gwan Shim , Ji-Hoon Cha , Im-Soo Park , Hyo-San Lee , Young-Hoo Kim , Jung-Min Oh
发明人： Dae-Hyuk Kang , Bo-Un Yoon , Kun-Tack Lee , Woo-Gwan Shim , Ji-Hoon Cha , Im-Soo Park , Hyo-San Lee , Young-Hoo Kim , Jung-Min Oh
IPC分类号： H01L27/108 , H01L29/94
CPC分类号： H01L28/91 , H01L27/10817 , H01L27/10852 , H01L28/87
摘要： In a method of forming a capacitor, a first mold layer pattern including a first insulating material may be formed on a substrate. The first mold layer pattern may have a trench. A supporting layer including a second insulating material may be formed in the trench. The second insulating material may have an etching selectivity with respect to the first insulating material. A second mold layer may be formed on the first mold layer pattern and the supporting layer pattern. A lower electrode may be formed through the second mold layer and the first mold layer pattern. The lower electrode may make contact with a sidewall of the supporting layer pattern. The first mold layer pattern and the second mold layer may be removed. A dielectric layer and an upper electrode may be formed on the lower electrode and the supporting layer pattern.
摘要翻译：在形成电容器的方法中，可以在基板上形成包括第一绝缘材料的第一模层图案。第一模层图案可以具有沟槽。可以在沟槽中形成包括第二绝缘材料的支撑层。第二绝缘材料可以具有相对于第一绝缘材料的蚀刻选择性。可以在第一模层图案和支撑层图案上形成第二模层。可以通过第二模具层和第一模具层图案形成下部电极。下电极可以与支撑层图案的侧壁接触。可以去除第一模层图案和第二模层。电介质层和上电极可以形成在下电极和支撑层图案上。

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