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11. 发明申请

US20070126055A1 Trench insulated gate field effect transistor 审中-公开
标题翻译：沟槽绝缘栅场效应晶体管
公开(公告)号：US20070126055A1
公开(公告)日：2007-06-07
申请号：US10580625
申请日：2004-11-26
申请人： Raymond Hueting , Erwin Hijzen
发明人： Raymond Hueting , Erwin Hijzen
IPC分类号： H01L29/94
CPC分类号： H01L29/7813 , H01L29/0696 , H01L29/0847 , H01L29/0878 , H01L29/402 , H01L29/407 , H01L29/41766 , H01L29/42368 , H01L29/42376 , H01L29/4238 , H01L29/4916
摘要： The invention relates to a trench MOSFET with drain (8), drift (10) body (12) and source (14) regions. The drift region is doped to have a high concentration gradient. A field plate electrode (34) is provided adjacent to the drift region (10) and a gate electrode (32) next to the body region (12).
摘要翻译：本发明涉及一种具有漏极（8），漂移（10）主体（12）和源极（14）区域的沟槽MOSFET。漂移区被掺杂以具有高浓度梯度。邻近漂移区（10）设置的场板电极（34）和邻近体区（12）的栅电极（32）。

12. 发明申请

US20060205222A1 Manufacture of trench-gate semiconductor devices 有权
标题翻译：沟槽栅半导体器件的制造
公开(公告)号：US20060205222A1
公开(公告)日：2006-09-14
申请号：US10538214
申请日：2003-12-08
申请人： Michael In't Zandt , Erwin Hijzen
发明人： Michael In't Zandt , Erwin Hijzen
IPC分类号： H01L21/8242 , H01L21/311
CPC分类号： H01L29/7813 , H01L29/42368 , H01L29/4238 , H01L29/511 , H01L29/513 , H01L29/518
摘要： A method of manufacturing a trench-gate semiconductor device (1), the method including forming trenches (20) in a semiconductor body (10) in an active transistor cell area of the device, the trenches (20) each having a trench bottom and trench sidewalls, and providing silicon oxide gate insulation (21) in the trenches such that the gate insulation (33) at the trench bottoms is thicker than the gate insulation (21) at the trench sidewalls in order to reduce the gate-drain capacitance of the device. The method includes, after forming the trenches (20), the steps of: (a) forming a silicon oxide layer (21) at the trench bottoms and trench sidewalls; (b) depositing a layer of doped polysilicon (31) adjacent the trench bottoms and trench side walls; (c) forming silicon nitride spacers (32) on the doped polysilicon (21) adjacent the trench sidewalls leaving the doped polysilicon exposed at the trench bottoms; (d) thermally oxidising the exposed doped polysilicon to grow said thicker gate insulation (33) at the trench bottoms; (e) removing the silicon nitride spacers (32); and (f) depositing gate conductive material (34) within the trenches to form a gate electrode for the device. The final thickness of the thicker gate insulation (33) at the trench bottoms is well controlled by the thickness of the layer of doped polysilicon (31) deposited in step (b). Also the doped (preferably greater than 5 e 19 cm-3) polysilicon oxidises fast at low temperatures (preferably 700-800° C.), reducing the risk of diffusing (e.g. p body) implantations present in the device at that stage.
摘要翻译：一种制造沟槽栅极半导体器件（1）的方法，所述方法包括在器件的有源晶体管单元区域中的半导体本体（10）中形成沟槽（20），所述沟槽（20）各自具有沟槽底部和沟槽侧壁，并且在沟槽中提供氧化硅栅极绝缘体（21），使得在沟槽底部处的栅极绝缘体（33）比沟槽侧壁处的栅极绝缘体（21）更厚，以便降低栅极 - 漏极电容装置。该方法包括在形成沟槽（20）之后的步骤：（a）在沟槽底部和沟槽侧壁处形成氧化硅层（21）; （b）在沟槽底部和沟槽侧壁附近沉积一层掺杂多晶硅（31）; （c）在与沟槽侧壁相邻的掺杂多晶硅（21）上形成氮化硅间隔物（32），留下在沟槽底部暴露的掺杂多晶硅; （d）热氧化暴露的掺杂多晶硅以在沟槽底部生长所述较厚的栅极绝缘体（33）; （e）去除氮化硅间隔物（32）; 和（f）在所述沟槽内淀积栅极导电材料（34）以形成所述器件的栅电极。沟槽底部较厚的栅极绝缘体（33）的最终厚度由步骤（b）中沉积的掺杂多晶硅层（31）的厚度很好地控制。此外，掺杂（优选大于5埃19厘米3）的多晶硅在低温（优选700-800℃）下快速氧化，降低了在该阶段存在于器件中的扩散（例如p体）植入的风险。

13. 发明申请

US20050156232A1 Edge termination in MOS transistors 失效
公开(公告)号：US20050156232A1
公开(公告)日：2005-07-21
申请号：US11066408
申请日：2005-02-25
申请人： Raymond Hueting , Erwin Hijzen , Michael In't Zandt
发明人： Raymond Hueting , Erwin Hijzen , Michael In't Zandt
IPC分类号： H01L29/06 , H01L29/40 , H01L29/423 , H01L29/739 , H01L29/78 , H01L29/76 , H01L21/336
CPC分类号： H01L29/7813 , H01L29/0696 , H01L29/402 , H01L29/407 , H01L29/4236 , H01L29/4238 , H01L29/7397 , H01L29/7811
摘要： A RESURF trench gate MOSFET has a sufficiently small pitch (close spacing of neighbouring trenches) that intermediate areas of the drain drift region are depleted in the blocking condition of the MOSFET. However, premature breakdown can still occur in this known device structure at the perimeter/edge of the active device area and/or adjacent the gate bondpad. To counter premature breakdown, the invention adopts two principles: the gate bondpad is either connected to an underlying stripe trench network surrounded by active cells, or is directly on top of the active cells, and a compatible 2D edge termination scheme is provided around the RESURF active device area. These principles can be implemented in various cellular layouts e.g. a concentric annular device geometry, which may be circular or rectangular or ellipsoidal, in the active area and in the edge termination, or a device array of such concentric hexagonal or circular stripe cells, or a device array of square active cells with stripe edge cells, or a device array of hexagonal active cells with an edge termination of hexagonal edge cells.

14. 发明申请

US20090166753A1 Semiconductor Device and Method of Manufacturing Such a Device 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20090166753A1
公开(公告)日：2009-07-02
申请号：US12304506
申请日：2007-06-12
申请人： Erwin Hijzen , Joost Melai , Wibo D. Van Noort , Johannes J.T.M Donkers , Philippe Meunier-Beillard , Andreas M. Piontek , Li Jen Choi , Stefaan Van Huylenbroeck
发明人： Erwin Hijzen , Joost Melai , Wibo D. Van Noort , Johannes J.T.M Donkers , Philippe Meunier-Beillard , Andreas M. Piontek , Li Jen Choi , Stefaan Van Huylenbroeck
IPC分类号： H01L27/06 , H01L21/8249
CPC分类号： H01L27/0623 , H01L21/8249 , H01L29/456 , H01L29/66242 , H01L29/7378
摘要： The invention relates to a semiconductor device (10) with a substrate (11) and a semiconductor body (1) comprising a bipolar transistor with in that order a collector region (2), a base region (3), and an emitter region (4), wherein the semiconductor body comprises a projecting mesa (5) comprising at least a portion of the collector region (2) and the base region (3), which mesa is surrounded by an isolation region (6). According to the invention, the semiconductor device (10) also comprises a field effect transistor with a source region, a drain region, an interposed channel region, a superimposed gate dielectric (7), and a gate region (8), which gate region (8) forms a highest part of the field effect transistor, and the height of the mesa (5) is greater than the height of the gate region (8). This device can be manufactured inexpensively and easily by a method according to the invention, and the bipolar transistor can have excellent high-frequency characteristics.
摘要翻译：本发明涉及具有基板（11）和半导体本体（1）的半导体器件（10），该半导体器件（1）包括双极晶体管，依次具有集电极区域（2），基极区域（3）和发射极区域 4），其中半导体主体包括包括集电极区域（2）和基极区域（3）的至少一部分的突出台面（5），该台面由隔离区域（6）包围。根据本发明，半导体器件（10）还包括具有源极区域，漏极区域，插入沟道区域，叠加栅极电介质（7）和栅极区域（8）的场效应晶体管，该栅极区域（8）形成场效应晶体管的最高部分，台面（5）的高度大于栅极区域（8）的高度。该装置可以通过根据本发明的方法廉价且容易地制造，并且双极晶体管可以具有优异的高频特性。

15. 发明申请

US20070120254A1 Semiconductor device comprising a pn-heterojunction 审中-公开
标题翻译：包括pn异质结的半导体器件
公开(公告)号：US20070120254A1
公开(公告)日：2007-05-31
申请号：US10584038
申请日：2004-12-20
申请人： Godefridus Hurkx , Prabhat Agarwal , Abraham Balkenende , Petrus Hubertus Magnee , Melanie Wagemans , Erik Petrus Antonius Bakkers , Erwin Hijzen
发明人： Godefridus Hurkx , Prabhat Agarwal , Abraham Balkenende , Petrus Hubertus Magnee , Melanie Wagemans , Erik Petrus Antonius Bakkers , Erwin Hijzen
IPC分类号： H01L23/48
CPC分类号： H01L29/8611 , B82Y10/00 , H01L29/045 , H01L29/0665 , H01L29/0673 , H01L29/0676 , H01L29/2003 , H01L29/66136 , H01L29/66219 , H01L2924/0002 , H01L2924/00
摘要： An electric device is disclosed comprising a pn-heterojunction (4) formed by a nanowire (3) of 111-V semiconductor material and a semiconductor body (1) comprising a group IV semiconductor material. The nanowire (3) is positioned in direct contact with the surface (2) of the semiconductor body (1) and has a first conductivity type, the semiconductor body (1) has a second conductivity type opposite to the first conductivity type, the nanowire (3) forming with the semiconductor body (1) a pn-heterojunction (4). The nanowire of III-V semiconductor material can be used as a diffusion source (5) of dopant atoms into the semiconductor body. The diffused group III atoms and/or the group V atoms from the III-V material are the dopant atoms forming a region (6) in the semiconductor body in direct contact with the nanowire (3).
摘要翻译：公开了一种电子器件，其包括由111-V族半导体材料的纳米线（3）和包含IV族半导体材料的半导体本体（1）形成的pn异质结（4）。纳米线（3）与半导体本体（1）的表面（2）直接接触并且具有第一导电类型，半导体本体（1）具有与第一导电类型相反的第二导电类型，纳米线（3）与半导体本体（1）形成pn异质结（4）。 III-V族半导体材料的纳米线可以用作半导体本体中掺杂剂原子的扩散源（5）。来自III-V材料的扩散的III族原子和/或V族原子是在半导体本体中与纳米线（3）直接接触形成区域（6）的掺杂剂原子。

16. 发明申请

US20060049453A1 Vertical insulated gate transistor and manufacturing method 有权
标题翻译：垂直绝缘栅晶体管及其制造方法
公开(公告)号：US20060049453A1
公开(公告)日：2006-03-09
申请号：US10538216
申请日：2003-12-08
申请人： Jurriaan Schmitz , Raymond Hueting , Erwin Hijzen , Andreas Montree , Michael In't Zandt , Gerrit Koops
发明人： Jurriaan Schmitz , Raymond Hueting , Erwin Hijzen , Andreas Montree , Michael In't Zandt , Gerrit Koops
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7813 , H01L29/4236 , H01L29/42368 , H01L29/66666 , H01L29/7827
摘要： A vertical insulated gate transistor is manufactured by providing a trench (26) extending through a source layer (8) and a channel layer (6) towards a drain layer (2). A spacer etch is used to form gate portions (20) along the trench side walls, a dielectric material (30) is filled into the trench between the sidewalls gate portions (20), and a gate electrical connection layer (30) is formed at the top of the trench electrically connecting the gate portions (20) across the trench.
摘要翻译：通过向漏极层（2）提供延伸穿过源极层（8）和沟道层（6）的沟槽（26）来制造垂直绝缘栅极晶体管。使用间隔物蚀刻沿着沟槽侧壁形成栅极部分（20），电介质材料（30）被填充到侧壁栅极部分（20）之间的沟槽中，并且栅极电连接层（30）形成在所述沟槽的顶部电连接所述栅极部分（20）穿过所述沟槽。

17. 发明授权

US08173511B2 Method of manufacturing a semiconductor device and semiconductor device obtained with such a method 有权
标题翻译：利用这种方法制造半导体器件和半导体器件的制造方法
公开(公告)号：US08173511B2
公开(公告)日：2012-05-08
申请号：US12094303
申请日：2006-10-29
申请人： Joost Melai , Erwin Hijzen , Philippe Meunier-Beillard , Johannes Josephus Theodorus Marinus Donkers
发明人： Joost Melai , Erwin Hijzen , Philippe Meunier-Beillard , Johannes Josephus Theodorus Marinus Donkers
IPC分类号： H01L21/331 , H01L21/8222
CPC分类号： H01L29/66242 , H01L29/66287
摘要： The invention relates to a method of manufacturing a semiconductor device (10) with a substrate (11) and a semiconductor body (12) which is provided with at least one bipolar transistor having an emitter region (1), a base region (2) and a collector region (3), wherein in the semiconductor body (12) a first semiconductor region (13) is formed that forms one (3) of the collector and emitter regions (1,3) and on the surface of the semiconductor body (12) a stack of layers is formed comprising a first insulating layer (4), a polycrystalline semiconductor layer (5) and a second insulating layer (6) in which stack an opening (7) is formed, after which by non-selective epitaxial growth a further semiconductor layer (22) is deposited of which a monocrystalline horizontal part on the bottom of the opening (7) forms the base region (2) and of which a polycrystalline vertical part (2A) on a side face of the opening (7) is connected to the polycrystalline semiconductor layer (5), after which spacers (S) are formed parallel to the side face of the opening (7) and a second semiconductor region (31) is formed between said spacers (S) forming the other one (1) of the emitter and collector regions (1,3). According to the invention the above method is characterized in that before the further semiconductor layer (22) is deposited, the second insulating layer (6) is provided with an end portion (6A) that viewed in projection overhangs an end portion (5A) of the underlying semiconductor layer (5). In this way bipolar transistor devices can be obtained with good high frequency properties in a cost effective manner.
摘要翻译：本发明涉及一种制造半导体器件（10）的方法，所述半导体器件（10）具有衬底（11）和半导体本体（12），所述半导体器件（12）具有至少一个具有发射极区域（1），基极区域（2）和集电极区域（3），其中在所述半导体本体（12）中形成第一半导体区域（13），所述第一半导体区域形成所述集电极和发射极区域（1,3）中的一个（3）并且在所述半导体主体（12）形成一叠层，其包括形成有开口（7）的第一绝缘层（4），多晶半导体层（5）和第二绝缘层（6），之后通过非选择性外延生长沉积另外的半导体层（22），其中开口（7）的底部上的单晶水平部分形成基部区域（2），并且在该开口的侧面上具有多晶垂直部分（2A）（7）连接到多晶半导体层（5），之后是间隔（S）形成为平行于开口（7）的侧面，并且在形成发射极和集电极区域（1,3）的另一个（1）的所述间隔物（S）之间形成第二半导体区域（31））。根据本发明，上述方法的特征在于，在沉积另外的半导体层（22）之前，第二绝缘层（6）设置有端部（6A），其从突出部分观察到突出部分底层半导体层（5）。以这种方式，可以以成本有效的方式获得具有良好高频特性的双极晶体管器件。

18. 发明申请

US20110186841A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURE THEREOF 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20110186841A1
公开(公告)日：2011-08-04
申请号：US12918524
申请日：2009-02-26
申请人： Philippe Meunier-Bellard , Johannas J. T. M. Donkers , Erwin Hijzen
发明人： Philippe Meunier-Bellard , Johannas J. T. M. Donkers , Erwin Hijzen
IPC分类号： H01L27/06 , H01L21/3065
CPC分类号： H01L21/8249 , H01L27/0623 , H01L29/0649 , H01L29/0821 , H01L29/1004 , H01L29/165 , H01L29/42304 , H01L29/456 , H01L29/66242 , H01L29/7378
摘要： A semiconductor device (10) comprising a bipolar transistor and a field 5 effect transistor within a semiconductor body (1) comprising a projecting mesa (5) within which are at least a portion of a collector region (22c and 22d) and a base region (33c) of the bipolar transistor. The bipolar transistor is provided with an insulating cavity (92b) provided in the collector region (22c and 22d). The insulating cavity (92b) may be provided by providing a layer (33a) in the collector region (22c), creating an access path, for example by selectively etching polysilicon towards monocrystalline, and removing a portion of the layer (33a) to provide the cavity using the access path. The layer (33a) provided in the collector region may be of SiGe:C. By blocking diffusion from the base region the insulating cavity (92b) provides a reduction in the base collector capacitance and can be described as defining the base contact.
摘要翻译：一种半导体器件（10），包括在半导体本体（1）内的双极晶体管和场效应晶体管，包括突出的台面（5），其中集电极区域（22c和22d）的至少一部分和基极区域（33c）。双极晶体管设置有设置在集电区域（22c和22d）中的绝缘腔（92b）。可以通过在集电极区域（22c）中设置层（33a）来提供绝缘腔（92b），从而产生存取路径，例如通过选择性地将多晶硅蚀刻成单晶，并去除层（33a）的一部分以提供使用进入路径的空腔。设置在集电区域中的层（33a）可以是SiGe：C。通过阻挡从基极区域的扩散，绝缘腔（92b）提供基极集电极电容的减小，并且可以被描述为限定基极接触。

19. 发明授权

US07868424B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07868424B2
公开(公告)日：2011-01-11
申请号：US11658227
申请日：2005-07-07
申请人： Godefridus Adrianus Maria Hurkx , Prabhat Agarwal , Erwin Hijzen , Raymond Josephus Engelbart Hueting
发明人： Godefridus Adrianus Maria Hurkx , Prabhat Agarwal , Erwin Hijzen , Raymond Josephus Engelbart Hueting
IPC分类号： H01L21/02
CPC分类号： H01L29/0821 , B82Y10/00 , H01L29/06 , H01L29/0665 , H01L29/0673 , H01L29/0676 , H01L29/08 , H01L29/423 , H01L29/42304 , H01L29/66242 , H01L29/737 , H01L29/7378
摘要： The invention relates to a semiconductor device (10) with a substrate (11) and a semiconductor body (12) comprising a vertical bipolar transistor with an emitter region, a base region and a collector region (1, 2, 3) of, respectively, a first conductivity type, a second conductivity type opposite to the first conductivity type and the first conductivity type, wherein the collector region (3) comprises a first sub-region (3A) bordering the base region (2) and a second sub-region (3B) bordering the first sub-region (3A) which has a lower doping concentration than the second sub-region (3B), and the transistor is provided with a gate electrode (5) which laterally borders the first sub-region (3A) and by means of which the first sub-region (3A) may be depleted. According to the invention the collector region (3) borders the surface of the semiconductor body (12), while the emitter region (1) is recessed in the semiconductor body (12), and the collector region (3) forms part of a mesa structure (6) formed at the surface of the semiconductor body (12). Such a device (10) has very favorable properties at high frequencies and high voltages and, moreover, is easy to manufacture. In a preferred embodiment the collector (3) comprises a nanowire (30) forming the mesa structure (6).
摘要翻译：本发明涉及一种具有衬底（11）和半导体本体（12）的半导体器件（10），该半导体器件包括分别具有发射极区，基极区和集电极区（1,2,3）的垂直双极晶体管，第一导电类型，与第一导电类型和第一导电类型相反的第二导电类型，其中集电极区域（3）包括与基极区域（2）接壤的第一子区域（3A）与第二子区域（3A）接合的第一子区域（3A）的区域（3B），其具有比第二子区域（3B）低的掺杂浓度，并且晶体管设置有与第一子区域横向相邻的栅电极（5） 3A），并且借助于此可以使第一子区域（3A）耗尽。根据本发明，集电极区域（3）与半导体本体（12）的表面相接触，而发射极区域（1）凹入半导体本体（12）中，并且集电极区域（3）形成台面的一部分结构（6）形成在半导体本体（12）的表面。这种装置（10）在高频和高电压下具有非常有利的特性，而且易于制造。在优选实施例中，收集器（3）包括形成台面结构（6）的纳米线（30）。

20. 发明申请

US20100047987A1 METHOD OF FABRICATING A BIPOLAR TRANSISTOR 审中-公开
标题翻译：制造双极晶体管的方法
公开(公告)号：US20100047987A1
公开(公告)日：2010-02-25
申请号：US11913048
申请日：2006-04-24
申请人： Johannes Josephus Theodorus Marin Donkers , Erwin Hijzen , Wibo Daniel Van Noort
发明人： Johannes Josephus Theodorus Marin Donkers , Erwin Hijzen , Wibo Daniel Van Noort
IPC分类号： H01L21/331
CPC分类号： H01L29/66272 , H01L21/76224 , H01L27/0641 , H01L27/0647 , H01L29/6625 , H01L29/66265 , H01L29/732 , H01L29/735
摘要： The invention provides a method for fabricating a bipolar transistor applying a standard shallow trench isolation fabrication method to simultaneously form a vertical bipolar transistor (29) or a lateral bipolar transistor (49) in a first trench (5, 50) and a shallow trench isolation region (27, 270) in a second trench (7, 70). Further, the fabrication method may simultaneously form a vertical bipolar transistor (27) in the first trench (5, 50), a lateral bipolar transistor (49) in a third trench and a shallow trench isolation region (27, 270) in the second trench (7, 70).
摘要翻译：本发明提供一种用于制造双极晶体管的方法，其应用标准浅沟槽隔离制造方法，以在第一沟槽（5,50）和浅沟槽隔离中同时形成垂直双极晶体管（29）或横向双极晶体管（49）区域（27,270）在第二沟槽（7,70）中。此外，制造方法可以同时在第一沟槽（5,50）中形成垂直双极晶体管（27），在第三沟槽中形成横向双极晶体管（49），在第二沟槽中形成浅沟槽隔离区域（27,270）沟槽（7,70）。

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