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1. 发明申请

US20090166753A1 Semiconductor Device and Method of Manufacturing Such a Device 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20090166753A1
公开(公告)日：2009-07-02
申请号：US12304506
申请日：2007-06-12
申请人： Erwin Hijzen , Joost Melai , Wibo D. Van Noort , Johannes J.T.M Donkers , Philippe Meunier-Beillard , Andreas M. Piontek , Li Jen Choi , Stefaan Van Huylenbroeck
发明人： Erwin Hijzen , Joost Melai , Wibo D. Van Noort , Johannes J.T.M Donkers , Philippe Meunier-Beillard , Andreas M. Piontek , Li Jen Choi , Stefaan Van Huylenbroeck
IPC分类号： H01L27/06 , H01L21/8249
CPC分类号： H01L27/0623 , H01L21/8249 , H01L29/456 , H01L29/66242 , H01L29/7378
摘要： The invention relates to a semiconductor device (10) with a substrate (11) and a semiconductor body (1) comprising a bipolar transistor with in that order a collector region (2), a base region (3), and an emitter region (4), wherein the semiconductor body comprises a projecting mesa (5) comprising at least a portion of the collector region (2) and the base region (3), which mesa is surrounded by an isolation region (6). According to the invention, the semiconductor device (10) also comprises a field effect transistor with a source region, a drain region, an interposed channel region, a superimposed gate dielectric (7), and a gate region (8), which gate region (8) forms a highest part of the field effect transistor, and the height of the mesa (5) is greater than the height of the gate region (8). This device can be manufactured inexpensively and easily by a method according to the invention, and the bipolar transistor can have excellent high-frequency characteristics.
摘要翻译：本发明涉及具有基板（11）和半导体本体（1）的半导体器件（10），该半导体器件（1）包括双极晶体管，依次具有集电极区域（2），基极区域（3）和发射极区域 4），其中半导体主体包括包括集电极区域（2）和基极区域（3）的至少一部分的突出台面（5），该台面由隔离区域（6）包围。根据本发明，半导体器件（10）还包括具有源极区域，漏极区域，插入沟道区域，叠加栅极电介质（7）和栅极区域（8）的场效应晶体管，该栅极区域（8）形成场效应晶体管的最高部分，台面（5）的高度大于栅极区域（8）的高度。该装置可以通过根据本发明的方法廉价且容易地制造，并且双极晶体管可以具有优异的高频特性。

2. 发明申请

US20100237434A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SUCH A DEVICE 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20100237434A1
公开(公告)日：2010-09-23
申请号：US11993296
申请日：2006-06-22
申请人： Wibo D. Van Noort , Jan Sonsky , Philippe Meunier-Beillard , Erwin Hijzen
发明人： Wibo D. Van Noort , Jan Sonsky , Philippe Meunier-Beillard , Erwin Hijzen
IPC分类号： H01L27/06 , H01L29/68 , H01L21/70
CPC分类号： H01L29/7378 , B82Y20/00 , H01L21/743 , H01L21/76229 , H01L21/8222 , H01L21/8249 , H01L29/1087 , H01L29/41708 , H01L29/42384 , H01L29/66242 , H01L29/78 , H01L29/78645 , H01L29/78696 , H01L31/035236 , H01L31/1812 , Y02E10/50
摘要： The invention relates to a semiconductor device (10) with a substrate (11) and a semiconductor body (12) of silicon which comprises an active region (A) with a transistor (T) and a passive region (P) surrounding the active region (A) and which is provided with a buried conducting region (1) of a metallic material that is connected to a conductive region (2) of a metallic material sunken from the surface of the semiconductor body (12), by which the buried conductive region (1) is made electrically connectable at the surface of the semiconductor body (12). According to the invention, the buried conducting region (1) is made at the location of the active region (A) of the semiconductor body (12). In this way, a very low buried resistance can be locally created in the active region (A) in the semiconductor body (12), using a metallic material that has completely different crystallographic properties from the surrounding silicon. This is made possible by using a method according to the invention. Such a buried low resistance offers substantial advantages both for a bipolar transistor and for a MOS transistor.
摘要翻译：本发明涉及具有衬底（11）和硅的半导体本体（12）的半导体器件（10），其包括具有晶体管（T）的有源区（A）和围绕有源区的无源区（P）（A），并且设置有金属材料的埋入导电区域（1），所述埋入导电区域连接到从所述半导体主体（12）的表面凹陷的金属材料的导电区域（2），所述埋入导电区域区域（1）在半导体本体（12）的表面处可电连接。根据本发明，在半导体本体（12）的有源区（A）的位置处形成掩埋导电区（1）。以这种方式，可以使用与周围的硅具有完全不同的晶体学特性的金属材料，在半导体本体（12）的有源区（A）中局部地产生非常低的掩埋电阻。这可以通过使用根据本发明的方法来实现。这种埋下的低电阻为双极晶体管和MOS晶体管提供了显着的优点。

3. 发明申请

US20100025808A1 Bipolar Transistor And Method Of Fabricating The Same 有权
标题翻译：双极晶体管及其制造方法
公开(公告)号：US20100025808A1
公开(公告)日：2010-02-04
申请号：US11814281
申请日：2006-01-12
申请人： Johannes J. T. M. Donkers , Wibo D. Van Noort , Philippe Meunier-Beillard
发明人： Johannes J. T. M. Donkers , Wibo D. Van Noort , Philippe Meunier-Beillard
IPC分类号： H01L29/73 , H01L21/331
CPC分类号： H01L29/66242 , H01L29/66272 , H01L29/732 , H01L29/7378
摘要： The invention provides a bipolar transistor with a reduced collector series resistance integrated in a trench (4, 44) of a standard CMOS shallow trench isolation region. The bipolar transistor includes a collector region (6, 34) manufactured in one fabrication step, therefore having a shorter conductive path with a reduced collector series resistance, improving the high frequency performance of the bipolar transistor. The bipolar transistor further includes a base region (8, 22, 38) with a first part on a selected portion of the collector region (6, 34), which is on the bottom of the trench (4, 44), and an emitter region (10, 24, 39) on a selected portion of the first part of the base region (8, 22, 38). A base contact (11, 26, 51) electrically contacts the base region (8, 22, 38) on a second part of the base region (8, 22, 38), which is on an insulating region (2, 42). The collector region (6, 34) is electrically contacted on top of a protrusion (5, 45) with a collector contact (13, 25, 50).
摘要翻译：本发明提供了集成在标准CMOS浅沟槽隔离区的沟槽（4,44）中的集电极串联电阻降低的双极晶体管。双极晶体管包括在一个制造步骤中制造的集电极区域（6,34），因此具有较短的集电极串联电阻的导电路径，从而改善了双极晶体管的高频性能。双极晶体管还包括在沟槽（4,44）的底部上的集电极区域（6,34）的选定部分上的第一部分的基极区域（8,22,38）和发射极区域（10,24,39）在基区（8,22,38）的第一部分的选定部分上。在绝缘区域（2,42）上的基极区域（8,22,38）的第二部分上的基极接触部分（11,26,31）与基极区域（8,22,38）电接触。集电区域（6,34）与突起（5,45）的顶部与集电极接触（13,25,50）电接触。

4. 发明授权

US07906403B2 Bipolar transistor and method of fabricating the same 有权
标题翻译：双极晶体管及其制造方法
公开(公告)号：US07906403B2
公开(公告)日：2011-03-15
申请号：US11814281
申请日：2006-01-12
申请人： Johannes JTM Donkers , Wibo D. Van Noort , Philippe Meunier-Beillard , Sebastien Nuttinck , Erwin Hujzen , Francois Neuilly
发明人： Johannes JTM Donkers , Wibo D. Van Noort , Philippe Meunier-Beillard , Sebastien Nuttinck , Erwin Hujzen , Francois Neuilly
IPC分类号： H01L21/331 , H01L21/8222
CPC分类号： H01L29/66242 , H01L29/66272 , H01L29/732 , H01L29/7378
摘要： Consistent with an example embodiment, there is a bipolar transistor with a reduced collector series resistance integrated in a trench of a standard CMOS shallow trench isolation region. The bipolar transistor includes a collector region manufactured in one fabrication step, therefore having a shorter conductive path with a reduced collector series resistance, improving the high frequency performance of the bipolar transistor. The bipolar transistor further includes a base region with a first part on a selected portion of the collector region (6, 34), which is on the bottom of the trench, and an emitter region on a selected portion of the first part of the base region. A base contact electrically contacts the base region on a second part of the base region, which is on an insulating region. The collector region is electrically contacted on top of a protrusion with a collector contact.
摘要翻译：与示例实施例一致，存在集成在标准CMOS浅沟槽隔离区的沟槽中的集电极串联电阻减小的双极晶体管。双极晶体管包括在一个制造步骤中制造的集电极区域，因此具有较短的集电极串联电阻的导电路径，从而改善了双极晶体管的高频性能。所述双极晶体管还包括基极区域，所述基极区域在所述沟槽的底部上的所述集电极区域（6,34）的选定部分上具有第一部分，并且所述基极的所述第一部分的选定部分上的发射极区域地区。基极触点与绝缘区域上的基极区域的第二部分上的基极区域电接触。集电极区域在突出部的顶部与集电极触点电接触。

5. 发明授权

US07838374B2 Method of manufacturing a bipolar transistor 有权
标题翻译：制造双极晶体管的方法
公开(公告)号：US07838374B2
公开(公告)日：2010-11-23
申请号：US12282300
申请日：2007-03-09
申请人： Wibo D. Van Noort , Jan Zonsky , Andreas M. Piontek
发明人： Wibo D. Van Noort , Jan Zonsky , Andreas M. Piontek
IPC分类号： H01L21/331
CPC分类号： H01L29/7378 , H01L29/0826 , H01L29/66242 , H01L29/66272 , H01L29/7322 , H01L29/7371
摘要： The invention relates to a method of manufacturing a bipolar transistor on a semiconductor substrate (11) which is provided with a first, a second and a third layer (1,2,3) of a first, second and third semiconductor material respectively, all of a first conductivity type. A first portion of the second layer (2) is transformed into a buried isolation region (15) comprising a first electrically insulating material. A first semiconductor region (6) of the first conductivity type, comprising, for example, a collector region, is formed from a second portion of the second layer (2) adjoining the buried isolation region (15) and a portion of the first layer (1) adjoining the second portion of the second layer (2). Then a base region (7) is formed on the buried isolation region (15) and on the first semiconductor region (6) by transforming the third layer (3) into a second conductivity type, which is opposite to the first conductivity type. Thereafter a second semiconductor region (8) of the first conductivity type, comprising, for example, an emitter region, is formed on a part of the base region (7). This method provides for the formation of a bipolar transistor with an advantageous decrease of the extrinsic collector to base region (6,7) capacitance by the fact that the value of this capacitance is mainly determined by the buried isolation region (15) which has a substantially lower dielectric constant than that of the collector to base region (6,7) junction.
摘要翻译：本发明涉及在半导体衬底（11）上制造双极晶体管的方法，该半导体衬底分别具有第一，第二和第三半导体材料的第一，第二和第三层（1,2,3），全部的第一导电类型。第二层（2）的第一部分被转换成包括第一电绝缘材料的掩埋隔离区（15）。第一导电类型的第一半导体区域（6）由包括例如集电极区域的第一半导体区域（6）由毗邻掩埋隔离区域（15）的第二层（2）的第二部分和第一层（1）邻接第二层（2）的第二部分。然后，通过将第三层（3）转变成与第一导电类型相反的第二导电类型，在掩埋隔离区（15）和第一半导体区（6）上形成基极区（7）。此后，在基极区域（7）的一部分上形成第一导电类型的第二半导体区域（8），其包括例如发射极区域。该方法通过以下事实来形成双极性晶体管，该双极晶体管有利于减少外部集电极到基极区域（6,7）的电容，该电容值主要由埋入隔离区域（15）确定，比集电极到基极区（6,7）结的介电常数要低得多。

6. 发明申请

US20090053872A1 METHOD OF MANUFACTURING A BIPOLAR TRANSISTOR 有权
标题翻译：制造双极晶体管的方法
公开(公告)号：US20090053872A1
公开(公告)日：2009-02-26
申请号：US12282300
申请日：2007-03-09
申请人： Wibo D. Van Noort , Jan Sonsky , Andreas M. Piontek
发明人： Wibo D. Van Noort , Jan Sonsky , Andreas M. Piontek
IPC分类号： H01L21/331
CPC分类号： H01L29/7378 , H01L29/0826 , H01L29/66242 , H01L29/66272 , H01L29/7322 , H01L29/7371
摘要： The invention relates to a method of manufacturing a bipolar transistor on a semiconductor substrate (11) which is provided with a first, a second and a third layer (1,2,3) of a first, second and third semiconductor material respectively, all of a first conductivity type. A first portion of the second layer (2) is transformed into a buried isolation region (15) comprising a first electrically insulating material. A first semiconductor region (6) of the first conductivity type, comprising, for example, a collector region, is formed from a second portion of the second layer (2) adjoining the buried isolation region (15) and a portion of the first layer (1) adjoining the second portion of the second layer (2). Then a base region (7) is formed on the buried isolation region (15) and on the first semiconductor region (6) by transforming the third layer (3) into a second conductivity type, which is opposite to the first conductivity type. Thereafter a second semiconductor region (8) of the first conductivity type, comprising, for example, an emitter region, is formed on a part of the base region (7). This method provides for the formation of a bipolar transistor with an advantageous decrease of the extrinsic collector to base region (6,7) capacitance by the fact that the value of this capacitance is mainly determined by the buried isolation region (15) which has a substantially lower dielectric constant than that of the collector to base region (6,7) junction.
摘要翻译：本发明涉及在半导体衬底（11）上制造双极晶体管的方法，该半导体衬底分别具有第一，第二和第三半导体材料的第一，第二和第三层（1,2,3），全部的第一导电类型。第二层（2）的第一部分被转换成包括第一电绝缘材料的掩埋隔离区（15）。第一导电类型的第一半导体区域（6）由包括例如集电极区域的第一半导体区域（6）由毗邻掩埋隔离区域（15）的第二层（2）的第二部分和第一层（1）邻接第二层（2）的第二部分。然后，通过将第三层（3）转变成与第一导电类型相反的第二导电类型，在掩埋隔离区（15）和第一半导体区（6）上形成基极区（7）。此后，在基极区域（7）的一部分上形成第一导电类型的第二半导体区域（8），其包括例如发射极区域。该方法通过以下事实来形成双极性晶体管，该双极晶体管有利于减少外部集电极到基极区域（6,7）的电容，该电容值主要由埋入隔离区域（15）确定，比集电极到基极区（6,7）结的介电常数要低得多。

7. 发明授权

US07932156B2 Bipolar transistor having a second, base-comprising region consisting of a first layer, a second, constrictive, layer, and a third layer 有权
标题翻译：具有由第一层，第二层，缩缩层和第三层组成的第二基底包含区域的双极晶体管
公开(公告)号：US07932156B2
公开(公告)日：2011-04-26
申请号：US11997231
申请日：2006-07-26
申请人： Johannes J. T. M. Donkers , Wibo D. Van Noort , Francois Neuilly
发明人： Johannes J. T. M. Donkers , Wibo D. Van Noort , Francois Neuilly
IPC分类号： H01L21/331
CPC分类号： H01L29/7378 , H01L21/26506 , H01L21/26513 , H01L29/0649 , H01L29/1004 , H01L29/66242 , H01L29/66272 , H01L29/732
摘要： The invention relates to a semiconductor device (10) with a substrate (12) and a semiconductor body (11) of silicon comprising a bipolar transistor with an emitter region, a base region and a collector region (1,2,3) first conductivity type, a second conductivity type opposite to said first conductivity type and the first conductivity type, respectively, with a first semiconductor region (3) comprising the collector region or the emitter region being formed in the semiconductor body (11), on top of which a second semiconductor region (2) comprising the base region is present, on top of which a third semiconductor region (1) comprising the other of said collector region and said emitter region is present, said semiconductor body (11) being provided with a constriction at the location of the transition between the first and the second semiconductor region (3, 2), which constriction has been formed by means of an electrically insulating region (26, 27) buried in the semiconductor body (11). According to the invention a part of the semiconductor body that is formed above the buried electrically insulating region (26,27) is monocrystalline. This enables a strong lateral miniaturization of the device and results in excellent high frequency properties of the transistor. Such a device (10) is possible thanks to its manufacture with a method of manufacturing according to the invention.
摘要翻译：本发明涉及具有衬底（12）和硅的半导体本体（11）的半导体器件（10），其包括具有发射极区域，基极区域和集电极区域（1,2,3）的双极晶体管的第一导电性类型，分别与所述第一导电类型和第一导电类型相反的第二导电类型，其中第一半导体区域（3）包括形成在半导体本体（11）中的集电极区域或发射极区域，其顶部存在包括基极区域的第二半导体区域（2），其上存在包括所述集电极区域和所述发射极区域中的另一个的第三半导体区域（1），所述半导体本体（11）设置有收缩部在第一和第二半导体区域（3,2）之间的过渡位置处，通过埋在半导体本体（11）中的电绝缘区域（26,27）形成该收缩）。根据本发明，形成在掩埋电绝缘区域（26,27）上方的半导体本体的一部分是单晶的。这使得器件的强大的侧向小型化并且导致晶体管的优异的高频特性。由于通过根据本发明的制造方法的制造，这种装置（10）是可能的。

8. 发明授权

US07923345B2 Methods relating to trench-based support structures for semiconductor devices 有权
标题翻译：涉及半导体器件的基于沟槽的支撑结构的方法
公开(公告)号：US07923345B2
公开(公告)日：2011-04-12
申请号：US12158988
申请日：2006-12-18
申请人： Jan Sonsky , Wibo D. Van Noort
发明人： Jan Sonsky , Wibo D. Van Noort
IPC分类号： H01L21/76 , H01L21/302 , H01L21/461
CPC分类号： H01L21/76229 , B81C1/00158 , B81C2201/014
摘要： A method of manufacturing a semiconductor device wherein a laminate structure comprising a sacrificial layer is sandwiched between two etch stop layers (8,11) and which separates a semiconductor membrane (9) from a bulk substrate (1) is used to provide an underetched structure. Access trenches (4) and support trenches (5) are formed in the layered structure through the thickness of the semiconductor layer (9) and through the upper etch stop layer (8). The support trenches extend deeper through the sacrificial layer (12) and the lower etch stop layer and are filled. The sacrificial layer is exposed and etched away selectively to the etch stop layers to form a cavity (30) and realise a semiconductor membrane which is attached to the bulk substrate via a vertical support structure comprising the filled support trenches.
摘要翻译：一种制造半导体器件的方法，其中包括牺牲层的层压结构被夹在两个蚀刻停止层（8,11）之间，并且将半导体膜（9）与体基板（1）分离，以提供未刻划的结构。通过半导体层（9）的厚度和通过上蚀刻停止层（8）在层状结构中形成通路沟槽（4）和支撑沟槽（5）。支撑沟槽通过牺牲层（12）和下蚀刻停止层更深地延伸并被填充。牺牲层被暴露并被选择性地蚀刻到蚀刻停止层以形成空腔（30）并且实现通过包括填充的支撑沟槽的垂直支撑结构附接到主体衬底的半导体膜。

9. 发明申请

US20090227091A1 METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20090227091A1
公开(公告)日：2009-09-10
申请号：US12158988
申请日：2006-12-18
申请人： Jan Sonsky , Wibo D. Van Noort
发明人： Jan Sonsky , Wibo D. Van Noort
IPC分类号： H01L21/20
CPC分类号： H01L21/76229 , B81C1/00158 , B81C2201/014
摘要： A method of manufacturing a semiconductor device wherein a laminate structure comprising a sacrificial layer is sandwiched between two etch stop layers (8,11) and which separates a semiconductor membrane (9) from a bulk substrate (1) is used to provide an underetched structure. Access trenches (4) and support trenches (5) are formed in the layered structure through the thickness of the semiconductor layer (9) and through the upper etch stop layer (8). The support trenches extend deeper through the sacrificial layer (12) and the lower etch stop layer and are filled. The sacrificial layer is exposed and etched away selectively to the etch stop layers to form a cavity (30) and realise a semiconductor membrane which is attached to the bulk substrate via a vertical support structure comprising the filled support trenches.
摘要翻译：一种制造半导体器件的方法，其中包括牺牲层的层压结构被夹在两个蚀刻停止层（8,11）之间，并且将半导体膜（9）与体基板（1）分离，以提供未刻划的结构。通过半导体层（9）的厚度和通过上蚀刻停止层（8）在层状结构中形成通路沟槽（4）和支撑沟槽（5）。支撑沟槽通过牺牲层（12）和下蚀刻停止层更深地延伸并被填充。牺牲层被暴露并被选择性地蚀刻到蚀刻停止层以形成空腔（30）并且实现通过包括填充的支撑沟槽的垂直支撑结构附接到主体衬底的半导体膜。

10. 发明申请

US20090174034A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SUCH A DEVICE 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20090174034A1
公开(公告)日：2009-07-09
申请号：US11997231
申请日：2006-07-26
申请人： Johannes J., T., M. Donkers , Wibo D. Van Noort , Francois Neuilly
发明人： Johannes J., T., M. Donkers , Wibo D. Van Noort , Francois Neuilly
IPC分类号： H01L29/73 , H01L21/331
CPC分类号： H01L29/7378 , H01L21/26506 , H01L21/26513 , H01L29/0649 , H01L29/1004 , H01L29/66242 , H01L29/66272 , H01L29/732
摘要： The invention relates to a semiconductor device (10) with a substrate (12) and a semiconductor body (11) of silicon comprising a bipolar transistor with an emitter region, a base region and a collector region (1,2,3) first conductivity type, a second conductivity type opposite to said first conductivity type and the first conductivity type, respectively, with a first semiconductor region (3) comprising the collector region or the emitter region being formed in the semiconductor body (11), on top of which a second semiconductor region (2) comprising the base region is present, on top of which a third semiconductor region (1) comprising the other of said collector region and said emitter region is present, said semiconductor body (11) being provided with a constriction at the location of the transition between the first and the second semiconductor region (3, 2), which constriction has been formed by means of an electrically insulating region (26, 27) buried in the semiconductor body (11). According to the invention a part of the semiconductor body that is formed above the buried electrically insulating region (26,27) is monocrystalline. This enables a strong lateral miniaturization of the device and results in excellent high frequency properties of the transistor. Such a device (10) is possible thanks to its manufacture with a method of manufacturing according to the invention.
摘要翻译：本发明涉及具有衬底（12）和硅的半导体本体（11）的半导体器件（10），其包括具有发射极区域，基极区域和集电极区域（1,2,3）的双极晶体管的第一导电性类型，分别与所述第一导电类型和第一导电类型相反的第二导电类型，其中第一半导体区域（3）包括形成在半导体本体（11）中的集电极区域或发射极区域，其顶部存在包括基极区域的第二半导体区域（2），其上存在包括所述集电极区域和所述发射极区域中的另一个的第三半导体区域（1），所述半导体本体（11）设置有收缩部在第一和第二半导体区域（3,2）之间的过渡位置处，通过埋在半导体本体（11）中的电绝缘区域（26,27）形成该收缩部）。根据本发明，形成在掩埋电绝缘区域（26,27）上方的半导体本体的一部分是单晶的。这使得器件的强大的侧向小型化并且导致晶体管的优异的高频特性。由于通过根据本发明的制造方法的制造，这种装置（10）是可能的。

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