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11. 发明授权

US06154079A Negative delay circuit operable in wide band frequency 有权
标题翻译：负延迟电路可在宽带频率下工作
公开(公告)号：US06154079A
公开(公告)日：2000-11-28
申请号：US177818
申请日：1998-10-23
申请人： Jae-Goo Lee , Young-Hyun Jun
发明人： Jae-Goo Lee , Young-Hyun Jun
IPC分类号： G06F1/10 , G11C7/22 , H03K5/13 , H03K5/14
CPC分类号： G11C7/222 , G06F1/10 , G11C7/22 , H03K5/131
摘要： A negative delay circuit (NDC) has an NDC array operated in a high frequency. The circuit varies a number of unit delay stages at an input stage of the NDC array according to a locking fail signal in a low frequency region. The NDC can carry out a negative delay operation in a wide band even when a number of the stages in the NDC array is small. The present invention decreases a size of a chip, and in addition, reduces an unnecessary current consumption by preventing a locking from re-occurring at a stage in a back portion because the NDC array has a delay value less than one clock.
摘要翻译：负延迟电路（NDC）具有以高频率操作的NDC阵列。该电路根据低频区域中的锁定失败信号，在NDC阵列的输入级上改变多个单位延迟级。 NDC可以在宽频带中进行负延迟操作，即使在NDC阵列中的多个级数较小时也是如此。本发明减小了芯片的尺寸，并且由于NDC阵列具有小于一个时钟的延迟值，因此通过防止在后部的一个阶段中的锁定再次发生而减少不必要的电流消耗。

12. 发明授权

US5966337A Method for overdriving bit line sense amplifier 失效
标题翻译：驱动位线读出放大器的方法
公开(公告)号：US5966337A
公开(公告)日：1999-10-12
申请号：US958932
申请日：1997-10-28
申请人： Jae-Goo Lee , Young-Hyun Jun
发明人： Jae-Goo Lee , Young-Hyun Jun
IPC分类号： G11C11/409 , G11C7/06 , G11C11/413 , G11C7/00
CPC分类号： G11C7/065
摘要： A bit line sense amplifier overdriving method includes a step for reaching a bit line data signal to a full swing level by driving the sense amplifiers in accordance with an overdriving voltage in an overdriving pulse interval, when an overdriving pulse signal is generated at points in which the sense amplifiers are enabled and disabled in a data read operation and a data write operation. The method maintains a sufficiently long refresh interval during a refresh operation.
摘要翻译：位线检测放大器过驱动方法包括通过在过驱动脉冲间隔中根据过驱动电压驱动读出放大器来将位线数据信号达到全摆幅电平的步骤，当在其中产生过驱动脉冲信号时，在数据读取操作和数据写入操作中启用和禁用读出放大器。该方法在刷新操作期间保持足够长的刷新间隔。

13. 发明申请

US20080291753A1 Semiconductor memory device and latency signal generating method thereof 有权
标题翻译：半导体存储器件及其等待时间信号产生方法
公开(公告)号：US20080291753A1
公开(公告)日：2008-11-27
申请号：US12219816
申请日：2008-07-29
申请人： Kwang-Il Park , Young-Hyun Jun , Seong-Jin Jang , Ho-Young Song
发明人： Kwang-Il Park , Young-Hyun Jun , Seong-Jin Jang , Ho-Young Song
IPC分类号： G11C7/00 , G11C8/18
CPC分类号： G11C7/1051 , G11C7/1066 , G11C7/1072
摘要： A latency signal generating method and a corresponding semiconductor memory device, among other things, are disclosed. Such a method includes: receiving a clock signal for the semiconductor memory device; receiving a mode characterization signal; providing the DQS; and adapting the duration of a preamble state of the DQS according to the mode characterization signal to promote conformance of a strobe state of the DQS with the clock signal.
摘要翻译：公开了等待信号产生方法和相应的半导体存储器件。这种方法包括：接收半导体存储器件的时钟信号; 接收模式表征信号; 提供DQS; 以及根据模式表征信号调整DQS的前导码状态的持续时间，以促进DQS的选通状态与时钟信号的一致性。

14. 发明授权

US07453745B2 Semiconductor memory device and latency signal generating method thereof 有权
公开(公告)号：US07453745B2
公开(公告)日：2008-11-18
申请号：US11416077
申请日：2006-05-03
申请人： Kwang-Il Park , Young-Hyun Jun , Seong-Jin Jang , Ho-Young Song
发明人： Kwang-Il Park , Young-Hyun Jun , Seong-Jin Jang , Ho-Young Song
IPC分类号： G11C7/00
CPC分类号： G11C7/1051 , G11C7/1066 , G11C7/1072
摘要： A latency signal generating method and a corresponding semiconductor memory device, among other things, are disclosed. Such a method includes: receiving a clock signal for the semiconductor memory device; receiving a mode characterization signal; providing the DQS; and adapting the duration of a preamble state of the DQS according to the mode characterization signal to promote conformance of a strobe state of the DQS with the clock signal.

15. 发明授权

US07348789B2 Integrated circuit device with on-chip setup/hold measuring circuit 失效
标题翻译：具有片上建立/保持测量电路的集成电路器件
公开(公告)号：US07348789B2
公开(公告)日：2008-03-25
申请号：US10972119
申请日：2004-10-21
申请人： Jong-Eon Lee , Young-Hyun Jun
发明人： Jong-Eon Lee , Young-Hyun Jun
IPC分类号： G01R31/02
CPC分类号： G11C29/50012 , G11C29/50
摘要： An integrated circuit device disclosed herein includes a test device and a setup and hold measuring circuit. The setup and hold measuring circuit generates a reference signal and a data signal in response to an external clock signal in a test mode of operation. The test device receives the data signal in response to a reference signal, and outputs the inputted data signal as a setup and hold determining circuit. One of the reference signal and the data signal is a multiphase signal synchronized with the external clock signal. The setup and hold measuring circuit detects whether the output of the test device indicates a valid value of the data signal, and generates the detected result to the external as a setup/hold timing margin through at least one pad.
摘要翻译：本文公开的集成电路装置包括测试装置和建立和保持测量电路。建立和保持测量电路在测试操作模式下响应外部时钟信号产生参考信号和数据信号。测试装置响应于参考信号接收数据信号，并输出输入的数据信号作为建立和保持确定电路。参考信号和数据信号之一是与外部时钟信号同步的多相信号。建立和保持测量电路检测测试装置的输出是否指示数据信号的有效值，并通过至少一个焊盘将检测结果作为建立/保持定时裕度产生到外部。

16. 发明授权

US5461591A Voltage generator for semiconductor memory device 失效
标题翻译：用于半导体存储器件的电压发生器
公开(公告)号：US5461591A
公开(公告)日：1995-10-24
申请号：US161761
申请日：1993-12-02
申请人： Tae-hoon Kim , Young-Hyun Jun
发明人： Tae-hoon Kim , Young-Hyun Jun
IPC分类号： G11C5/14 , G11C7/00 , H03K3/01
CPC分类号： G11C5/147 , G11C5/146 , H01L2924/0002
摘要： A voltage generator for use in a semiconductor memory device suitable for use as a backbias voltage generator, as an internal high voltage generator, or as an internal power voltage generator. The present invention includes: a rectifier for producing a dc voltage power by rectifying clock signals; an oscillator including an odd number of invertors connected in series, and with the output of the last invertor fed back to the first invertor so as to oscillate clock pulses; and one or more bypass circuit connected so as for the output of the first invertor to bypass one or more intermediate invertors, and connected and disconnected by a control switch.
摘要翻译：一种用于半导体存储器件的电压发生器，适用于作为反向电压发生器，作为内部高压发生器或内部电力电压发生器。本发明包括：整流器，用于通过整流时钟信号产生直流电压电力; 包括串联连接的奇数个反相器的振荡器，并且将最后一个反相器的输出反馈到第一反相器以振荡时钟脉冲; 并且连接一个或多个旁路电路，以便使第一反相器的输出绕过一个或多个中间反相器，并由控制开关连接和断开。

17. 发明授权

US08130028B2 CMOS charge pump with improved latch-up immunity 有权
标题翻译： CMOS电荷泵具有提高的闭锁抑制能力
公开(公告)号：US08130028B2
公开(公告)日：2012-03-06
申请号：US12691937
申请日：2010-01-22
申请人： Su-Jin Park , Joung-Yeal Kim , Bai-Sun Kong , Young-Hyun Jun
发明人： Su-Jin Park , Joung-Yeal Kim , Bai-Sun Kong , Young-Hyun Jun
IPC分类号： G05F3/02
CPC分类号： H02M3/07
摘要： A CMOS charge pump with improved latch-up immunity is provided. The CMOS charge pump includes a blocking transistor that disconnects first and second boost nodes from a bulk node in response to a blocking control signal, such that a bulk voltage can be maintained at a predetermined level or higher. The CMOS charge pump in a power-up period first precharges the bulk voltage before the main pump performs a boosting operation and prevents a latch-up phenomenon.
摘要翻译：提供了具有提高的闭锁电阻的CMOS电荷泵。 CMOS电荷泵包括阻塞晶体管，其响应于阻塞控制信号将第一和第二升压节点与体节点断开，使得体电压可以保持在预定水平或更高水平。在上电期间的CMOS电荷泵首先在主泵进行升压操作之前预充电体积电压并且防止闩锁现象。

18. 发明申请

US20100271886A1 Semiconductor memory device and latency signal generating method thereof 审中-公开
公开(公告)号：US20100271886A1
公开(公告)日：2010-10-28
申请号：US12801953
申请日：2010-07-02
申请人： Kwang-II Park , Young-Hyun Jun , Seong-Jin Jang , Ho-Young Song
发明人： Kwang-II Park , Young-Hyun Jun , Seong-Jin Jang , Ho-Young Song
IPC分类号： G11C7/00
CPC分类号： G11C7/1051 , G11C7/1066 , G11C7/1072
摘要： A latency signal generating method and a corresponding semiconductor memory device, among other things, are disclosed. Such a method includes: receiving a clock signal for the semiconductor memory device; receiving a mode characterization signal; providing the DQS; and adapting the duration of a preamble state of the DQS according to the mode characterization signal to promote conformance of a strobe state of the DQS with the clock signal.

19. 发明授权

US07492647B2 Voltage generation circuit and semiconductor memory device including the same 有权
标题翻译：电压产生电路和包括其的半导体存储器件
公开(公告)号：US07492647B2
公开(公告)日：2009-02-17
申请号：US12025442
申请日：2008-02-04
申请人： Hyong-Ryol Hwang , Young-Hyun Jun
发明人： Hyong-Ryol Hwang , Young-Hyun Jun
IPC分类号： G11C7/00
CPC分类号： G11C5/14
摘要： A voltage generation circuit and semiconductor memory device including the same are provided. The voltage generation circuit includes: a voltage level detector, which detects a level of a first high voltage to generate a first high voltage level detection signal and detects a level of a second high voltage to generate a second high voltage level detection signal; a control signal generator, which generates at least four pumping control signals in sequence when the first high voltage level detection signal is active, generates a control signal when the first high voltage level detection signal is inactive, and generates a first one of the at least four pumping control signals in response to a level of a power supply voltage; and a voltage generator, which pumps a boost node in response to the at least four pumping control signals to generate the first high voltage and transmits charge from the boost node to a second high voltage generation terminal in response to the control signal to generate the second high voltage.
摘要翻译：提供了包括该电压产生电路和半导体存储器件的电压产生电路。电压产生电路包括：电压电平检测器，其检测第一高电平的电平以产生第一高电压电平检测信号，并检测第二高电平的电平以产生第二高电压电平检测信号; 控制信号发生器，当所述第一高电压电平检测信号有效时，依次产生至少四个泵送控制信号，当所述第一高电压电平检测信号无效时产生控制信号，并且产生至少四个泵送控制信号响应于电源电压的电平; 以及电压发生器，其响应于所述至少四个泵送控制信号泵送升压节点以产生所述第一高电压，并且响应于所述控制信号将电压从所述升压节点传输到第二高电压发生端子，以产生所述第二高电压高压。

20. 发明申请

US20060120179A1 Voltage generation circuit and semiconductor memory device including the same 有权
公开(公告)号：US20060120179A1
公开(公告)日：2006-06-08
申请号：US11293890
申请日：2005-12-02
申请人： Hyong-Ryol Hwang , Young-Hyun Jun
发明人： Hyong-Ryol Hwang , Young-Hyun Jun
IPC分类号： G11C7/00
CPC分类号： G11C5/14
摘要： A voltage generation circuit and semiconductor memory device including the same are provided. The voltage generation circuit includes: a voltage level detector, which detects a level of a first high voltage to generate a first high voltage level detection signal and detects a level of a second high voltage to generate a second high voltage level detection signal; a control signal generator, which generates at least four pumping control signals in sequence when the first high voltage level detection signal is active, generates a control signal when the first high voltage level detection signal is inactive, and generates a first one of the at least four pumping control signals in response to a level of a power supply voltage; and a voltage generator, which pumps a boost node in response to the at least four pumping control signals to generate the first high voltage and transmits charge from the boost node to a second high voltage generation terminal in response to the control signal to generate the second high voltage.

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