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1. 发明授权

US5461591A Voltage generator for semiconductor memory device 失效
标题翻译：用于半导体存储器件的电压发生器
公开(公告)号：US5461591A
公开(公告)日：1995-10-24
申请号：US161761
申请日：1993-12-02
申请人： Tae-hoon Kim , Young-Hyun Jun
发明人： Tae-hoon Kim , Young-Hyun Jun
IPC分类号： G11C5/14 , G11C7/00 , H03K3/01
CPC分类号： G11C5/147 , G11C5/146 , H01L2924/0002
摘要： A voltage generator for use in a semiconductor memory device suitable for use as a backbias voltage generator, as an internal high voltage generator, or as an internal power voltage generator. The present invention includes: a rectifier for producing a dc voltage power by rectifying clock signals; an oscillator including an odd number of invertors connected in series, and with the output of the last invertor fed back to the first invertor so as to oscillate clock pulses; and one or more bypass circuit connected so as for the output of the first invertor to bypass one or more intermediate invertors, and connected and disconnected by a control switch.
摘要翻译：一种用于半导体存储器件的电压发生器，适用于作为反向电压发生器，作为内部高压发生器或内部电力电压发生器。本发明包括：整流器，用于通过整流时钟信号产生直流电压电力; 包括串联连接的奇数个反相器的振荡器，并且将最后一个反相器的输出反馈到第一反相器以振荡时钟脉冲; 并且连接一个或多个旁路电路，以便使第一反相器的输出绕过一个或多个中间反相器，并由控制开关连接和断开。

2. 发明授权

US5905402A Voltage pump circuit having an independent well-bias voltage 失效
标题翻译：电压泵电路具有独立的良好偏置电压
公开(公告)号：US5905402A
公开(公告)日：1999-05-18
申请号：US866128
申请日：1997-05-30
申请人： Tae-Hoon Kim , Young-Hyun Jun
发明人： Tae-Hoon Kim , Young-Hyun Jun
IPC分类号： G11C11/407 , G11C5/14 , G11C11/408 , H01L21/8234 , H01L27/088 , H02M3/07 , G05F3/02
CPC分类号： H02M3/07
摘要： A voltage pump circuit for precharging/pumping a charge to/from a pumping capacitor separately employs a voltage generator for independently supplying a well-bias voltage to a PMOS transfer transistor which transfers a charge of a precharged capacitor to produce reference voltage. The voltage of the voltage generator is applied to a well of the PMOS transfer transistor to body bias the PMOS transfer transistor and, thus, ruggedize its threshold voltage transistor. Here, the well-bias voltage equals or exceeds the reference voltage while being approximately twice a power source voltage. The well-bias voltage generator includes a non-overlap control circuit for receiving a pulse signal as an input to generate two pulse signals having different points of changing into high and low states, a second pumping capacitor, first, second and third bootstrap capacitors, a precharge circuit for precharging the voltage on the second pumping capacitor and first and second bootstrap capacitors for a predetermined period, a first step control circuit for controlling a first-step transistor, a second step control circuit for controlling a second-step transistor and a pumping control circuit for controlling a third-step transistor, which are provided for precharging the voltage to the third bootstrap capacitor, and a transfer transistor having a gate connected to the reference voltage of the third bootstrap capacitor for transferring the well-bias voltage.
摘要翻译：用于向/从泵送电容器预充电/泵送电荷的电压泵电路分别采用电压发生器，用于独立向PMOS传输晶体管提供阱偏置电压，PMOS传输晶体管传送预充电电容器的电荷以产生参考电压。电压发生器的电压被施加到PMOS传输晶体管的阱以对PMOS传输晶体管进行偏置，并因此加强其阈值电压晶体管。这里，阱偏置电压等于或超过参考电压，而大约是电源电压的两倍。阱偏置电压发生器包括：不重叠控制电路，用于接收作为输入的脉冲信号，以产生具有变为高和低状态的不同点的两个脉冲信号;第二泵浦电容器，第一，第二和第三自举电容器; 预充电电路，用于对预定时间段内的第二泵浦电容器和第一和第二自举电容器进行预充电;第一级控制电路，用于控制第一级晶体管;第二级控制电路，用于控制第二级晶体管;以及泵控制电路，用于控制用于对第三自举电容器进行电压预充电的第三级晶体管;以及传输晶体管，其具有连接到第三自举电容器的参考电压的栅极，用于传送阱偏置电压。

3. 发明授权

US5602506A Back bias voltage generator 失效
标题翻译：背偏置电压发生器
公开(公告)号：US5602506A
公开(公告)日：1997-02-11
申请号：US362299
申请日：1994-12-22
申请人： Tae-Hoon Kim , Young-Hyun Jun
发明人： Tae-Hoon Kim , Young-Hyun Jun
IPC分类号： H01L27/04 , G11C5/14 , G11C11/408 , H01L21/822 , H02M3/07 , G05F1/10
CPC分类号： G11C5/146 , H02M3/07 , H01L2924/0002
摘要： A back bias voltage generator comprising a power-on signal generator for generating a power-on signal when an external voltage remains at a constant level, a reference voltage generator for generating a reference voltage in response to the power-on signal from the power-on signal generator, an internal voltage generator for generating an internal voltage and an internal/external voltage select signal in response to the reference voltage from the reference voltage generator, the internal voltage being constant in level, a back bias voltage sensor for generating an oscillation enable signal in response to the external voltage or the internal voltage from the internal voltage generator under control of the internal/external voltage select signal from the internal voltage generator, an oscillator for generating an oscillating signal at a desired period and an enable signal in response to the oscillation enable signal from the back bias voltage sensor and outputting the generated enable signal to the internal voltage generator, and a back bias voltage pump for performing a voltage pumping operation in response to the oscillating signal from the oscillator to generate a desired level of back bias voltage and outputting the generated back bias voltage to an external circuit and the back bias voltage sensor.
摘要翻译：背偏置电压发生器，其包括用于当外部电压保持在恒定电平时产生通电信号的上电信号发生器，用于响应于来自电源开关信号的电源接通信号产生参考电压的参考电压发生器，信号发生器，内部电压发生器，用于响应于来自参考电压发生器的参考电压产生内部电压和内部/外部电压选择信号，内部电压水平恒定;用于产生振荡的反向偏置电压传感器在来自内部电压发生器的内部/外部电压选择信号的控制下，响应于来自内部电压发生器的外部电压或内部电压的使能信号，用于在期望周期产生振荡信号的振荡器和响应中的使能信号到来自背偏压电压传感器的振荡使能信号，并输出所产生的使能信号内部电压发生器和反向偏置电压泵，用于响应于来自振荡器的振荡信号进行电压抽运操作，以产生期望电平的反向偏置电压，并将产生的反向偏置电压输出到外部电路，并且背偏置电压传感器。

4. 发明申请

US20110246857A1 MEMORY SYSTEM AND METHOD 审中-公开
标题翻译：记忆系统和方法
公开(公告)号：US20110246857A1
公开(公告)日：2011-10-06
申请号：US13078364
申请日：2011-04-01
申请人： Seung-Jun Bae , Kwang-Il Park , Young-Soo Sohn , Young-Hyun Jun , Joo-Sun Choi , Tae-Young Oh
发明人： Seung-Jun Bae , Kwang-Il Park , Young-Soo Sohn , Young-Hyun Jun , Joo-Sun Choi , Tae-Young Oh
IPC分类号： H03M13/09 , H03M13/05 , G06F11/10
CPC分类号： G06F11/1004 , H03M13/09
摘要： A memory system includes a memory controller and a memory device. The memory device exchanges data through a first channel with the memory controller, exchanges a first cyclic redundancy check (CRC) code associated with the data through a second channel with the memory controller, and receives a command/address packet including a second CRC code associated with a command/address from the memory controller through a third channel.
摘要翻译：存储器系统包括存储器控制器和存储器件。存储器件通过第一通道与存储器控制器交换数据，通过与存储器控制器的第二通道交换与数据相关联的第一循环冗余校验（CRC）代码，并且接收包括相关联的第二CRC码的命令/地址分组具有来自存储器控制器的命令/地址通过第三通道。

5. 发明授权

US07724073B2 Charge pump circuit 有权
标题翻译：电荷泵电路
公开(公告)号：US07724073B2
公开(公告)日：2010-05-25
申请号：US12287620
申请日：2008-10-10
申请人： Joung-Yeal Kim , Young-Hyun Jun , Bai-Sun Kong
发明人： Joung-Yeal Kim , Young-Hyun Jun , Bai-Sun Kong
IPC分类号： G05F3/02
CPC分类号： G11C5/145
摘要： A charge pump circuit includes initialization units, each of which initializes a boost node to an initialization voltage. Boosting units each boost the boost node to a higher voltage than the initialization voltage in response to an input voltage. First and second pump circuits each include a transfer unit for transferring a voltage of the boost node to an output node and sharing the output node. The transfer unit of the first pump circuit includes two transfer transistors that are switched in response to a voltage of a control node of the first pump circuit and the voltage of the boost node of the second pump circuit. The transfer unit of the second pump circuit includes two transfer transistors that are switched in response to a voltage of a control node of the second pump circuit and the voltage of the boost node of the first pump circuit.
摘要翻译：电荷泵电路包括初始化单元，每个初始化单元将升压节点初始化为初始化电压。升压单元各自将升压节点升压到比初始化电压高的电压以响应于输入电压。第一和第二泵电路各自包括用于将升压节点的电压传送到输出节点并共享输出节点的传送单元。第一泵电路的传送单元包括响应于第一泵电路的控制节点的电压和第二泵电路的升压节点的电压而被切换的两个传输晶体管。第二泵电路的传送单元包括响应于第二泵电路的控制节点的电压和第一泵电路的升压节点的电压而被切换的两个传输晶体管。

6. 发明申请

US20080122523A1 VOLTAGE GENERATION CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME 有权
标题翻译：电压发生电路和包括其的半导体存储器件
公开(公告)号：US20080122523A1
公开(公告)日：2008-05-29
申请号：US12025442
申请日：2008-02-04
申请人： Hyoung-Ryol Hwang , Young-Hyun Jun
发明人： Hyoung-Ryol Hwang , Young-Hyun Jun
IPC分类号： G05F3/02 , G05F3/16
CPC分类号： G11C5/14
摘要： A voltage generation circuit and semiconductor memory device including the same are provided. The voltage generation circuit includes: a voltage level detector, which detects a level of a first high voltage to generate a first high voltage level detection signal and detects a level of a second high voltage to generate a second high voltage level detection signal; a control signal generator, which generates at least four pumping control signals in sequence when the first high voltage level detection signal is active, generates a control signal when the first high voltage level detection signal is inactive, and generates a first one of the at least four pumping control signals in response to a level of a power supply voltage; and a voltage generator, which pumps a boost node in response to the at least four pumping control signals to generate the first high voltage and transmits charge from the boost node to a second high voltage generation terminal in response to the control signal to generate the second high voltage.
摘要翻译：提供了包括该电压产生电路和半导体存储器件的电压产生电路。电压产生电路包括：电压电平检测器，其检测第一高电平的电平以产生第一高电压电平检测信号，并检测第二高电平的电平以产生第二高电压电平检测信号; 控制信号发生器，当所述第一高电压电平检测信号有效时，依次产生至少四个泵送控制信号，当所述第一高电压电平检测信号无效时产生控制信号，并且产生至少四个泵送控制信号响应于电源电压的电平; 以及电压发生器，其响应于所述至少四个泵送控制信号泵送升压节点以产生所述第一高电压，并且响应于所述控制信号将电压从所述升压节点传输到第二高电压发生端子，以产生所述第二高电压高压。

7. 发明申请

US20050105315A1 Content addressable memory (CAM) capable of finding errors in a CAM cell array and a method thereof 失效
标题翻译：能够在CAM单元阵列中发现错误的内容可寻址存储器（CAM）及其方法
公开(公告)号：US20050105315A1
公开(公告)日：2005-05-19
申请号：US10973806
申请日：2004-10-26
申请人： Ho-Geun Shin , Young-Hyun Jun
发明人： Ho-Geun Shin , Young-Hyun Jun
IPC分类号： G11C15/00 , G11C29/08
CPC分类号： G11C29/08 , G11C15/00
摘要： A method of finding errors in a content addressable memory (CAM) and a CAM cell array, the CAM being capable of finding errors in the CAM cell array, is disclosed. The CAM includes the CAM cell array having a plurality of CAM cells and a match line state storing unit. The match line state storing unit is connected to a word line and a match line of the plurality of CAM cells and has a plurality of state cells in which a logic level of stored data is changed according to a logic level of the match line. Errors in the CAM cell array are found by reading data stored in the plurality of state cells. The data stored in the plurality of state cells are matched when there are no errors in the CAM cell array.
摘要翻译：公开了一种在内容可寻址存储器（CAM）和CAM单元阵列中发现错误的方法，CAM能够在CAM单元阵列中发现错误。 CAM包括具有多个CAM单元的CAM单元阵列和匹配线状态存储单元。匹配线状态存储单元连接到多个CAM单元的字线和匹配线，并且具有根据匹配线的逻辑电平改变存储数据的逻辑电平的多个状态单元。通过读取存储在多个状态单元中的数据来发现CAM单元阵列中的错误。当CAM单元阵列中没有错误时，存储在多个状态单元中的数据是匹配的。

8. 发明申请

US20050094448A1 Integrated circuit device with on-chip setup/hold measuring circuit 失效
标题翻译：具有片上建立/保持测量电路的集成电路器件
公开(公告)号：US20050094448A1
公开(公告)日：2005-05-05
申请号：US10972119
申请日：2004-10-21
申请人： Jong-Eon Lee , Young-Hyun Jun
发明人： Jong-Eon Lee , Young-Hyun Jun
IPC分类号： G11C7/00 , G11C29/50
CPC分类号： G11C29/50012 , G11C29/50
摘要： An integrated circuit device disclosed herein includes a test device and a setup and hold measuring circuit. The setup and hold measuring circuit generates a reference signal and a data signal in response to an external clock signal in a test mode of operation. The test device receives the data signal in response to a reference signal, and outputs the inputted data signal as a setup and hold determining circuit. One of the reference signal and the data signal is a multiphase signal synchronized with the external clock signal. The setup and hold measuring circuit detects whether the output of the test device indicates a valid value of the data signal, and generates the detected result to the external as a setup/hold timing margin through at least one pad.
摘要翻译：本文公开的集成电路装置包括测试装置和建立和保持测量电路。建立和保持测量电路在测试操作模式下响应外部时钟信号产生参考信号和数据信号。测试装置响应于参考信号接收数据信号，并输出输入的数据信号作为建立和保持确定电路。参考信号和数据信号之一是与外部时钟信号同步的多相信号。建立和保持测量电路检测测试装置的输出是否指示数据信号的有效值，并通过至少一个焊盘将检测结果作为建立/保持定时裕度产生到外部。

9. 发明授权

US06154079A Negative delay circuit operable in wide band frequency 有权
标题翻译：负延迟电路可在宽带频率下工作
公开(公告)号：US06154079A
公开(公告)日：2000-11-28
申请号：US177818
申请日：1998-10-23
申请人： Jae-Goo Lee , Young-Hyun Jun
发明人： Jae-Goo Lee , Young-Hyun Jun
IPC分类号： G06F1/10 , G11C7/22 , H03K5/13 , H03K5/14
CPC分类号： G11C7/222 , G06F1/10 , G11C7/22 , H03K5/131
摘要： A negative delay circuit (NDC) has an NDC array operated in a high frequency. The circuit varies a number of unit delay stages at an input stage of the NDC array according to a locking fail signal in a low frequency region. The NDC can carry out a negative delay operation in a wide band even when a number of the stages in the NDC array is small. The present invention decreases a size of a chip, and in addition, reduces an unnecessary current consumption by preventing a locking from re-occurring at a stage in a back portion because the NDC array has a delay value less than one clock.
摘要翻译：负延迟电路（NDC）具有以高频率操作的NDC阵列。该电路根据低频区域中的锁定失败信号，在NDC阵列的输入级上改变多个单位延迟级。 NDC可以在宽频带中进行负延迟操作，即使在NDC阵列中的多个级数较小时也是如此。本发明减小了芯片的尺寸，并且由于NDC阵列具有小于一个时钟的延迟值，因此通过防止在后部的一个阶段中的锁定再次发生而减少不必要的电流消耗。

10. 发明授权

US5966337A Method for overdriving bit line sense amplifier 失效
标题翻译：驱动位线读出放大器的方法
公开(公告)号：US5966337A
公开(公告)日：1999-10-12
申请号：US958932
申请日：1997-10-28
申请人： Jae-Goo Lee , Young-Hyun Jun
发明人： Jae-Goo Lee , Young-Hyun Jun
IPC分类号： G11C11/409 , G11C7/06 , G11C11/413 , G11C7/00
CPC分类号： G11C7/065
摘要： A bit line sense amplifier overdriving method includes a step for reaching a bit line data signal to a full swing level by driving the sense amplifiers in accordance with an overdriving voltage in an overdriving pulse interval, when an overdriving pulse signal is generated at points in which the sense amplifiers are enabled and disabled in a data read operation and a data write operation. The method maintains a sufficiently long refresh interval during a refresh operation.
摘要翻译：位线检测放大器过驱动方法包括通过在过驱动脉冲间隔中根据过驱动电压驱动读出放大器来将位线数据信号达到全摆幅电平的步骤，当在其中产生过驱动脉冲信号时，在数据读取操作和数据写入操作中启用和禁用读出放大器。该方法在刷新操作期间保持足够长的刷新间隔。

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