专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07778094B2 Semiconductor memory device and latency signal generating method thereof 有权
标题翻译：半导体存储器件及其等待时间信号产生方法
公开(公告)号：US07778094B2
公开(公告)日：2010-08-17
申请号：US12219816
申请日：2008-07-29
申请人： Kwang-II Park , Young-Hyun Jun , Seong-Jin Jang , Ho-Young Song
发明人： Kwang-II Park , Young-Hyun Jun , Seong-Jin Jang , Ho-Young Song
IPC分类号： G11C7/00
CPC分类号： G11C7/1051 , G11C7/1066 , G11C7/1072
摘要： A latency signal generating method and a corresponding semiconductor memory device, among other things, are disclosed. Such a method includes: receiving a clock signal for the semiconductor memory device; receiving a mode characterization signal; providing the DQS; and adapting the duration of a preamble state of the DQS according to the mode characterization signal to promote conformance of a strobe state of the DQS with the clock signal.
摘要翻译：公开了等待信号产生方法和相应的半导体存储器件。这种方法包括：接收半导体存储器件的时钟信号; 接收模式表征信号; 提供DQS; 以及根据模式表征信号调整DQS的前导码状态的持续时间，以促进DQS的选通状态与时钟信号的一致性。

2. 发明申请

US20100271886A1 Semiconductor memory device and latency signal generating method thereof 审中-公开
公开(公告)号：US20100271886A1
公开(公告)日：2010-10-28
申请号：US12801953
申请日：2010-07-02
申请人： Kwang-II Park , Young-Hyun Jun , Seong-Jin Jang , Ho-Young Song
发明人： Kwang-II Park , Young-Hyun Jun , Seong-Jin Jang , Ho-Young Song
IPC分类号： G11C7/00
CPC分类号： G11C7/1051 , G11C7/1066 , G11C7/1072
摘要： A latency signal generating method and a corresponding semiconductor memory device, among other things, are disclosed. Such a method includes: receiving a clock signal for the semiconductor memory device; receiving a mode characterization signal; providing the DQS; and adapting the duration of a preamble state of the DQS according to the mode characterization signal to promote conformance of a strobe state of the DQS with the clock signal.

3. 发明申请

US20060250861A1 Semiconductor memory device and latency signal generating method thereof 有权
标题翻译：半导体存储器件及其等待时间信号产生方法
公开(公告)号：US20060250861A1
公开(公告)日：2006-11-09
申请号：US11416077
申请日：2006-05-03
申请人： Kwang-II Park , Young-Hyun Jun , Seong-Jin Jang , Ho-Young Song
发明人： Kwang-II Park , Young-Hyun Jun , Seong-Jin Jang , Ho-Young Song
IPC分类号： G11C7/00
CPC分类号： G11C7/1051 , G11C7/1066 , G11C7/1072
摘要： A latency signal generating method and a corresponding semiconductor memory device, among other things, are disclosed. Such a method includes: receiving a clock signal for the semiconductor memory device; receiving a mode characterization signal; providing the DQS; and adapting the duration of a preamble state of the DQS according to the mode characterization signal to promote conformance of a strobe state of the DQS with the clock signal.
摘要翻译：公开了等待信号产生方法和相应的半导体存储器件。这种方法包括：接收半导体存储器件的时钟信号; 接收模式表征信号; 提供DQS; 以及根据模式表征信号调整DQS的前导码状态的持续时间，以促进DQS的选通状态与时钟信号的一致性。

4. 发明申请

US20100284231A1 Memory system, memory device, and output data strobe signal generating method 失效
公开(公告)号：US20100284231A1
公开(公告)日：2010-11-11
申请号：US12662720
申请日：2010-04-29
申请人： Kwang-II Park , Seong-Jin Jang , Ho-Young Song
发明人： Kwang-II Park , Seong-Jin Jang , Ho-Young Song
IPC分类号： G11C7/00
CPC分类号： G11C7/1051 , G11C7/1066 , G11C2207/2254
摘要： An output data strobe signal generating method and a memory system that includes a plurality of semiconductor memory devices, and a memory controller for controlling the semiconductor memory devices, wherein the memory controller provides a command signal and a chip selecting signal to the semiconductor memory devices. One or more of the semiconductor memory devices may detect a read command and a dummy read command in response to the command signal and the chip selecting signal and generate one or more preamble signals based on a calculated preamble cycle number.

5. 发明申请

US20070206428A1 HIGH-SPEED PHASE-ADJUSTED QUADRATURE DATA RATE (QDR) TRANSCEIVER AND METHOD THEREOF 有权
标题翻译：高速相位调整数据速率（QDR）收发器及其方法
公开(公告)号：US20070206428A1
公开(公告)日：2007-09-06
申请号：US11612800
申请日：2006-12-19
申请人： Seung-Jun Bae , Seong-Jin Jang , Kwang-II Park , Sang-Woong Shin , Ho-Young Song
发明人： Seung-Jun Bae , Seong-Jin Jang , Kwang-II Park , Sang-Woong Shin , Ho-Young Song
IPC分类号： G11C7/00
CPC分类号： G11C7/22 , G11C7/1051 , G11C7/1066 , G11C7/1078 , G11C7/1093 , G11C7/222 , G11C11/4076 , G11C11/4093 , G11C11/4096
摘要： A high-speed double or quadrature data rate interface semiconductor device and a method thereof are provided. A transmitter (e.g., a data transmitting semiconductor device) for high-speed data transmission transmits a first strobe signal and a second strobe signal, which have a phase difference of 90 degrees there-between, a first group (byte of) data, and a second group (byte of) data. The transmitter adjusts the phase of at least one of the first and second strobe signals based on phase-error information fed back from a receiver and then transmits the phase-adjusted strobe signal to the receiver. The receiver receives the first and second strobe signals from the transmitter and receives the first group (byte of) data and the second group (byte of) data using the first and second strobe signals. The receiver does not require a phase-locked loop (PLL) or a delay-locked loop (DLL), thereby decreasing the circuit area and power consumption of the receiver. In addition, since source synchronization is realized using a strobe signal, phase noise can be efficiently removed.
摘要翻译：提供了一种高速双倍或正交数据速率接口半导体器件及其方法。用于高速数据传输的发射机（例如，数据传输半导体器件）发送第一选通信号和第二选通信号，第一选通信号和第二选通信号之间具有90度的相位差，第一组（字节）数据和第二组（字节）数据。发射机基于从接收机反馈的相位误差信息来调节第一和第二选通信号中的至少一个的相位，然后将相位调整的选通信号发送到接收机。接收机从发送器接收第一和第二选通信号，并使用第一和第二选通信号接收数据的第一组（字节）和第二组（字节）数据。接收机不需要锁相环（PLL）或延迟锁定环（DLL），从而减少接收机的电路面积和功耗。此外，由于使用选通信号实现源同步，因此可以有效地去除相位噪声。

6. 发明授权

US07205799B2 Input buffer having a stabilized operating point and an associated method 失效
标题翻译：输入缓冲器具有稳定的工作点和相关联的方法
公开(公告)号：US07205799B2
公开(公告)日：2007-04-17
申请号：US11225915
申请日：2005-09-13
申请人： Hyun-Jin Kim , Seong-Jin Jang , Kwang-II Park , Sang-Joon Hwang , Ho-Young Song , Ho-Kyong Lee , Woo-Jin Lee
发明人： Hyun-Jin Kim , Seong-Jin Jang , Kwang-II Park , Sang-Joon Hwang , Ho-Young Song , Ho-Kyong Lee , Woo-Jin Lee
IPC分类号： H03K3/00
CPC分类号： H03F3/45
摘要： We describe an input buffer having a stabilized operating point and an associated method. An input buffer may include a first differential amplifying unit to generate a first output signal having a first operating point and a second differential amplifying unit to generate a second output signal having a second operating point. An output control circuit varies respective weights of the first and second output signals responsive to an output control signal. The first differential amplifying unit may operate responsive to a reference voltage and an input voltage signal. The second differential amplifying unit may operate responsive to the reference voltage and the input voltage signal. The first operating point may be relatively higher than the second operating point.
摘要翻译：我们描述具有稳定的工作点和相关方法的输入缓冲器。输入缓冲器可以包括第一差分放大单元，用于产生具有第一工作点的第一输出信号和第二差分放大单元，以产生具有第二工作点的第二输出信号。响应于输出控制信号，输出控制电路改变第一和第二输出信号的各个权重。第一差分放大单元可以响应于参考电压和输入电压信号而进行操作。第二差分放大单元可以响应于参考电压和输入电压信号而工作。第一工作点可以相对高于第二工作点。

7. 发明申请

US20080291753A1 Semiconductor memory device and latency signal generating method thereof 有权
标题翻译：半导体存储器件及其等待时间信号产生方法
公开(公告)号：US20080291753A1
公开(公告)日：2008-11-27
申请号：US12219816
申请日：2008-07-29
申请人： Kwang-Il Park , Young-Hyun Jun , Seong-Jin Jang , Ho-Young Song
发明人： Kwang-Il Park , Young-Hyun Jun , Seong-Jin Jang , Ho-Young Song
IPC分类号： G11C7/00 , G11C8/18
CPC分类号： G11C7/1051 , G11C7/1066 , G11C7/1072
摘要： A latency signal generating method and a corresponding semiconductor memory device, among other things, are disclosed. Such a method includes: receiving a clock signal for the semiconductor memory device; receiving a mode characterization signal; providing the DQS; and adapting the duration of a preamble state of the DQS according to the mode characterization signal to promote conformance of a strobe state of the DQS with the clock signal.
摘要翻译：公开了等待信号产生方法和相应的半导体存储器件。这种方法包括：接收半导体存储器件的时钟信号; 接收模式表征信号; 提供DQS; 以及根据模式表征信号调整DQS的前导码状态的持续时间，以促进DQS的选通状态与时钟信号的一致性。

8. 发明授权

US07453745B2 Semiconductor memory device and latency signal generating method thereof 有权
公开(公告)号：US07453745B2
公开(公告)日：2008-11-18
申请号：US11416077
申请日：2006-05-03
申请人： Kwang-Il Park , Young-Hyun Jun , Seong-Jin Jang , Ho-Young Song
发明人： Kwang-Il Park , Young-Hyun Jun , Seong-Jin Jang , Ho-Young Song
IPC分类号： G11C7/00
CPC分类号： G11C7/1051 , G11C7/1066 , G11C7/1072
摘要： A latency signal generating method and a corresponding semiconductor memory device, among other things, are disclosed. Such a method includes: receiving a clock signal for the semiconductor memory device; receiving a mode characterization signal; providing the DQS; and adapting the duration of a preamble state of the DQS according to the mode characterization signal to promote conformance of a strobe state of the DQS with the clock signal.

9. 发明申请

US20100091600A1 CIRCUIT AND METHOD FOR SAMPLING VALID COMMAND USING EXTENDED VALID ADDRESS WINDOW IN DOUBLE PUMPED ADDRESS SCHEME MEMORY DEVICE 审中-公开
标题翻译：在双重抽取地址方案存储器件中使用扩展有效地址窗口采样有效命令的电路和方法
公开(公告)号：US20100091600A1
公开(公告)日：2010-04-15
申请号：US12635785
申请日：2009-12-11
申请人： Hyun-Jin Kim , Seong-Jin Jang , Jeong-Don Lim , Kwang-Il Park , Ho-Young Song , Woo-Jin Lee
发明人： Hyun-Jin Kim , Seong-Jin Jang , Jeong-Don Lim , Kwang-Il Park , Ho-Young Song , Woo-Jin Lee
IPC分类号： G11C8/00 , G11C8/18
CPC分类号： G06F12/02 , G11C7/1078 , G11C7/109
摘要： Provided are a circuit and method for sampling a valid command using a valid address window extended for a high-speed operation in a double pumped address scheme memory device. A method for extending the valid address window includes: inputting a valid command signal and a first address signal at the first cycle of a clock signal; inputting a second address signal at the second cycle of the clock signal; generating a decoded command signal and extended first and second internal address signals respectively in response to the command signal and the address signals; and latching and decoding the extended first and second internal address signals in response to the decoded command signal.
摘要翻译：提供了一种用于在双抽取地址方案存储器件中使用扩展用于高速操作的有效地址窗口来对有效命令进行采样的电路和方法。扩展有效地址窗口的方法包括：在时钟信号的第一周期输入有效的命令信号和第一地址信号; 在时钟信号的第二周期输入第二地址信号; 响应于命令信号和地址信号分别产生解码的命令信号和扩展的第一和第二内部地址信号; 以及响应于解码的命令信号来锁存和解码扩展的第一和第二内部地址信号。

10. 发明申请

US20060062286A1 Data training in memory device 审中-公开
标题翻译：存储设备中的数据训练
公开(公告)号：US20060062286A1
公开(公告)日：2006-03-23
申请号：US11128795
申请日：2005-05-13
申请人： Kwang-Il Park , Seong-Jin Jang , Ho-Young Song
发明人： Kwang-Il Park , Seong-Jin Jang , Ho-Young Song
IPC分类号： H04B1/38
CPC分类号： G11C7/1072 , G11C29/50 , G11C29/50012 , G11C2207/2254
摘要： For data training in a memory device, a selecting unit selects a subset of data bit patterns received from a controlling device. In addition, a storing unit comprised of memory cells of the memory device stores the selected subset of data bit patterns. Such stored data bit patterns are then sent back to the controlling device that determines the level of data skew. Such data training more accurately reflects the actual paths and environments of the transmitted data bits.
摘要翻译：对于存储器件中的数据训练，选择单元选择从控制装置接收的数据位模式的子集。此外，由存储器件的存储器单元组成的存储单元存储所选择的数据位模式子集。然后将这种存储的数据位模式发送回确定数据偏移水平的控制设备。这种数据训练更准确地反映了传输数据位的实际路径和环境。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式