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11. 发明申请

US20110320881A1 ISOLATION OF FAULTY LINKS IN A TRANSMISSION MEDIUM 有权
标题翻译：在传输介质中分离故障链路
公开(公告)号：US20110320881A1
公开(公告)日：2011-12-29
申请号：US12822508
申请日：2010-06-24
申请人： John S. Dodson , Frank D. Ferraiolo , Michele M. Franceschini , Kevin C. Gower , Lisa C. Gower , Ashish Jagmohan , Luis A. Lastras-Montano , Kenneth L. Wright
发明人： John S. Dodson , Frank D. Ferraiolo , Michele M. Franceschini , Kevin C. Gower , Lisa C. Gower , Ashish Jagmohan , Luis A. Lastras-Montano , Kenneth L. Wright
IPC分类号： G06F11/34
CPC分类号： G06F11/10 , G06F11/2005 , H04L1/0061 , H04L2001/0096
摘要： Isolation of faulty links in a transmission medium including a method that includes receiving an atomic data unit via a multi-link transmission medium that has a plurality of transmission links An error condition is detected and it is determined that the error condition is isolated to a single transmission link. It is determined if the single transmission link has been isolated previously as a failing transmission link a specified number of times within an interval specified by a timer. If the single transmission link has been isolated previously as a failing transmission link a specified number of times within an interval specified by a timer then: identifying the single transmission link as a faulty transmission link; resetting the timer; and outputting an identifier of the single transmission link.
摘要翻译：隔离传输介质中的故障链路，包括包括通过具有多个传输链路的多链路传输介质接收原子数据单元的方法检测到错误状况，并且确定错误状况被隔离为单个传输链路。在由定时器指定的间隔内，确定单个传输链路是否已经被隔离为先前被隔离的传输链路指定的次数。如果单个传输链路在由定时器指定的间隔内已经被隔离为失败的传输链路指定的次数，则：将单个传输链路识别为有故障的传输链路; 重置定时器; 并输出单个传输链路的标识符。

12. 发明申请

US20110252215A1 COMPUTER MEMORY WITH DYNAMIC CELL DENSITY 审中-公开
标题翻译：具有动态细胞密度的计算机存储器
公开(公告)号：US20110252215A1
公开(公告)日：2011-10-13
申请号：US12757738
申请日：2010-04-09
申请人： Michele M. Franceschini , John P. Karidis , Luis A. Lastras-Montano , Moinuddin Qureshi
发明人： Michele M. Franceschini , John P. Karidis , Luis A. Lastras-Montano , Moinuddin Qureshi
IPC分类号： G06F12/02
CPC分类号： G11C11/5628 , G06F12/0238 , G11C11/5678 , G11C13/0004 , G11C2211/5641 , Y02D10/13
摘要： A computer memory with dynamic cell density including a method that obtains a target size for a first memory region. The first memory region includes first memory units operating at a first density. The first memory units are includes in a memory in a memory system. The memory is operable at the first density and a second density. The method also includes: determining that a current size of the first memory region is not within a threshold of the target size and that the first memory region is smaller than the target size; identifying a second memory unit currently operating at the second density in a second memory region, the second memory unit included in the memory; and dynamically reassigning, during normal system operation, the second memory unit into the first memory region, the second memory unit operating at the first density after being reassigned to the first memory region.
摘要翻译：一种具有动态单元密度的计算机存储器，包括获得第一存储器区域的目标尺寸的方法。第一存储器区域包括以第一密度操作的第一存储器单元。第一存储器单元包括在存储器系统的存储器中。存储器可在第一密度和第二密度下操作。所述方法还包括：确定所述第一存储器区域的当前大小不在所述目标大小的阈值内，并且所述第一存储器区域小于所述目标大小; 识别当前在第二存储器区域以第二密度操作的第二存储器单元，所述第二存储器单元包括在存储器中; 以及在正常系统操作期间将所述第二存储器单元动态地重新分配到所述第一存储器区域中，所述第二存储器单元在被重新分配给所述第一存储器区域之后以所述第一密度操作。

13. 发明授权

US08024642B2 System and method for providing constrained transmission and storage in a random access memory 失效
标题翻译：用于在随机存取存储器中提供约束传输和存储的系统和方法
公开(公告)号：US08024642B2
公开(公告)日：2011-09-20
申请号：US11846814
申请日：2007-08-29
申请人： Luis A. Lastras-Montano
发明人： Luis A. Lastras-Montano
IPC分类号： G11C29/00
CPC分类号： G06F13/4243 , Y02D10/14 , Y02D10/151
摘要： A system and method for providing constrained transmission and storage in a random access memory. A system includes a memory device for providing constrained transmission and storage. The memory device includes an interface to a data bus, the data bus having a previous state. The memory device also includes an interface to an address and command bus for receiving a request to read data at an address, and a mechanism for initiating a programmable mode. The programmable mode facilitates retrieving data at the address, and executing an exclusive or (XOR) using the retrieved data and the previous state of the data bus as input. The result of the XOR operation is transmitted to the requester via the data bus.
摘要翻译：一种在随机存取存储器中提供约束传输和存储的系统和方法。系统包括用于提供有限传输和存储的存储器件。存储器件包括与数据总线的接口，数据总线具有先前的状态。存储装置还包括到地址和命令总线的接口，用于接收在地址处读取数据的请求，以及用于启动可编程模式的机制。可编程模式便于在地址处检索数据，并使用检索到的数据和数据总线的先前状态作为输入执行异或（XOR）。 XOR操作的结果通过数据总线传送到请求者。

14. 发明授权

US08023345B2 Iteratively writing contents to memory locations using a statistical model 有权
标题翻译：使用统计模型迭代地将内容写入内存位置
公开(公告)号：US08023345B2
公开(公告)日：2011-09-20
申请号：US12391693
申请日：2009-02-24
申请人： Matthew J. Breitwisch , Roger W. Cheek , Stefanie R. Chiras , Ibrahim M. Elfadel , Michele M. Franceschini , John P. Karidis , Luis A. Lastras-Montano , Thomas Mittelholzer , Mayank Sharma
发明人： Matthew J. Breitwisch , Roger W. Cheek , Stefanie R. Chiras , Ibrahim M. Elfadel , Michele M. Franceschini , John P. Karidis , Luis A. Lastras-Montano , Thomas Mittelholzer , Mayank Sharma
IPC分类号： G11C29/00 , G11C7/00
CPC分类号： G11C29/02 , G11C13/0004 , G11C13/0064 , G11C13/0069 , G11C29/021 , G11C29/028 , G11C2013/0092
摘要： Systems, methods, and devices for iteratively writing contents to memory locations are provided. A statistical model is used to determine a sequence of pulses to write desired contents to a memory location. The contents can be expressed as a resistance value in a range to store one or more bits in a memory cell. For phase change memory, an adaptive reset pulse and one or more annealing pulses are selected based on a desired resistance range. Reading the resistance value of the memory cell can provide feedback to determine adjustments in an overall pulse application strategy. The statistical model and a look up table can be used to select and modify pulses. Adaptively updating the statistical model and look up table may reduce the number of looping iterations to shift the resistance value of the memory cell into the desired resistance range.
摘要翻译：提供了用于向内存位置迭代地写入内容的系统，方法和设备。统计模型用于确定将所需内容写入存储器位置的脉冲序列。内容可以表示为在存储单元中存储一个或多个位的范围内的电阻值。对于相变存储器，基于期望的电阻范围来选择自适应复位脉冲和一个或多个退火脉冲。读取存储器单元的电阻值可提供反馈以确定整体脉冲应用策略中的调整。统计模型和查询表可用于选择和修改脉冲。自适应地更新统计模型和查找表可以减少循环迭代的次数以将存储器单元的电阻值移动到期望的电阻范围。

15. 发明授权

US07984329B2 System and method for providing DRAM device-level repair via address remappings external to the device 有权
标题翻译：通过设备外部的地址重映射提供DRAM设备级修复的系统和方法
公开(公告)号：US07984329B2
公开(公告)日：2011-07-19
申请号：US11849452
申请日：2007-09-04
申请人： Luis A. Lastras-Montano , Darren L. Anand , Jeffrey H. Dreibelbis , Charles A. Kilmer , Warren E. Maule , Robert B. Tremaine
发明人： Luis A. Lastras-Montano , Darren L. Anand , Jeffrey H. Dreibelbis , Charles A. Kilmer , Warren E. Maule , Robert B. Tremaine
IPC分类号： G06F11/00
CPC分类号： G11C29/76 , G11C11/401
摘要： A system and method for providing DRAM device-level repair via address remappings external to the device. A system includes a memory controller having an interface to one or more memory devices via a memory module. The memory devices include addressable redundant and non-redundant memory blocks. The memory controller also includes a mechanism for utilizing one or more redundant memory blocks in place of one or more failing non-redundant memory blocks via an address remapping external to the memory device. The remapping occurs while the system is on-line.
摘要翻译：一种用于通过设备外部的地址重映射提供DRAM设备级修复的系统和方法。系统包括存储器控制器，其经由存储器模块具有到一个或多个存储器设备的接口。存储器件包括可寻址冗余和非冗余存储器块。存储器控制器还包括一种机构，用于经由存储器件外部的地址重新映射来代替一个或多个故障非冗余存储器块来利用一个或多个冗余存储器块。重新映射发生在系统在线时。

16. 发明申请

US20110138104A1 MULTI-WRITE CODING OF NON-VOLATILE MEMORIES 有权
标题翻译：非易失性存储器的多写编码
公开(公告)号：US20110138104A1
公开(公告)日：2011-06-09
申请号：US12631470
申请日：2009-12-04
申请人： Michele M. Franceschini , Ashish Jagmohan , Luis A. Lastras-Montano
发明人： Michele M. Franceschini , Ashish Jagmohan , Luis A. Lastras-Montano
IPC分类号： G06F12/00 , G06F12/02
CPC分类号： G06F12/0246 , G06F2212/401 , G11C11/5621 , G11C16/3418 , G11C16/349
摘要： Multi-write coding of non-volatile memories including a method that receives write data, and a write address of a memory page. The memory page is in either an erased state or a previously written state. If the memory page is in the erased state: selecting a first codeword from a code such that the first codeword encodes the write data and is consistent with a target set of distributions of electrical charge levels in the memory page; and writing the first codeword to the memory page. If the memory page is in the previously written state: selecting a coset from a linear code such that the coset encodes the write data and includes one or more words that are consistent with previously written content of the memory page; selecting a subsequent codeword from the one or more words in the coset; and writing the subsequent codeword to the memory page.
摘要翻译：包括接收写入数据的方法的非易失性存储器的多写入编码以及存储器页面的写入地址。存储器页面处于擦除状态或先前写入的状态。如果存储器页面处于擦除状态：从代码中选择第一码字，使得第一码字对写入数据进行编码，并与存储器页面中的电荷电平分布的目标集合一致; 以及将所述第一码字写入所述存储器页。如果存储器页面处于先前写入的状态：从线性代码选择陪集，使得陪集对编写数据进行编码并且包括与存储器页面的先前写入的内容一致的一个或多个单词; 从陪集中的一个或多个单词中选择随后的码字; 以及将所述后续码字写入所述存储器页面。

17. 发明申请

US20110134676A1 RESISTIVE MEMORY DEVICES HAVING A NOT-AND (NAND) STRUCTURE 有权
标题翻译：具有非和（非）结构的电阻式存储器件
公开(公告)号：US20110134676A1
公开(公告)日：2011-06-09
申请号：US12631310
申请日：2009-12-04
申请人： Matthew J. Breitwisch , Gary S. Ditlow , Michele M. Franceschini , Luis A. Lastras-Montano , Robert K. Montoye , Bipin Rajendran
发明人： Matthew J. Breitwisch , Gary S. Ditlow , Michele M. Franceschini , Luis A. Lastras-Montano , Robert K. Montoye , Bipin Rajendran
IPC分类号： G11C15/00 , G11C11/00 , G11C7/00
CPC分类号： G11C15/046 , G11C13/0004 , G11C13/003 , G11C13/0069 , G11C16/0483 , G11C2013/0088 , G11C2013/0092 , G11C2213/75
摘要： Resistive memories having a not-and (NAND) structure including a resistive memory cell. The resistive memory cell includes a resistive memory element for storing a resistance value and a memory element access device for controlling access to the resistive memory element. The memory element access device is connected in parallel to the resistive memory element.
摘要翻译：具有包括电阻存储单元的非 - 和（NAND）结构的电阻存储器。电阻性存储单元包括用于存储电阻值的电阻性存储器元件和用于控制对电阻式存储器元件的访问的存储元件访问器件。存储元件存取装置与电阻式存储元件并联连接。

18. 发明授权

US07895502B2 Error control coding methods for memories with subline accesses 失效
标题翻译：具有子线路访问的存储器的错误控制编码方法
公开(公告)号：US07895502B2
公开(公告)日：2011-02-22
申请号：US11619929
申请日：2007-01-04
申请人： Junsheng Han , Luis A. Lastras-Montano , Michael R. Trombley
发明人： Junsheng Han , Luis A. Lastras-Montano , Michael R. Trombley
IPC分类号： G11C29/00
CPC分类号： G06F11/1012
摘要： A two-level error control protocol detects errors on the subline level and corrects errors using the codeword for the entire line. This enables a system to read small pieces of coded data and check for errors before accepting them, and in case errors are detected, the whole codeword is read for error correction.
摘要翻译：两级错误控制协议检测子线路上的错误，并使用整个行的代码字纠正错误。这使得系统能够读取小块编码数据并在接受编码数据之前检查错误，并且在检测到错误的情况下，读取整个码字用于纠错。

19. 发明申请

US20100293438A1 System to Improve Error Correction Using Variable Latency and Associated Methods 有权
标题翻译：使用变量延迟和相关方法改进误差校正的系统
公开(公告)号：US20100293438A1
公开(公告)日：2010-11-18
申请号：US12023546
申请日：2008-01-31
申请人： Luis A. Lastras-Montano , Piyush C. Patel , Eric E. Retter , Barry M. Trager , Michael R. Trombley , Shmuel Winograd , Kenneth L. Wright
发明人： Luis A. Lastras-Montano , Piyush C. Patel , Eric E. Retter , Barry M. Trager , Michael R. Trombley , Shmuel Winograd , Kenneth L. Wright
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： G06F11/1048
摘要： A system to improve error correction may include a fast decoder to process data packets until the fast decoder finds an uncorrectable error in a data packet at which point a request for at least two data packets is generated. The system may also include a slow decoder to possibly correct the uncorrectable error in a data packet based upon the at least two data packets.
摘要翻译：用于改进纠错的系统可以包括处理数据分组的快速解码器，直到快速解码器在数据分组中发现对于至少两个数据分组的请求产生的不可校正的错误。该系统还可以包括慢解码器，以可能地基于至少两个数据分组校正数据分组中的不可校正错误。

20. 发明申请

US20100293436A1 System for Error Control Coding for Memories of Different Types and Associated Methods 有权
标题翻译：用于不同类型和相关方法的记忆的错误控制编码系统
公开(公告)号：US20100293436A1
公开(公告)日：2010-11-18
申请号：US12023408
申请日：2008-01-31
申请人： Paul W. Coteus , Luis A. Lastras-Montano , Warren Edward Maule , Barry M. Trager , Shmuel Winograd
发明人： Paul W. Coteus , Luis A. Lastras-Montano , Warren Edward Maule , Barry M. Trager , Shmuel Winograd
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： H03M13/1545 , G06F11/1048 , H03M13/1515 , H03M13/154 , H03M13/35 , H03M13/353 , H03M13/3707 , H03M13/6511 , H03M13/6516
摘要： A system to improve error control coding may include memory chips of at least two different kinds. The system may also include error control encoder circuitry to substantially encode data for storage in any memory rank. The system may further include error control decoder circuitry to substantially decode encoded data received from any memory rank. The error decoder circuitry is comprised of a slow decoder and a fast decoder.
摘要翻译：改进误差控制编码的系统可以包括至少两种不同种类的存储器芯片。该系统还可以包括错误控制编码器电路，用于基本上编码数据以存储在任何存储器等级中。系统还可以包括错误控制解码器电路，以基本上解码从任何存储器级接收的编码数据。错误解码器电路由慢解码器和快速解码器组成。

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