专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20100293436A1 System for Error Control Coding for Memories of Different Types and Associated Methods 有权
标题翻译：用于不同类型和相关方法的记忆的错误控制编码系统
公开(公告)号：US20100293436A1
公开(公告)日：2010-11-18
申请号：US12023408
申请日：2008-01-31
申请人： Paul W. Coteus , Luis A. Lastras-Montano , Warren Edward Maule , Barry M. Trager , Shmuel Winograd
发明人： Paul W. Coteus , Luis A. Lastras-Montano , Warren Edward Maule , Barry M. Trager , Shmuel Winograd
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： H03M13/1545 , G06F11/1048 , H03M13/1515 , H03M13/154 , H03M13/35 , H03M13/353 , H03M13/3707 , H03M13/6511 , H03M13/6516
摘要： A system to improve error control coding may include memory chips of at least two different kinds. The system may also include error control encoder circuitry to substantially encode data for storage in any memory rank. The system may further include error control decoder circuitry to substantially decode encoded data received from any memory rank. The error decoder circuitry is comprised of a slow decoder and a fast decoder.
摘要翻译：改进误差控制编码的系统可以包括至少两种不同种类的存储器芯片。该系统还可以包括错误控制编码器电路，用于基本上编码数据以存储在任何存储器等级中。系统还可以包括错误控制解码器电路，以基本上解码从任何存储器级接收的编码数据。错误解码器电路由慢解码器和快速解码器组成。

2. 发明授权

US08185800B2 System for error control coding for memories of different types and associated methods 有权
标题翻译：用于不同类型和相关方法的存储器的错误控制编码系统
公开(公告)号：US08185800B2
公开(公告)日：2012-05-22
申请号：US12023408
申请日：2008-01-31
申请人： Paul W. Coteus , Luis A. Lastras-Montano , Warren Edward Maule , Barry M. Trager , Shmuel Winograd
发明人： Paul W. Coteus , Luis A. Lastras-Montano , Warren Edward Maule , Barry M. Trager , Shmuel Winograd
IPC分类号： G11C29/00
CPC分类号： H03M13/1545 , G06F11/1048 , H03M13/1515 , H03M13/154 , H03M13/35 , H03M13/353 , H03M13/3707 , H03M13/6511 , H03M13/6516
摘要： A system to improve error control coding. An example system includes memory chips of at least two different kinds. The system also includes error control encoder circuitry to substantially encode data for storage in any memory rank. The system further includes error control decoder circuitry to substantially decode encoded data received from any memory rank. The error decoder circuitry is comprised of a slow decoder and a fast decoder.
摘要翻译：一种改进错误控制编码的系统。示例系统包括至少两种不同类型的存储器芯片。该系统还包括错误控制编码器电路，用于基本上编码数据以存储在任何存储器级中。该系统还包括错误控制解码器电路，以基本上解码从任何存储器等级接收的编码数据。错误解码器电路由慢解码器和快速解码器组成。

3. 发明授权

US08185801B2 System to improve error code decoding using historical information and associated methods 有权
标题翻译：系统使用历史信息和相关方法改进错误码解码
公开(公告)号：US08185801B2
公开(公告)日：2012-05-22
申请号：US12023445
申请日：2008-01-31
申请人： Timothy J. Dell , Luis A. Lastras-Montano , Barry M. Trager , Shmuel Winograd
发明人： Timothy J. Dell , Luis A. Lastras-Montano , Barry M. Trager , Shmuel Winograd
IPC分类号： H03M13/00
CPC分类号： G06F11/1044
摘要： A system to improve error code decoding using historical information. An example system includes storage partitioned into memory ranks, and a table to record symbols having failures for each memory rank. The system generates a memory rank score for each memory rank. The system also includes an error control decoder that uses the memory rank score when each memory rank is accessed in order to determine whether an error should be corrected or not.
摘要翻译：一种使用历史信息改进错误代码解码的系统。示例性系统包括分割成存储器排名的存储器，以及用于记录具有每个存储器级别的故障的符号的表。系统为每个存储器级别生成内存等级分数。该系统还包括错误控制解码器，当访问每个存储器等级时，使用存储器等级分数，以便确定是否应该纠正错误。

4. 发明申请

US20100293438A1 System to Improve Error Correction Using Variable Latency and Associated Methods 有权
标题翻译：使用变量延迟和相关方法改进误差校正的系统
公开(公告)号：US20100293438A1
公开(公告)日：2010-11-18
申请号：US12023546
申请日：2008-01-31
申请人： Luis A. Lastras-Montano , Piyush C. Patel , Eric E. Retter , Barry M. Trager , Michael R. Trombley , Shmuel Winograd , Kenneth L. Wright
发明人： Luis A. Lastras-Montano , Piyush C. Patel , Eric E. Retter , Barry M. Trager , Michael R. Trombley , Shmuel Winograd , Kenneth L. Wright
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： G06F11/1048
摘要： A system to improve error correction may include a fast decoder to process data packets until the fast decoder finds an uncorrectable error in a data packet at which point a request for at least two data packets is generated. The system may also include a slow decoder to possibly correct the uncorrectable error in a data packet based upon the at least two data packets.
摘要翻译：用于改进纠错的系统可以包括处理数据分组的快速解码器，直到快速解码器在数据分组中发现对于至少两个数据分组的请求产生的不可校正的错误。该系统还可以包括慢解码器，以可能地基于至少两个数据分组校正数据分组中的不可校正错误。

5. 发明申请

US20100287445A1 System to Improve Memory Reliability and Associated Methods 有权
标题翻译：提高内存可靠性和相关方法的系统
公开(公告)号：US20100287445A1
公开(公告)日：2010-11-11
申请号：US12023374
申请日：2008-01-31
申请人： Timothy J. Dell , Luis A. Lastras-Montano , Barry M. Trager , Shmuel Winograd
发明人： Timothy J. Dell , Luis A. Lastras-Montano , Barry M. Trager , Shmuel Winograd
IPC分类号： H03M13/05 , G06F11/10 , H03M13/07
CPC分类号： H03M13/1545 , G06F11/1044 , H03M13/1515
摘要： A system to improve memory reliability in computer systems that may include memory chips, and may rely on a error control encoder to send codeword symbols for storage in each of the memory chips. At least two symbols from a codeword are assigned to each memory chip and therefore failure of any of the memory chips could affect two symbols or more. The system may also include a table to record failures and partial failures of the codeword symbols for each of the memory chips so the error control encoder can correct subsequent partial failures based upon the previous partial failures. The error control coder is capable of correcting and/or detecting more errors if only a fraction of a chip is noted in the table as having a failure as opposed to a full chip noted as having a failure.
摘要翻译：一种用于提高可能包括存储器芯片的计算机系统中的存储器可靠性的系统，并且可以依赖于错误控制编码器来发送用于存储在每个存储器芯片中的码字符号。来自码字的至少两个符号被分配给每个存储器芯片，因此任何存储器芯片的故障可能影响两个或更多个符号。该系统还可以包括用于记录每个存储器芯片的码字符号的故障和部分故障的表，因此错误控制编码器可以基于先前的部分故障来校正随后的部分故障。误差控制编码器能够校正和/或检测更多的误差，如果在表中只有一部分芯片被注意为具有故障，而不是被称为具有故障的全芯片。

6. 发明申请

US20100299576A1 System to Improve Miscorrection Rates in Error Control Code Through Buffering and Associated Methods 失效
标题翻译：系统通过缓冲和相关方法提高错误控制代码的误码率
公开(公告)号：US20100299576A1
公开(公告)日：2010-11-25
申请号：US12023516
申请日：2008-01-31
申请人： Irving G. Baysah , Timothy J. Dell , Luis A. Lastras-Montano , Warren E. Maule , Eric E. Retter , Barry M. Trager , Michael R. Trombley , Shmuel Winograd , Kenneth L. Wright
发明人： Irving G. Baysah , Timothy J. Dell , Luis A. Lastras-Montano , Warren E. Maule , Eric E. Retter , Barry M. Trager , Michael R. Trombley , Shmuel Winograd , Kenneth L. Wright
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： G06F11/1044
摘要： A system to improve miscorrection rates in error control code may include an error control decoder with a safe decoding mode that processes at least two data packets. The system may also include a buffer to receive the processed at least two data packets from the error control decoder. The error control decoder may apply a logic OR operation to the uncorrectable error signal related to the processing of the at least two data packets to produce a global uncorrectable error signal. The system may further include a recipient to receive the at least two data packets and the global uncorrectable error signal.
摘要翻译：用于改善错误控制代码中的错误率的系统可以包括处理至少两个数据分组的具有安全解码模式的错误控制解码器。系统还可以包括缓冲器，以从误差控制解码器接收经处理的至少两个数据分组。误差控制解码器可以对与至少两个数据分组的处理相关的不可校正误差信号应用逻辑或运算，以产生全局不可校正的误差信号。系统还可以包括接收器以接收至少两个数据分组和全局不可校正的误差信号。

7. 发明授权

US08181094B2 System to improve error correction using variable latency and associated methods 有权
标题翻译：使用可变延迟和相关方法改进纠错的系统
公开(公告)号：US08181094B2
公开(公告)日：2012-05-15
申请号：US12023546
申请日：2008-01-31
申请人： Luis A. Lastras-Montano , Piyush C. Patel , Eric E. Retter , Barry M. Trager , Michael R. Trombley , Shmuel Winograd , Kenneth L. Wright
发明人： Luis A. Lastras-Montano , Piyush C. Patel , Eric E. Retter , Barry M. Trager , Michael R. Trombley , Shmuel Winograd , Kenneth L. Wright
IPC分类号： H03M13/00
CPC分类号： G06F11/1048
摘要： A system to improve error correction includes a fast decoder to process data packets until the fast decoder finds an uncorrectable error in a data packet at which point a request for at least two data packets is generated. The system also includes a slow decoder to correct the uncorrectable error in a data packet based upon the at least two data packets.
摘要翻译：改进纠错的系统包括处理数据分组的快速解码器，直到快速解码器在数据分组中发现不可校正的错误，在该时间点产生对至少两个数据分组的请求。该系统还包括缓慢解码器，用于基于至少两个数据分组校正数据分组中的不可校正错误。

8. 发明申请

US20100293437A1 System to Improve Memory Failure Management and Associated Methods 失效
标题翻译：改善内存故障管理和相关方法的系统
公开(公告)号：US20100293437A1
公开(公告)日：2010-11-18
申请号：US12023498
申请日：2008-01-31
申请人： Marc A. Gollub , Luis A. Lastras-Montano , Piyush C. Patel , Eric E. Retter , Barry M. Trager , Shmuel Winograd , Kenneth L. Wright
发明人： Marc A. Gollub , Luis A. Lastras-Montano , Piyush C. Patel , Eric E. Retter , Barry M. Trager , Shmuel Winograd , Kenneth L. Wright
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： H03M13/1545 , G06F11/1048 , H03M13/1515 , H03M13/154 , H03M13/353 , H03M13/3707 , H03M13/6511
摘要： A system to improve memory failure management may include memory, and an error control decoder to determine failures in the memory. The system may also include an agent that may monitor failures in the memory. The system may further include a table where the error control decoder may record the failures, and where the agent can read and write to.
摘要翻译：改善存储器故障管理的系统可以包括存储器和用于确定存储器中的故障的错误控制解码器。系统还可以包括可以监视存储器中的故障的代理。该系统还可以包括一个表，其中错误控制解码器可以记录故障，以及代理可以在哪里读写。

9. 发明申请

US20100287454A1 System to Improve Error Code Decoding Using Historical Information and Associated Methods 有权
标题翻译：使用历史信息和相关方法改进错误代码解码的系统
公开(公告)号：US20100287454A1
公开(公告)日：2010-11-11
申请号：US12023445
申请日：2008-01-31
申请人： Timothy J. Dell , Luis A. Lastras-Montano , Barry M. Trager , Shmuel Winograd
发明人： Timothy J. Dell , Luis A. Lastras-Montano , Barry M. Trager , Shmuel Winograd
IPC分类号： H03M13/09 , G06F11/10
CPC分类号： G06F11/1044
摘要： A system to improve error code decoding using historical information may include storage partitioned into memory ranks, and a table to record symbols having failures for each memory rank. The system may also generate a memory rank score for each memory rank. The system may also include an error control decoder that may use the memory rank score when each memory rank is accessed in order to determine whether an error should be corrected or not.
摘要翻译：使用历史信息改进错误代码解码的系统可以包括分割成存储器排名的存储器，以及记录具有每个存储器级别故障的符号的表。系统还可以为每个存储器等级产生存储器等级分数。系统还可以包括错误控制解码器，其可以在访问每个存储器级时使用存储器等级分数，以便确定是否应该纠正错误。

10. 发明授权

US08171377B2 System to improve memory reliability and associated methods 有权
标题翻译：系统提高内存可靠性和相关方法
公开(公告)号：US08171377B2
公开(公告)日：2012-05-01
申请号：US12023374
申请日：2008-01-31
申请人： Timothy J. Dell , Luis A. Lastras-Montano , Barry M. Trager , Shmuel Winograd
发明人： Timothy J. Dell , Luis A. Lastras-Montano , Barry M. Trager , Shmuel Winograd
IPC分类号： G11C29/00
CPC分类号： H03M13/1545 , G06F11/1044 , H03M13/1515
摘要： A system to improve memory reliability in computer systems that may include memory chips, and may rely on a error control encoder to send codeword symbols for storage in each of the memory chips. At least two symbols from a codeword are assigned to each memory chip and therefore failure of any of the memory chips could affect two symbols or more. The system may also include a table to record failures and partial failures of the codeword symbols for each of the memory chips so the error control encoder can correct subsequent partial failures based upon the previous partial failures. The error control coder is capable of correcting and/or detecting more errors if only a fraction of a chip is noted in the table as having a failure as opposed to a full chip noted as having a failure.
摘要翻译：一种用于提高可能包括存储器芯片的计算机系统中的存储器可靠性的系统，并且可以依赖于错误控制编码器来发送用于存储在每个存储器芯片中的码字符号。来自码字的至少两个符号被分配给每个存储器芯片，因此任何存储器芯片的故障可能影响两个或更多个符号。该系统还可以包括用于记录每个存储器芯片的码字符号的故障和部分故障的表，因此错误控制编码器可以基于先前的部分故障来校正随后的部分故障。误差控制编码器能够校正和/或检测更多的误差，如果在表中只有一部分芯片被注意为具有故障，而不是被称为具有故障的全芯片。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式