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1. 发明授权

US08463985B2 Constrained coding to reduce floating gate coupling in non-volatile memories 失效
标题翻译：约束编码以减少非易失性存储器中的浮动栅极耦合
公开(公告)号：US08463985B2
公开(公告)日：2013-06-11
申请号：US12751197
申请日：2010-03-31
申请人： Michele M. Franceschini , Ashish Jagmohan , Luis A. Lastras-Montano , Mayank Sharma
发明人： Michele M. Franceschini , Ashish Jagmohan , Luis A. Lastras-Montano , Mayank Sharma
IPC分类号： G06F12/02 , H03M13/00
CPC分类号： G11C16/0483 , G06F12/0246 , G06F2212/7202 , G11C7/1006 , G11C16/10
摘要： Constrained coding to reduce floating gate coupling in non-volatile memories including a method for storing data. The method includes receiving write data to be written to a flash memory device, selecting a codeword in response to the write data, and writing the codeword to the flash memory device. The codeword is selected to reduce floating gate coupling in the flash memory device by preventing specified symbol patterns from occurring in the codeword.
摘要翻译：约束编码以减少非易失性存储器中的浮动栅极耦合，包括用于存储数据的方法。该方法包括接收要写入闪速存储器件的写入数据，响应写入数据选择一个代码字，以及将该代码字写入闪存器件。选择码字以通过防止在码字中发生指定的符号模式来减少闪存器件中的浮动栅极耦合。

2. 发明申请

US20130013860A1 MEMORY CELL PRESETTING FOR IMPROVED MEMORY PERFORMANCE 有权
标题翻译：用于改善记忆性能的存储单元预置
公开(公告)号：US20130013860A1
公开(公告)日：2013-01-10
申请号：US13619451
申请日：2012-09-14
申请人： Michele M. Franceschini , Ashish Jagmohan , John P. Karidis , Luis A. Lastras-Montano , Moinuddin K. Qureshi
发明人： Michele M. Franceschini , Ashish Jagmohan , John P. Karidis , Luis A. Lastras-Montano , Moinuddin K. Qureshi
IPC分类号： G06F12/00 , G06F12/08
CPC分类号： G06F12/00 , G06F12/08 , G06F12/0802 , G06F12/0891
摘要： Memory cell presetting for improved performance including a method for using a computer system to identify a region in a memory. The region includes a plurality of memory cells characterized by a write performance characteristic that has a first expected value when a write operation changes a current state of the memory cells to a desired state of the memory cells and a second expected value when the write operation changes a specified state of the memory cells to the desired state of the memory cells. The second expected value is closer than the first expected value to a desired value of the write performance characteristic. The plurality of memory cells in the region are set to the specified state, and the data is written into the plurality of memory cells responsive to the setting.
摘要翻译：用于改进性能的存储单元预设，包括使用计算机系统识别存储器中的区域的方法。该区域包括多个存储单元，其特征在于当写入操作将存储单元的当前状态改变到存储单元的期望状态时具有第一期望值的写入性能特性，以及当写入操作改变时第二预期值存储器单元的指定状态到存储器单元的期望状态。第二期望值比第一期望值更接近写入性能特性的期望值。区域中的多个存储单元被设置为指定状态，并且响应于该设置将数据写入多个存储单元。

3. 发明授权

US08352839B2 Encoding data into constrained memory 失效
标题翻译：将数据编码到受限内存中
公开(公告)号：US08352839B2
公开(公告)日：2013-01-08
申请号：US12814142
申请日：2010-06-11
申请人： Michele M. Franceschini , Ashish Jagmohan , Luis A. Lastras-Montano , Mayank Sharma
发明人： Michele M. Franceschini , Ashish Jagmohan , Luis A. Lastras-Montano , Mayank Sharma
IPC分类号： H03M13/00
CPC分类号： G11C13/0004 , G11C7/1006 , G11C13/00 , G11C13/0069
摘要： Encoding data into constrained memory using a method for writing data that includes receiving write data to be encoded into a write word, receiving constraints on symbol values associated with the write word, encoding the write data into the write word, and writing the write word to a memory. The encoding includes: representing the write data and the constraints as a first linear system in a first field of a first size; embedding the first linear system into a second linear system in a second field of a second size, the second size larger than the first size; solving the second linear system in the second field resulting in a solution; and collapsing the solution into the first field resulting in the write word, the write word satisfying the constraints on symbol values associated with the write word.
摘要翻译：使用用于写入数据的方法将数据编码到约束存储器中，该方法包括接收要编码的写入数据到写入字中，接收与写入字相关联的符号值的约束，将写入数据编码到写入字中，以及将写入字写入一个记忆编码包括：在第一尺寸的第一场中表示作为第一线性系统的写入数据和约束; 在第二尺寸的第二场中将第一线性系统嵌入第二线性系统中，第二尺寸大于第一尺寸; 求解第二个场中的第二个线性系统，得到解决方案; 并且将解决方案折叠到第一场中，导致写入字，写入字满足与写入字相关联的符号值的约束。

4. 发明申请

US20120290898A1 ADAPTIVE ENDURANCE CODING OF NON-VOLATILE MEMORIES 有权
标题翻译：非易失性存储器的自适应耐久编码
公开(公告)号：US20120290898A1
公开(公告)日：2012-11-15
申请号：US13556275
申请日：2012-07-24
申请人： MIchele M. Franceschini , Ashish Jagmohan , John P. Karidis , Luis A. Lastras-Montano
发明人： MIchele M. Franceschini , Ashish Jagmohan , John P. Karidis , Luis A. Lastras-Montano
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： G06F12/0246 , G06F11/1012 , G06F2212/1036 , G06F2212/401 , G06F2212/403 , G06F2212/7207 , G11C16/349
摘要： Adaptive endurance coding including a method for accessing memory that includes retrieving a codeword from a memory address. The codeword is multiplied by a metadata matrix to recover metadata for the codeword. The metadata includes a data location specification. The data in the codeword is identified in response to the metadata and the data is output as read data.
摘要翻译：适应性耐力编码包括用于访问存储器的方法，包括从存储器地址检索码字。将码字乘以元数据矩阵以恢复码字的元数据。元数据包括数据位置规范。代码字中的数据是响应于元数据而被识别的，数据被输出为读取数据。

5. 发明申请

US20120287714A1 INCREASED CAPACITY HETEROGENEOUS STORAGE ELEMENTS 有权
标题翻译：增加容量异质存储元素
公开(公告)号：US20120287714A1
公开(公告)日：2012-11-15
申请号：US13557298
申请日：2012-07-25
申请人： Ibrahim M. Elfadel , Michele M. Franceschini , Ashish Jagmohan , Luis A. Lastras-Montano , Mayank Sharma
发明人： Ibrahim M. Elfadel , Michele M. Franceschini , Ashish Jagmohan , Luis A. Lastras-Montano , Mayank Sharma
IPC分类号： G11C7/00 , G11C11/00 , G11C16/04
CPC分类号： G11C29/08 , G11C11/5678 , G11C13/0004 , G11C13/0069 , G11C2013/0076 , G11C2211/5641
摘要： Providing increased capacity in heterogeneous storage elements including a method for reading from memory. The method includes receiving a read word from a block of memory cells, where physical characteristics of the memory cells support different sets of data levels. The read word is separated into two or more virtual read vectors. For each of the virtual read vectors, the codebook that was utilized to generate the virtual read vector is identified and a partial read data vector is generated. The generating includes multiplying the virtual read vector by a matrix that represents the codebook. The partial read data vectors are combined into a read message and the read message is output.
摘要翻译：在异构存储元件中提供增加的容量，包括从存储器读取的方法。该方法包括从存储器单元块接收读取字，其中存储器单元的物理特性支持不同数据级的集合。读取的字被分成两个或更多个虚拟读取向量。对于每个虚拟读取向量，识别用于生成虚拟读取向量的码本，并生成部分读取数据向量。生成包括将虚拟读取向量乘以代表码本的矩阵。将部分读取数据矢量组合成读取消息，并输出读出的消息。

6. 发明授权

US08176235B2 Non-volatile memories with enhanced write performance and endurance 有权
标题翻译：具有增强的写入性能和耐用性的非易失性存储器
公开(公告)号：US08176235B2
公开(公告)日：2012-05-08
申请号：US12631505
申请日：2009-12-04
申请人： Michele M. Franceschini , Ashish Jagmohan , Luis A. Lastras-Montano , Mayank Sharma
发明人： Michele M. Franceschini , Ashish Jagmohan , Luis A. Lastras-Montano , Mayank Sharma
IPC分类号： G06F12/00
CPC分类号： G06F12/0246
摘要： Enhanced write performance for non-volatile memories including a memory system that includes a receiver for receiving a data rate of a data sequence to be written to a non-volatile flash memory device. The memory system also includes a physical page selector for selecting a physical address of an invalid previously written memory page from a group of physical addresses of invalid previously written memory pages located on the non-volatile memory device, and for determining if the number of free bits in the invalid previously written memory page at the selected physical address is greater than or equal to the data rate. The memory system also includes a transmitter for outputting the selected physical address of the invalid previously written memory page, the outputting in response to the physical page selector determining that the number of free bits is greater than or equal to the data rate.
摘要翻译：对于非易失性存储器的增强的写入性能，包括存储器系统，该存储器系统包括用于接收要写入非易失性闪速存储器件的数据序列的数据速率的接收器。存储器系统还包括物理页面选择器，用于从位于非易失性存储器设备上的无效的先前写入的存储器页面的一组物理地址中选择无效的先前写入的存储器页面的物理地址，并且用于确定是否有空闲数量在所选物理地址处的无效的先前写入的存储器页中的位大于或等于数据速率。存储器系统还包括用于输出无效的先前写入的存储器页面的所选物理地址的发射器，响应于物理页选择器确定空闲位的数量大于或等于数据速率的输出。

7. 发明申请

US20110138105A1 NON-VOLATILE MEMORIES WITH ENHANCED WRITE PERFORMANCE AND ENDURANCE 有权
标题翻译：具有增强的写性能和耐用性的非易失性存储器
公开(公告)号：US20110138105A1
公开(公告)日：2011-06-09
申请号：US12631505
申请日：2009-12-04
申请人： Michele M. Franceschini , Ashish Jagmohan , Luis A. Lastras-Montano , Mayank Sharma
发明人： Michele M. Franceschini , Ashish Jagmohan , Luis A. Lastras-Montano , Mayank Sharma
IPC分类号： G06F12/02 , G06F12/00
CPC分类号： G06F12/0246
摘要： Enhanced write performance for non-volatile memories including a memory system that includes a receiver for receiving a data rate of a data sequence to be written to a non-volatile flash memory device. The memory system also includes a physical page selector for selecting a physical address of an invalid previously written memory page from a group of physical addresses of invalid previously written memory pages located on the non-volatile memory device, and for determining if the number of free bits in the invalid previously written memory page at the selected physical address is greater than or equal to the data rate. The memory system also includes a transmitter for outputting the selected physical address of the invalid previously written memory page, the outputting in response to the physical page selector determining that the number of free bits is greater than or equal to the data rate.
摘要翻译：对于非易失性存储器的增强的写入性能，包括存储器系统，该存储器系统包括用于接收要写入非易失性闪速存储器件的数据序列的数据速率的接收器。存储器系统还包括物理页面选择器，用于从位于非易失性存储器设备上的无效的先前写入的存储器页面的一组物理地址中选择无效的先前写入的存储器页面的物理地址，并且用于确定是否有空闲数量在所选物理地址处的无效的先前写入的存储器页中的位大于或等于数据速率。存储器系统还包括用于输出无效的先前写入的存储器页面的所选物理地址的发射器，响应于物理页选择器确定空闲位的数量大于或等于数据速率的输出。

8. 发明申请

US20130212427A1 RECLAIMING DISCARDED SOLID STATE DEVICES 有权
标题翻译：重新抛弃固定状态装置
公开(公告)号：US20130212427A1
公开(公告)日：2013-08-15
申请号：US13396020
申请日：2012-02-14
申请人： Michele M. Franceschini , Ashish Jagmohan , Luis A. Lastras-Montano , Mayank Sharma
发明人： Michele M. Franceschini , Ashish Jagmohan , Luis A. Lastras-Montano , Mayank Sharma
IPC分类号： G06F11/16
CPC分类号： G11C29/56008 , G06F11/2289 , G06F11/3409 , G11C16/349
摘要： Discarded memory devices unfit for an original purpose can be reclaimed for reuse for another purpose. The discarded memory devices are tested and evaluated to determine the level of performance degradation therein. A set of an alternate usage and an information encoding scheme to facilitate a reuse of the tested memory device is identified based on the evaluation of the discarded memory device. A memory chip controller may be configured to facilitate usage of reclaimed memory devices by enabling a plurality of encoding schemes therein. Further, a memory device can be configured to facilitate diagnosis of the functionality, and to facilitate usage as a discarded memory unit. Waste due to discarded memory devices can be thereby reduced.
摘要翻译：废弃的不适合原始目的的存储设备可以回收再利用用于另一目的。对废弃的存储器件进行测试和评估，以确定其中性能下降的程度。基于对废弃的存储器件的评估来识别一组替代使用和信息编码方案，以便于重新使用被测试的存储器件。存储器芯片控制器可以被配置为通过使能其中的多个编码方案来促进再生存储器件的使用。此外，存储器装置可以被配置为便于诊断功能，并且便于作为丢弃的存储器单元的使用。因此可以减少由于废弃的存储器件造成的浪费。

9. 发明授权

US08464137B2 Probabilistic multi-tier error correction in not-and (NAND) flash memory 有权
标题翻译：不和（NAND）闪存中的概率多层纠错
公开(公告)号：US08464137B2
公开(公告)日：2013-06-11
申请号：US12960004
申请日：2010-12-03
申请人： Michele M. Franceschini , Ashish Jagmohan , Luis A. Lastras-Montano , Mayank Sharma
发明人： Michele M. Franceschini , Ashish Jagmohan , Luis A. Lastras-Montano , Mayank Sharma
IPC分类号： G06F11/00
CPC分类号： G06F11/1012 , H03M13/2906 , H03M13/3715 , H03M13/3738
摘要： Error correction in not-and (NAND) flash memory including a system for retrieving data from memory. The system includes a decoder in communication with a memory. The decoder is for performing a method that includes receiving a codeword stored on a page in the memory, the codeword including data and first-tier check symbols that are generated in response to the data. The method further includes determining that the codeword includes errors that cannot be corrected using the first-tier check symbols, and in response second-tier check symbols are received. The second-tier check symbols are generated in response to receiving the data and to the contents of other pages in the memory that were written prior to the page containing the codeword. The codeword is corrected in response to the second-tier check symbols. The corrected codeword is output.
摘要翻译：在非NAND（NAND）闪存中包括用于从存储器检索数据的系统的纠错。该系统包括与存储器通信的解码器。解码器用于执行包括接收存储在存储器中的页面上的码字的方法，所述码字包括响应于该数据生成的数据和第一层校验符号。该方法还包括确定码字包括不能使用第一层校验符号校正的错误，并且响应于接收到第二层校验符号。响应于接收到包含码字的页面之前写入的数据和存储器中其他页面的内容，生成第二层校验符号。响应于第二层校验符号校正码字。校正的码字被输出。

10. 发明授权

US08341501B2 Adaptive endurance coding of non-volatile memories 有权
标题翻译：非易失性存储器的适应性耐力编码
公开(公告)号：US08341501B2
公开(公告)日：2012-12-25
申请号：US12433669
申请日：2009-04-30
申请人： Michele M. Franceschini , Ashish Jagmohan , John P. Karidis , Luis A. Lastras-Montano
发明人： Michele M. Franceschini , Ashish Jagmohan , John P. Karidis , Luis A. Lastras-Montano
IPC分类号： H03M13/00 , G11C29/00
CPC分类号： G06F12/0246 , G06F11/1012 , G06F2212/1036 , G06F2212/401 , G06F2212/403 , G06F2212/7207 , G11C16/349
摘要： Adaptive endurance coding including a method for storing data that includes receiving write data and a write address. A compression algorithm is applied to the write data to generate compressed data. An endurance code is applied to the compressed data to generate a codeword. The endurance code is selected and applied in response to the amount of space saved by applying the compression to the write data. The codeword is written to the write address.
摘要翻译：自适应耐力编码包括用于存储包括接收写入数据和写入地址的数据的方法。将压缩算法应用于写入数据以生成压缩数据。将耐力码应用于压缩数据以产生码字。响应于通过将压缩应用于写数据而节省的空间量来选择和应用耐久代码。代码字被写入写入地址。

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