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11. 发明授权

US07796446B2 Memory dies for flexible use and method for configuring memory dies 有权
标题翻译：用于灵活使用的存储器模块和用于配置存储器管芯的方法
公开(公告)号：US07796446B2
公开(公告)日：2010-09-14
申请号：US12234312
申请日：2008-09-19
申请人： Hermann Ruckerbauer , Michael Bruennert , Ullrich Menczigar , Christian Mueller , Sitt Tontisirin , Georg Braun , Dominique Savignac
发明人： Hermann Ruckerbauer , Michael Bruennert , Ullrich Menczigar , Christian Mueller , Sitt Tontisirin , Georg Braun , Dominique Savignac
IPC分类号： G11C7/10
CPC分类号： G11C7/1048 , G11C7/1006 , G11C7/1051 , G11C7/1057 , G11C7/1078 , G11C7/1084 , G11C29/70 , H01L2224/16145
摘要： A memory die, including a memory array, a memory array data terminal and a data bus that includes a first sub bus and a second sub bus is disclosed. A first bi-directional buffer arranged between the memory array data terminal and the first sub bus and a second bi-directional buffer arranged between the memory array data terminal and the second sub bus is also disclosed. The first and second bi-directional buffers are adapted to couple the first sub bus or the second sub bus to the memory array data terminal at a time.
摘要翻译：公开了包括存储器阵列，存储器阵列数据终端和包括第一子总线和第二子总线的数据总线的存储器管芯。还公开了布置在存储器阵列数据终端和第一子总线之间的第一双向缓冲器和布置在存储器阵列数据终端和第二副总线之间的第二双向缓冲器。第一和第二双向缓冲器一次适于将第一子总线或第二子总线耦合到存储器阵列数据终端。

12. 发明授权

US07698470B2 Integrated circuit, chip stack and data processing system 失效
标题翻译：集成电路，芯片堆栈和数据处理系统
公开(公告)号：US07698470B2
公开(公告)日：2010-04-13
申请号：US11834617
申请日：2007-08-06
申请人： Hermann Ruckerbauer , Dominique Savignac
发明人： Hermann Ruckerbauer , Dominique Savignac
IPC分类号： G06F3/00 , H03K19/173 , H01L25/00
CPC分类号： G11C5/04 , G11C5/02 , G11C7/10 , G11C29/1201 , G11C2029/0407 , H01L2224/16145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/4824 , H01L2224/73257 , H01L2224/73265 , H01L2924/00014 , H01L2924/00
摘要： An integrated circuit includes a first connection and a memory circuit. The integrated circuit is switchable between a master mode of operation, in which a buffer between the first connection and the memory circuit is activated, and a slave mode of operation, in which the buffer between the first connection and the memory circuit is deactivated.
摘要翻译：集成电路包括第一连接和存储电路。集成电路可以在其中第一连接和存储器电路之间的缓冲器被激活的主操作模式和从动操作模式之间切换，其中第一连接和存储器电路之间的缓冲器被停用。

13. 发明申请

US20090122628A1 DEVICE WITH PRECHARGE/HOMOGENIZE CIRCUIT 有权
标题翻译：具有预充电/均质电路的器件
公开(公告)号：US20090122628A1
公开(公告)日：2009-05-14
申请号：US12122273
申请日：2008-05-16
申请人： Dominique Savignac , Helmut Schneider
发明人： Dominique Savignac , Helmut Schneider
IPC分类号： G11C7/00
CPC分类号： H01L27/10897 , G11C11/4085 , G11C11/4094 , H01L27/0207 , H01L27/105
摘要： A device with a precharge/homogenize circuit. One embodiment provides at least one switching element is acting as a homogenizer, and at least one switching element is acting as a precharger. The diffusion region of the switching element acting as a homogenizer is separated from the diffusion region of the switching element acting as a precharger.
摘要翻译：具有预充电/均质电路的器件。一个实施例提供至少一个开关元件用作均化器，并且至少一个开关元件充当预充电器。作为均化器的开关元件的扩散区域与作为预充电器的开关元件的扩散区域分离。

14. 发明申请

US20080217655A1 INTEGRATED CIRCUIT WITH BURIED CONTROL LINE STRUCTURES 失效
标题翻译：集成电路与布线控制线结构
公开(公告)号：US20080217655A1
公开(公告)日：2008-09-11
申请号：US12028474
申请日：2008-02-08
申请人： Dirk Baumann , Dominique Savignac , Till Schloesser , Helmut Schneider
发明人： Dirk Baumann , Dominique Savignac , Till Schloesser , Helmut Schneider
IPC分类号： H01L29/76
CPC分类号： H01L27/10891
摘要： An integrated circuit with buried control line structures. In one embodiment, the control lines are subdivided into sections, wherein regions free of switching transistors are provided at intervals along the control lines. Connections for feeding the control potentials into the sections of the control lines are provided at least in a subset of the regions free of switching transistors. The isolations lines are connected to one another by an interconnect running transversely with respect to the control lines.
摘要翻译：具有埋地控制线结构的集成电路。在一个实施例中，控制线被细分为多个部分，其中不存在开关晶体管的区域沿着控制线间隔设置。至少在没有开关晶体管的区域的子集中提供用于将控制电位馈送到控制线的部分中的连接。隔离线通过相对于控制线横向运行的互连而彼此连接。

15. 发明申请

US20070033487A1 Semiconductor memory device and method of operating the same 有权
标题翻译：半导体存储器件及其操作方法
公开(公告)号：US20070033487A1
公开(公告)日：2007-02-08
申请号：US11182063
申请日：2005-07-15
申请人： Hermann Ruckerbauer , Dominique Savignac
发明人： Hermann Ruckerbauer , Dominique Savignac
IPC分类号： G11C29/00
CPC分类号： G11C7/1006 , G06F11/1052 , G11C29/42 , G11C2207/104
摘要： A semiconductor memory device including semiconductor memory cells with at least one memory cell capable of either acting as a storage device for ECC information or of acting as a redundant memory cell is provided. The semiconductor memory device further includes a signal control device for signaling if the at least one memory cell is to be used either as a storage device or as a redundant memory cell. A method of operating a semiconductor memory device is also provided including the steps of registering a status of a signal device and, depending on the status of the signal device, operating the at least one memory cell either as a storing device for ECC information or as a redundant memory cell.
摘要翻译：提供一种半导体存储器件，其包括具有至少一个存储单元的半导体存储单元，所述至少一个存储单元可以充当用于ECC信息的存储器件或用作冗余存储器单元。半导体存储器件还包括信号控制装置，用于发信号通知至少一个存储单元是作为存储装置还是用作冗余存储单元。还提供了一种操作半导体存储器件的方法，包括以下步骤：注册信号器件的状态，并且根据信号器件的状态，操作至少一个存储器单元作为ECC信息的存储设备或者作为冗余存储单元。

16. 发明授权

US06458631B1 Method for fabricating an integrated circuit, in particular an antifuse 有权
标题翻译：用于制造集成电路的方法，特别是反熔丝
公开(公告)号：US06458631B1
公开(公告)日：2002-10-01
申请号：US10079045
申请日：2002-02-19
申请人： Axel Brintzinger , Ulrich Frey , Jürgen Lindolf , Dominique Savignac , Stefan Dankowski , Matthias Lehr , Jochen Müller , Kamel Ayadi
发明人： Axel Brintzinger , Ulrich Frey , Jürgen Lindolf , Dominique Savignac , Stefan Dankowski , Matthias Lehr , Jochen Müller , Kamel Ayadi
IPC分类号： H01L2182
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides a method for fabricating an integrated circuit, comprising the following steps: preparing a circuit substrate (1); providing a metallization region (10a) comprising a first metal in the circuit substrate (1); providing a first insulation layer (25) above the metallization region (10a); forming an opening (13) in the insulating layer (25) in order to uncover at least part of the surface of the metallization region (10a); depositing a functional layer (15′) above the resulting structure; depositing a second insulating layer (35) above the resulting structure, in such a manner that the opening (13) is filled; polishing-back of the second insulating layer (35) and of the functional layer (15′) in order to uncover the surface of the first insulating layer (25); forming a contact (11a′) in the second insulating layer (35) inside the opening (13) in order to make contact with the functional layer (15′); and providing an interconnect (40a) for electrical connection of the contact (11a′).
摘要翻译：本发明提供一种制造集成电路的方法，包括以下步骤：制备电路基板（1）; 在所述电路基板（1）中提供包括第一金属的金属化区域（10a）; 在所述金属化区域（10a）之上提供第一绝缘层（25）; 在所述绝缘层（25）中形成开口（13），以便露出所述金属化区域（10a）的所述表面的至少一部分; 在所得结构上沉积功能层（15'）; 以所述开口（13）填充的方式在所得结构上方沉积第二绝缘层（35）; 第二绝缘层（35）和功能层（15'）的抛光以便露出第一绝缘层（25）的表面; 在所述开口（13）内部的所述第二绝缘层（35）中形成接触（11a'），以与所述功能层（15'）接触。以及提供用于电连接触头（11a'）的互连（40a）。

17. 发明授权

US5546036A Circuit array for amplifying and holding data with different supply 失效
标题翻译：用于放大和保存不同电源的数据的电路阵列
公开(公告)号：US5546036A
公开(公告)日：1996-08-13
申请号：US376683
申请日：1995-01-23
申请人： Diether Sommer , Dominique Savignac , Dieter Gleis
发明人： Diether Sommer , Dominique Savignac , Dieter Gleis
IPC分类号： G11C7/06 , G11C7/10 , G11C11/4093 , H03K3/286
CPC分类号： G11C11/4093 , G11C7/065 , G11C7/1051
摘要： A circuit array for amplifying and holding data with different supply voltages includes a first flip-flop being constructed in MOS technology for receiving a low supply voltage and data with a low supply voltage. The first flip-flop has output terminals. A second flip-flop being constructed in MOS technology receives a high supply voltage. The second flip-flop has a load segment and output terminals. At least one additional MOS transistor is connected in series with each of the output terminals of the second flip-flop between the load segment and ground. The at least one additional MOS transistor each has a gate terminal being connected to a respective one of the output terminals of the first flip-flip. A device for activating the first and second flip-flops is triggered for amplifying and holding the data to activate the first flip-flop and to activate the second flip-flop after a time delay.
摘要翻译：用于放大和保持具有不同电源电压的数据的电路阵列包括以MOS技术构造的用于接收低电源电压的第一触发器和具有低电源电压的数据。第一个触发器具有输出端子。以MOS技术构造的第二个触发器接收高电源电压。第二个触发器具有负载段和输出端。至少一个额外的MOS晶体管与负载段和地之间的第二触发器的每个输出端串联连接。所述至少一个附加MOS晶体管的每个栅极端子连接到第一翻盖的输出端子的相应一个。触发用于激活第一和第二触发器的装置，用于放大和保持数据以激活第一触发器并在时间延迟之后激活第二触发器。

18. 发明申请

US20090039915A1 Integrated Circuit, Chip Stack and Data Processing System 失效
标题翻译：集成电路，芯片堆栈和数据处理系统
公开(公告)号：US20090039915A1
公开(公告)日：2009-02-12
申请号：US11834617
申请日：2007-08-06
申请人： Hermann Ruckerbauer , Dominique Savignac
发明人： Hermann Ruckerbauer , Dominique Savignac
IPC分类号： G06F7/38 , H03K19/173
CPC分类号： G11C5/04 , G11C5/02 , G11C7/10 , G11C29/1201 , G11C2029/0407 , H01L2224/16145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/4824 , H01L2224/73257 , H01L2224/73265 , H01L2924/00014 , H01L2924/00
摘要： An integrated circuit includes a first connection and a memory circuit. The integrated circuit is switchable between a master mode of operation, in which a buffer between the first connection and the memory circuit is activated, and a slave mode of operation, in which the buffer between the first connection and the memory circuit is deactivated.
摘要翻译：集成电路包括第一连接和存储电路。集成电路可以在其中第一连接和存储器电路之间的缓冲器被激活的主操作模式和从动操作模式之间切换，其中第一连接和存储器电路之间的缓冲器被停用。

19. 发明申请

US20070061671A1 Data memory system and method for transferring data into a data memory 有权
标题翻译：用于将数据传送到数据存储器的数据存储器系统和方法
公开(公告)号：US20070061671A1
公开(公告)日：2007-03-15
申请号：US11217081
申请日：2005-08-30
申请人： Paul Wallner , Dominique Savignac , Christian Sichert , Thomas Hein
发明人： Paul Wallner , Dominique Savignac , Christian Sichert , Thomas Hein
IPC分类号： H03M13/00
CPC分类号： G06F13/4243 , G06F11/1052
摘要： A method for transferring data into a data memory using a data protocol is presented. The data memory is an error correction code (ECC) memory or a non-error correction code memory. The data protocol has different frames. When data are written into an ECC memory, the protocol includes a data mask frame in which the data mask bits are replaced by ECC bits. The method is designed such that ECC and non-ECC DRAMs can be established with the same protocol and at least a similar architecture.
摘要翻译：提出了一种使用数据协议将数据传输到数据存储器中的方法。数据存储器是纠错码（ECC）存储器或非纠错码存储器。数据协议具有不同的帧。当数据被写入ECC存储器时，该协议包括数据屏蔽帧，其中数据屏蔽位被ECC位替换。该方法被设计成使得可以使用相同的协议和至少相似的架构来建立ECC和非ECC DRAM。

20. 发明授权

US07173877B2 Memory system with two clock lines and a memory device 有权
标题翻译：具有两个时钟线和存储器件的存储器系统
公开(公告)号：US07173877B2
公开(公告)日：2007-02-06
申请号：US10955177
申请日：2004-09-30
申请人： Hermann Ruckerbauer , Christian Sichert , Dominique Savignac , Peter Gregorius , Paul Wallner
发明人： Hermann Ruckerbauer , Christian Sichert , Dominique Savignac , Peter Gregorius , Paul Wallner
IPC分类号： G11C8/00
CPC分类号： G11C5/04 , G11C5/063 , G11C7/22 , G11C7/222 , G11C11/4076
摘要： The present invention relates to a memory system having a memory device with two clock lines. One embodiment of the present invention provides a memory system comprising at least one memory device, a memory controller to control operation of the memory device, a first clock line which extends from a write clock output of the memory controller to a clock port of the memory device to provide a clock signal to the memory device, and a second clock line which extends from the clock port of the memory device to a read clock input of the memory controller to forward the clock signal applied to the clock port of the memory device back to a read clock input of the memory controller. The memory device may further comprise a synchronization circuit adapted to receive the clock signal from the memory controller and to, provide an output data synchronized to the forwarded clock signal.
摘要翻译：本发明涉及一种具有两条时钟线的存储器件的存储器系统。本发明的一个实施例提供了一种存储器系统，其包括至少一个存储器件，用于控制存储器件的操作的存储器控制器，从存储器控制器的写时钟输出延伸到存储器的时钟端口的第一时钟线向存储器件提供时钟信号的第二时钟线，以及从存储器件的时钟端口延伸到存储器控制器的读时钟输入端的第二时钟线，以将施加到存储器件的时钟端口的时钟信号转发回到存储器控制器的读时钟输入。存储器件还可以包括同步电路，其适于从存储器控制器接收时钟信号，并提供与转发的时钟信号同步的输出数据。

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