专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明授权

US5710054A Method of forming a shallow junction by diffusion from a silicon-based spacer 失效
标题翻译：通过从硅基间隔物扩散形成浅结的方法
公开(公告)号：US5710054A
公开(公告)日：1998-01-20
申请号：US703273
申请日：1996-08-26
申请人： Mark I. Gardner , Robert Dawson , H. Jim Fulford, Jr. , Frederick N. Hause , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
发明人： Mark I. Gardner , Robert Dawson , H. Jim Fulford, Jr. , Frederick N. Hause , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
IPC分类号： H01L21/225 , H01L21/28 , H01L21/336 , H01L29/08 , H01L29/78 , H01L21/265 , H01L21/385
CPC分类号： H01L29/66575 , H01L21/2256 , H01L21/2257 , H01L21/28105 , H01L21/28114 , H01L29/0847 , H01L29/41783 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7833 , H01L29/7834
摘要： A method of forming a shallow junction in an IGFET is disclosed. The method includes forming a gate insulator on a semiconductor substrate of first conductivity type, forming a gate electrode on the gate insulator, forming a sidewall insulator on an edge of the gate electrode, forming a silicon-based spacer over the substrate such that the sidewall insulator separates and electrically isolates the spacer and the gate electrode, and diffusing a dopant of second conductivity type from the spacer into the substrate. The diffused dopant forms a shallow region of second conductivity type in the substrate, and a shallow junction is substantially laterally aligned with the edge of the gate electrode.
摘要翻译：公开了一种在IGFET中形成浅结的方法。该方法包括在第一导电类型的半导体衬底上形成栅极绝缘体，在栅极绝缘体上形成栅电极，在栅电极的边缘上形成侧壁绝缘体，在衬底上形成硅基间隔物，使得侧壁绝缘体分离并电隔离间隔物和栅电极，并将第二导电类型的掺杂剂从间隔物扩散到衬底中。扩散掺杂剂在衬底中形成第二导电类型的浅区域，并且浅结与栅电极的边缘基本上横向对齐。

12. 发明授权

US06353253B2 Semiconductor isolation region bounded by a trench and covered with an oxide to improve planarization 有权
标题翻译：由沟槽限定并被氧化物覆盖以改善平坦化的半导体隔离区
公开(公告)号：US06353253B2
公开(公告)日：2002-03-05
申请号：US09227914
申请日：1999-01-08
申请人： Fred N. Hause , Basab Bandyopadhyay , H. Jim Fulford, Jr. , Robert Dawson , Mark W. Michael , William S. Brennan
发明人： Fred N. Hause , Basab Bandyopadhyay , H. Jim Fulford, Jr. , Robert Dawson , Mark W. Michael , William S. Brennan
IPC分类号： H01L2900
CPC分类号： H01L21/76205 , H01L21/76229
摘要： An isolation technique is provided for improving the overall planarity of isolation regions relative to adjacent active area silicon mesas. The isolation process results in a trench formed in field regions immediately adjacent the active regions. The trench, however, does not extend entirely across the field region. By preventing large area trenches, substantial dielectric fill material and the problems of subsequent planarization of that fill material is avoided. Accordingly, the present isolation technique does not require conventional fill dielectric normally associated with a shallow trench process. While it achieves the advantages of forming silicon mesas, the present process avoids having to rework dielectric surfaces in large area field regions using conventional sacrificial etchback, block masking and chemical-mechanical polishing. The improved isolation technique hereof utilizes trenches of minimal width etched into the silicon substrate at the periphery of field regions, leaving a field mesa. A field dielectric, preferably oxide, is formed upon the field mesa and fills trenches between the field mesa and active mesas, leaving a substantially planar field dielectric commensurate with the upper surface of adjacent active mesas.
摘要翻译：提供隔离技术用于改善隔离区域相对于相邻有源区硅台面的整体平面度。隔离过程导致在紧邻有源区域的场区域中形成沟槽。然而，这个沟槽并不完全穿过田野区域。通过防止大面积沟槽，避免了大量的介电填充材料以及该填充材料随后的平坦化问题。因此，本发明的隔离技术不需要通常与浅沟槽工艺相关联的常规填充电介质。虽然它实现了形成硅台面的优点，但是本方法避免了使用常规的牺牲回蚀，块掩模和化学机械抛光在大面积场区域中的电介质表面的返修。其改进的隔离技术利用在场区周边蚀刻到硅衬底中的最小宽度的沟槽，留下场台面。在场台面上形成场电介质，优选氧化物，并填充场台面和有源台面之间的沟槽，留下与相邻活性台面的上表面相当的基本上平面的场电介质。

13. 发明授权

US6111260A Method and apparatus for in situ anneal during ion implant 失效
标题翻译：离子注入过程中原位退火的方法和装置
公开(公告)号：US6111260A
公开(公告)日：2000-08-29
申请号：US872258
申请日：1997-06-10
申请人： Robert Dawson , H. Jim Fulford, Jr. , Mark I. Gardner , Frederick N. Hause , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
发明人： Robert Dawson , H. Jim Fulford, Jr. , Mark I. Gardner , Frederick N. Hause , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
IPC分类号： H01J37/317
CPC分类号： H01J37/3171 , H01J2237/316
摘要： During a semiconductor substrate ion implant process thermal energy is supplied to raise the temperature of the semiconductor wafer. The increased temperature of the semiconductor wafer during implantation acts to anneal the implanted impurities or dopants in the wafer, reducing impurity diffusion and reducing the number of fabrication process steps. An ion implant device includes an end station that is adapted for application and control of thermal energy to the end station for raising the temperature of a semiconductor substrate wafer during implantation. The adapted end station includes a heating element for heating the semiconductor substrate wafer, a thermocouple for sensing the temperature of the semiconductor substrate wafer, and a controller for monitoring the sensed temperature and controlling the thermal energy applied to the semiconductor substrate wafer by the heating element. An ion implant device including a system for applying and controlling thermal energy applied to a semiconductor substrate wafer during ion implantation raises the temperature of the wafer to a temperature that is sufficient to activate impurities within the semiconductor substrate wafer when an ion beam is implanting ions to the wafer, but the temperature is insufficient to activate impurities when the ion beam is inactive.
摘要翻译：在半导体衬底离子注入过程中，提供热能以提高半导体晶片的温度。在注入期间半导体晶片的温度升高期间用于退火晶片中注入的杂质或掺杂剂，减少杂质扩散并减少制造工艺步骤的数量。离子注入装置包括终端站，其适于向端站施加和控制热能，以在植入期间提高半导体衬底晶片的温度。适用的端站包括用于加热半导体衬底晶片的加热元件，用于感测半导体衬底晶片的温度的热电偶，以及用于监测感测温度并通过加热元件控制施加到半导体衬底晶片的热能的控制器。包括用于在离子注入期间施加和控制施加到半导体衬底晶片的热能的系统的离子注入装置将晶片的温度升高到当离子束注入离子时足以激活半导体衬底晶片内的杂质的温度晶片，但当离子束无效时，温度不足以激活杂质。

14. 发明授权

US6090703A Method of forming an integrated circuit having conductors of enhanced cross-sectional area with etch stop barrier layer 有权
标题翻译：形成集成电路的方法，其具有具有蚀刻停止阻挡层的具有增强的横截面面积的导体
公开(公告)号：US6090703A
公开(公告)日：2000-07-18
申请号：US165765
申请日：1998-10-02
申请人： Basab Bandyopadhyay , H. Jim Fulford, Jr. , William S. Brennan , Fred N. Hause , Robert Dawson , Mark W. Michael
发明人： Basab Bandyopadhyay , H. Jim Fulford, Jr. , William S. Brennan , Fred N. Hause , Robert Dawson , Mark W. Michael
IPC分类号： H01L21/60 , H01L21/768 , H01L23/522 , H01L21/4763
CPC分类号： H01L23/5226 , H01L21/76816 , H01L21/76838 , H01L2924/0002
摘要： A interconnect structure is provided having a conductor with enhanced thickness. The conductor includes an upper portion and a lower portion, wherein the lower portion geometry is sufficient to increase the current-carrying capacity beyond that provided by the upper portion. The lower portion is formed by filling a trench within an upper dielectric region, and the upper portion is formed by selectively removing a conductive material from the upper dielectric surface except for regions directly above the lower portion. The upper and lower portions thereby form a conductor of enhanced cross-section which can be produced by modifying a via-etch mask, rather than having to reconfigure and/or move interconnect features formed by a metal mask.
摘要翻译：提供具有增强厚度的导体的互连结构。导体包括上部和下部，其中下部几何形状足以增加超过上部提供的载流能力。下部通过在上部电介质区域内填充沟槽而形成，并且通过从直接在下部的正上方的区域除去上电介质表面的导电材料形成上部。上部和下部由此形成增强横截面的导体，其可以通过修改通孔蚀刻掩模而不是必须重新配置和/或移动由金属掩模形成的互连特征而产生。

15. 发明授权

US6074904A Method and structure for isolating semiconductor devices after transistor formation 失效
标题翻译：在晶体管形成之后隔离半导体器件的方法和结构
公开(公告)号：US6074904A
公开(公告)日：2000-06-13
申请号：US63796
申请日：1998-04-21
申请人： Thomas E. Spikes, Jr. , Mark W. Michael , Mark I. Gardner , Robert Dawson
发明人： Thomas E. Spikes, Jr. , Mark W. Michael , Mark I. Gardner , Robert Dawson
IPC分类号： H01L21/762 , H01L21/8238
CPC分类号： H01L21/823878 , H01L21/76237
摘要： A method for isolating semiconductor devices comprising providing a semiconductor substrate. The semiconductor substrate includes a first pair of source/drain regions on either side of a first channel region and a second pair of source/drain regions on either side of a second channel region. One of the first pair of source/drain regions is proximal to one of the second pair of source/drain regions. First and second laterally displaced MOS transistors are formed partially within the semiconductor substrate. An isolation trench is formed through the proximal source/drain regions and the trench is filled with a trench dielectric material such that the proximal source/drain regions are electrically isolated whereby the first transistor is electrically isolated from the second transistor.
摘要翻译：一种用于隔离半导体器件的方法，包括提供半导体衬底。半导体衬底包括在第一沟道区的任一侧上的第一对源/漏区和在第二沟道区的任一侧上的第二对源极/漏极区。第一对源极/漏极区域中的一个靠近第二对源极/漏极区域中的一个。第一和第二横向位移的MOS晶体管部分地形成在半导体衬底内。通过近端源极/漏极区域形成隔离沟槽，并且沟槽填充有沟槽电介质材料，使得近端源极/漏极区域被电隔离，由此第一晶体管与第二晶体管电隔离。

16. 发明授权

US6031289A Integrated circuit which uses a recessed local conductor for producing staggered interconnect lines 失效
标题翻译：集成电路，其使用凹入的局部导体来产生交错的互连线
公开(公告)号：US6031289A
公开(公告)日：2000-02-29
申请号：US034589
申请日：1998-03-04
申请人： H. Jim Fulford, Jr. , Basab Bandyopadhyay , Robert Dawson , Fred N. Hause , Mark W. Michael , William S. Brennan
发明人： H. Jim Fulford, Jr. , Basab Bandyopadhyay , Robert Dawson , Fred N. Hause , Mark W. Michael , William S. Brennan
IPC分类号： H01L21/302 , H01L21/3065 , H01L21/316 , H01L21/3205 , H01L21/768 , H01L21/822 , H01L23/52 , H01L23/522 , H01L27/04 , A07C29/41
CPC分类号： H01L23/5222 , H01L21/768 , H01L2924/0002
摘要： An improved multilevel interconnect structure is provided. The interconnect structure includes several levels of conductors, wherein conductors on one level are staggered with respect to conductors on another level. In densely spaced interconnect areas, interposed conductors are drawn to dissimilar elevational levels to lessen the capacitive coupling between the interconnects. By staggering every other interconnect line in the densely patterned areas, the interconnects are capable of carrying a larger amount of current with minimal capacitive coupling therebetween.
摘要翻译：提供了一种改进的多级互连结构。互连结构包括多个级别的导体，其中一个层上的导体相对于另一层上的导体交错。在密集间隔的互连区域中，插入的导体被拉至不同的高度级以减小互连之间的电容耦合。通过交错密集图案化区域中的每隔一个互连线，互连能够承载更大量的电流并且在其间具有最小的电容耦合。

17. 发明授权

US6030752A Method of stitching segments defined by adjacent image patterns during the manufacture of a semiconductor device 失效
标题翻译：在制造半导体器件期间缝合由相邻图像图案定义的片段的方法
公开(公告)号：US6030752A
公开(公告)日：2000-02-29
申请号：US805534
申请日：1997-02-25
申请人： H. Jim Fulford, Jr. , Robert Dawson , Mark I. Gardner , Frederick N. Hause , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
发明人： H. Jim Fulford, Jr. , Robert Dawson , Mark I. Gardner , Frederick N. Hause , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
IPC分类号： G03F7/20
CPC分类号： G03F7/70475
摘要： A method of stitching segments defined by adjacent image patterns of a photolithographic system during the manufacture of a semiconductor device is disclosed. The method includes forming a material over a semiconductor substrate, projecting a first image pattern over the substrate that defines a first segment and a contact region, projecting a second image pattern over the substrate that defines a second segment with an end that overlaps the contact region, and removing a portion of the material corresponding to the first and second image patterns to form the first and second segments stitched by a portion of the contact region. The contact region has a greater width than the first and second segments. In this manner, the contact region accommodates misalignments that might otherwise lead to inadequate coupling or decoupling between the first and second segments. The invention is particularly well-suited for stitching polysilicon gates of N-channel and P-channel devices.
摘要翻译：公开了一种在制造半导体器件期间缝合由光刻系统的相邻图像图案限定的片段的方法。该方法包括在半导体衬底上形成材料，将限定第一部分和接触区域的第一图案图案投影在衬底上，将限定第二部分的第二图像图案投影在衬底上，端部与接触区域重叠以及去除对应于第一和第二图像图案的材料的一部分以形成由接触区域的一部分缝合的第一和第二段。接触区域具有比第一和第二段更大的宽度。以这种方式，接触区域适应可能导致第一和第二段之间不充分的耦合或解耦的未对准。本发明特别适用于拼接N沟道和P沟道器件的多晶硅栅极。

18. 发明授权

US5976956A Method of controlling dopant concentrations using transient-enhanced diffusion prior to gate formation in a device 失效
标题翻译：在器件中栅极形成之前使用瞬态增强扩散来控制掺杂剂浓度的方法
公开(公告)号：US5976956A
公开(公告)日：1999-11-02
申请号：US837936
申请日：1997-04-11
申请人： Mark I. Gardner , Derick J. Wristers , Robert Dawson , H. Jim Fulford, Jr. , Frederick N. Hause , Mark W. Michael , Bradley T. Moore
发明人： Mark I. Gardner , Derick J. Wristers , Robert Dawson , H. Jim Fulford, Jr. , Frederick N. Hause , Mark W. Michael , Bradley T. Moore
IPC分类号： H01L21/336 , H01L21/265 , H01L21/322 , H01L29/78
CPC分类号： H01L21/26506 , H01L21/3221 , Y10S148/024 , Y10S148/06
摘要： Dopant atoms have coefficients of diffusion that vary due to implant damage. Damaged regions are selected and created by implanting silicon atoms into a silicon substrate prior to formation of a gate electrode. The silicon atoms act as a getter for attracting selected dopants that are trapped in the silicon substrate. Dopants are implanted in the vicinity of the damaged regions and diffused by transient-enhanced diffusion (TED) into the damaged regions by thermal cycling to accumulate dopant atoms. Transient-enhanced diffusion improves the doping of a substrate by enhancing the diffusion of dopants at relatively low anneal temperatures. Dopant accumulation sets particular selected electrical properties without placing an excessive amount of dopant in regions adjacent to junctions for purposes including threshold control for a field device, threshold setting for a transistor, and prevention of device punchthrough.
摘要翻译：掺杂原子具有由于植入物损伤而变化的扩散系数。通过在形成栅电极之前将硅原子注入到硅衬底中来选择并产生损伤区域。硅原子用作吸收被捕获在硅衬底中的所选掺杂剂的吸气剂。掺杂剂被注入到受损区域附近，并通过热循环通过瞬态增强扩散（TED）扩散到受损区域以积累掺杂剂原子。瞬态增强扩散通过在相对低的退火温度下增强掺杂剂的扩散来改善衬底的掺杂。掺杂剂累积设置特定选择的电性能，而不会在邻近接点的区域中放置过量的掺杂剂，包括用于现场设备的阈值控制，晶体管的阈值设置以及防止器件穿透。

19. 发明授权

US5953626A Dissolvable dielectric method 失效
标题翻译：溶解介电法
公开(公告)号：US5953626A
公开(公告)日：1999-09-14
申请号：US659166
申请日：1996-06-05
申请人： Fred N. Hause , Basab Bandyopadhyay , Robert Dawson , H. Jim Fulford, Jr. , Mark W. Michael , William S. Brennan
发明人： Fred N. Hause , Basab Bandyopadhyay , Robert Dawson , H. Jim Fulford, Jr. , Mark W. Michael , William S. Brennan
IPC分类号： H01L21/768 , H01L21/4763
CPC分类号： H01L21/7682
摘要： A fabrication process that produces an air gap dielectric in which a multi-level interconnect structure is formed upon a temporary supporting material. The temporary material is subsequently dissolved away leaving behind an intralevel and an interlevel dielectric comprised of air. In one embodiment of the invention, a first interconnect level is formed on a barrier layer. A temporary support material is then formed over the first interconnect level and a second level of interconnect is formed on the temporary support material. Prior to formation of the second interconnect level, a plurality of pillar openings are formed in the temporary material and filled with a conductive material. In addition to providing a contact between the first and second level of interconnects, the pillars provide mechanical support for the second interconnect level. The temporary material is dissolved in a solution that attacks the temporary material but leaves the interconnect material and pillar material intact. In one embodiment of the invention, a passivation layer is formed on the second interconnect level prior to dissolving the temporary material. The air gap dielectric can be used with more than two levels of interconnect, if desired.
摘要翻译：一种制造气隙电介质的制造工艺，其中在临时支撑材料上形成多层互连结构。随后将临时材料溶解掉，留下由空气组成的层间和层间电介质。在本发明的一个实施例中，在阻挡层上形成第一互连电平。然后在第一互连层上形成临时支撑材料，并在临时支撑材料上形成第二层互连。在形成第二互连级别之前，在临时材料中形成多个柱状开口并填充有导电材料。除了在第一和第二级互连之间提供接触之外，支柱为第二互连电平提供机械支撑。临时材料溶解在攻击临时材料的溶液中，但使互连材料和支柱材料完好无损。在本发明的一个实施例中，在溶解临时材料之前，在第二互连层上形成钝化层。如果需要，气隙电介质可以与多于两个级别的互连一起使用。

20. 发明授权

US5930642A Transistor with buried insulative layer beneath the channel region 失效
标题翻译：晶体管与通道区域之下的埋入绝缘层
公开(公告)号：US5930642A
公开(公告)日：1999-07-27
申请号：US871468
申请日：1997-06-09
申请人： Bradley T. Moore , Robert Dawson , H. Jim Fulford, Jr. , Mark I. Gardner , Frederick N. Hause , Mark W. Michael , Derick J. Wristers
发明人： Bradley T. Moore , Robert Dawson , H. Jim Fulford, Jr. , Mark I. Gardner , Frederick N. Hause , Mark W. Michael , Derick J. Wristers
IPC分类号： H01L21/265 , H01L21/266 , H01L21/336 , H01L21/762 , H01L29/786 , H01L29/24
CPC分类号： H01L29/78696 , H01L21/26533 , H01L21/266 , H01L21/76243 , H01L29/6659 , H01L29/66772 , H01L29/78603 , H01L29/78654
摘要： A transistor with a buried insulative layer beneath a channel region is disclosed. Unlike conventional SIMOX, the buried insulative layer has a top surface beneath the channel region that is closer than bottom surfaces of the source and drain to the top surface of the substrate. Preferably, the buried insulative layer is formed by implanting oxygen into the substrate and then performing a high-temperature anneal so that the implanted oxygen reacts with silicon in the substrate to form a continuous stoichiometric layer of silicon dioxide. Advantageously, the buried insulative layer provides a diffusion barrier and an electrical isolation barrier for the channel region.
摘要翻译：公开了一种在沟道区下方具有埋入绝缘层的晶体管。与常规SIMOX不同，掩埋绝缘层在通道区域下方具有比源极和漏极的底表面更靠近衬底顶表面的顶表面。优选地，通过将氧注入到衬底中然后进行高温退火来形成掩埋绝缘层，使得注入的氧与衬底中的硅反应形成连续化学计量的二氧化硅层。有利地，掩埋绝缘层为通道区域提供扩散阻挡层和电隔离屏障。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式