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1. 发明授权

US6074904A Method and structure for isolating semiconductor devices after transistor formation 失效
标题翻译：在晶体管形成之后隔离半导体器件的方法和结构
公开(公告)号：US6074904A
公开(公告)日：2000-06-13
申请号：US63796
申请日：1998-04-21
申请人： Thomas E. Spikes, Jr. , Mark W. Michael , Mark I. Gardner , Robert Dawson
发明人： Thomas E. Spikes, Jr. , Mark W. Michael , Mark I. Gardner , Robert Dawson
IPC分类号： H01L21/762 , H01L21/8238
CPC分类号： H01L21/823878 , H01L21/76237
摘要： A method for isolating semiconductor devices comprising providing a semiconductor substrate. The semiconductor substrate includes a first pair of source/drain regions on either side of a first channel region and a second pair of source/drain regions on either side of a second channel region. One of the first pair of source/drain regions is proximal to one of the second pair of source/drain regions. First and second laterally displaced MOS transistors are formed partially within the semiconductor substrate. An isolation trench is formed through the proximal source/drain regions and the trench is filled with a trench dielectric material such that the proximal source/drain regions are electrically isolated whereby the first transistor is electrically isolated from the second transistor.
摘要翻译：一种用于隔离半导体器件的方法，包括提供半导体衬底。半导体衬底包括在第一沟道区的任一侧上的第一对源/漏区和在第二沟道区的任一侧上的第二对源极/漏极区。第一对源极/漏极区域中的一个靠近第二对源极/漏极区域中的一个。第一和第二横向位移的MOS晶体管部分地形成在半导体衬底内。通过近端源极/漏极区域形成隔离沟槽，并且沟槽填充有沟槽电介质材料，使得近端源极/漏极区域被电隔离，由此第一晶体管与第二晶体管电隔离。

2. 发明授权

US6111260A Method and apparatus for in situ anneal during ion implant 失效
标题翻译：离子注入过程中原位退火的方法和装置
公开(公告)号：US6111260A
公开(公告)日：2000-08-29
申请号：US872258
申请日：1997-06-10
申请人： Robert Dawson , H. Jim Fulford, Jr. , Mark I. Gardner , Frederick N. Hause , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
发明人： Robert Dawson , H. Jim Fulford, Jr. , Mark I. Gardner , Frederick N. Hause , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
IPC分类号： H01J37/317
CPC分类号： H01J37/3171 , H01J2237/316
摘要： During a semiconductor substrate ion implant process thermal energy is supplied to raise the temperature of the semiconductor wafer. The increased temperature of the semiconductor wafer during implantation acts to anneal the implanted impurities or dopants in the wafer, reducing impurity diffusion and reducing the number of fabrication process steps. An ion implant device includes an end station that is adapted for application and control of thermal energy to the end station for raising the temperature of a semiconductor substrate wafer during implantation. The adapted end station includes a heating element for heating the semiconductor substrate wafer, a thermocouple for sensing the temperature of the semiconductor substrate wafer, and a controller for monitoring the sensed temperature and controlling the thermal energy applied to the semiconductor substrate wafer by the heating element. An ion implant device including a system for applying and controlling thermal energy applied to a semiconductor substrate wafer during ion implantation raises the temperature of the wafer to a temperature that is sufficient to activate impurities within the semiconductor substrate wafer when an ion beam is implanting ions to the wafer, but the temperature is insufficient to activate impurities when the ion beam is inactive.
摘要翻译：在半导体衬底离子注入过程中，提供热能以提高半导体晶片的温度。在注入期间半导体晶片的温度升高期间用于退火晶片中注入的杂质或掺杂剂，减少杂质扩散并减少制造工艺步骤的数量。离子注入装置包括终端站，其适于向端站施加和控制热能，以在植入期间提高半导体衬底晶片的温度。适用的端站包括用于加热半导体衬底晶片的加热元件，用于感测半导体衬底晶片的温度的热电偶，以及用于监测感测温度并通过加热元件控制施加到半导体衬底晶片的热能的控制器。包括用于在离子注入期间施加和控制施加到半导体衬底晶片的热能的系统的离子注入装置将晶片的温度升高到当离子束注入离子时足以激活半导体衬底晶片内的杂质的温度晶片，但当离子束无效时，温度不足以激活杂质。

3. 发明授权

US6030752A Method of stitching segments defined by adjacent image patterns during the manufacture of a semiconductor device 失效
标题翻译：在制造半导体器件期间缝合由相邻图像图案定义的片段的方法
公开(公告)号：US6030752A
公开(公告)日：2000-02-29
申请号：US805534
申请日：1997-02-25
申请人： H. Jim Fulford, Jr. , Robert Dawson , Mark I. Gardner , Frederick N. Hause , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
发明人： H. Jim Fulford, Jr. , Robert Dawson , Mark I. Gardner , Frederick N. Hause , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
IPC分类号： G03F7/20
CPC分类号： G03F7/70475
摘要： A method of stitching segments defined by adjacent image patterns of a photolithographic system during the manufacture of a semiconductor device is disclosed. The method includes forming a material over a semiconductor substrate, projecting a first image pattern over the substrate that defines a first segment and a contact region, projecting a second image pattern over the substrate that defines a second segment with an end that overlaps the contact region, and removing a portion of the material corresponding to the first and second image patterns to form the first and second segments stitched by a portion of the contact region. The contact region has a greater width than the first and second segments. In this manner, the contact region accommodates misalignments that might otherwise lead to inadequate coupling or decoupling between the first and second segments. The invention is particularly well-suited for stitching polysilicon gates of N-channel and P-channel devices.
摘要翻译：公开了一种在制造半导体器件期间缝合由光刻系统的相邻图像图案限定的片段的方法。该方法包括在半导体衬底上形成材料，将限定第一部分和接触区域的第一图案图案投影在衬底上，将限定第二部分的第二图像图案投影在衬底上，端部与接触区域重叠以及去除对应于第一和第二图像图案的材料的一部分以形成由接触区域的一部分缝合的第一和第二段。接触区域具有比第一和第二段更大的宽度。以这种方式，接触区域适应可能导致第一和第二段之间不充分的耦合或解耦的未对准。本发明特别适用于拼接N沟道和P沟道器件的多晶硅栅极。

4. 发明授权

US5976956A Method of controlling dopant concentrations using transient-enhanced diffusion prior to gate formation in a device 失效
标题翻译：在器件中栅极形成之前使用瞬态增强扩散来控制掺杂剂浓度的方法
公开(公告)号：US5976956A
公开(公告)日：1999-11-02
申请号：US837936
申请日：1997-04-11
申请人： Mark I. Gardner , Derick J. Wristers , Robert Dawson , H. Jim Fulford, Jr. , Frederick N. Hause , Mark W. Michael , Bradley T. Moore
发明人： Mark I. Gardner , Derick J. Wristers , Robert Dawson , H. Jim Fulford, Jr. , Frederick N. Hause , Mark W. Michael , Bradley T. Moore
IPC分类号： H01L21/336 , H01L21/265 , H01L21/322 , H01L29/78
CPC分类号： H01L21/26506 , H01L21/3221 , Y10S148/024 , Y10S148/06
摘要： Dopant atoms have coefficients of diffusion that vary due to implant damage. Damaged regions are selected and created by implanting silicon atoms into a silicon substrate prior to formation of a gate electrode. The silicon atoms act as a getter for attracting selected dopants that are trapped in the silicon substrate. Dopants are implanted in the vicinity of the damaged regions and diffused by transient-enhanced diffusion (TED) into the damaged regions by thermal cycling to accumulate dopant atoms. Transient-enhanced diffusion improves the doping of a substrate by enhancing the diffusion of dopants at relatively low anneal temperatures. Dopant accumulation sets particular selected electrical properties without placing an excessive amount of dopant in regions adjacent to junctions for purposes including threshold control for a field device, threshold setting for a transistor, and prevention of device punchthrough.
摘要翻译：掺杂原子具有由于植入物损伤而变化的扩散系数。通过在形成栅电极之前将硅原子注入到硅衬底中来选择并产生损伤区域。硅原子用作吸收被捕获在硅衬底中的所选掺杂剂的吸气剂。掺杂剂被注入到受损区域附近，并通过热循环通过瞬态增强扩散（TED）扩散到受损区域以积累掺杂剂原子。瞬态增强扩散通过在相对低的退火温度下增强掺杂剂的扩散来改善衬底的掺杂。掺杂剂累积设置特定选择的电性能，而不会在邻近接点的区域中放置过量的掺杂剂，包括用于现场设备的阈值控制，晶体管的阈值设置以及防止器件穿透。

5. 发明授权

US5930642A Transistor with buried insulative layer beneath the channel region 失效
标题翻译：晶体管与通道区域之下的埋入绝缘层
公开(公告)号：US5930642A
公开(公告)日：1999-07-27
申请号：US871468
申请日：1997-06-09
申请人： Bradley T. Moore , Robert Dawson , H. Jim Fulford, Jr. , Mark I. Gardner , Frederick N. Hause , Mark W. Michael , Derick J. Wristers
发明人： Bradley T. Moore , Robert Dawson , H. Jim Fulford, Jr. , Mark I. Gardner , Frederick N. Hause , Mark W. Michael , Derick J. Wristers
IPC分类号： H01L21/265 , H01L21/266 , H01L21/336 , H01L21/762 , H01L29/786 , H01L29/24
CPC分类号： H01L29/78696 , H01L21/26533 , H01L21/266 , H01L21/76243 , H01L29/6659 , H01L29/66772 , H01L29/78603 , H01L29/78654
摘要： A transistor with a buried insulative layer beneath a channel region is disclosed. Unlike conventional SIMOX, the buried insulative layer has a top surface beneath the channel region that is closer than bottom surfaces of the source and drain to the top surface of the substrate. Preferably, the buried insulative layer is formed by implanting oxygen into the substrate and then performing a high-temperature anneal so that the implanted oxygen reacts with silicon in the substrate to form a continuous stoichiometric layer of silicon dioxide. Advantageously, the buried insulative layer provides a diffusion barrier and an electrical isolation barrier for the channel region.
摘要翻译：公开了一种在沟道区下方具有埋入绝缘层的晶体管。与常规SIMOX不同，掩埋绝缘层在通道区域下方具有比源极和漏极的底表面更靠近衬底顶表面的顶表面。优选地，通过将氧注入到衬底中然后进行高温退火来形成掩埋绝缘层，使得注入的氧与衬底中的硅反应形成连续化学计量的二氧化硅层。有利地，掩埋绝缘层为通道区域提供扩散阻挡层和电隔离屏障。

6. 发明授权

US5899732A Method of implanting silicon through a polysilicon gate for punchthrough control of a semiconductor device 失效
标题翻译：通过多晶硅栅极注入硅的方法，用于半导体器件的穿通控制
公开(公告)号：US5899732A
公开(公告)日：1999-05-04
申请号：US837937
申请日：1997-04-11
申请人： Mark I. Gardner , Derick J. Wristers , Robert Dawson , H. Jim Fulford, Jr. , Frederick N. Hause , Mark W. Michael , Bradley T. Moore
发明人： Mark I. Gardner , Derick J. Wristers , Robert Dawson , H. Jim Fulford, Jr. , Frederick N. Hause , Mark W. Michael , Bradley T. Moore
IPC分类号： H01L21/225 , H01L21/265 , H01L21/322 , H01L21/336 , H01L21/8238 , H01L29/10
CPC分类号： H01L29/66492 , H01L21/2253 , H01L21/26506 , H01L21/26513 , H01L21/3221 , H01L21/8238 , H01L29/1083 , H01L29/6659
摘要： A region of damaged silicon is exploited as a gettering region for gettering impurities in a silicon substrate. The region of damaged silicon is formed between source and drain regions of a device by implanting silicon atoms into the silicon substrate after the formation of a gate electrode of the device. The damaged region is subsequently annealed and, during the annealing process, dopant atoms such as boron segregate to the region, locally increasing the dopant concentration in the region. The previously damaged region is in a location that determine the punchthrough characteristics of the device. The silicon implant for creating a gettering effect is performed after gate formation so that the region immediately beneath the junction is maintained at a lower dopant concentration to reduce junction capacitance. Silicon is implanted in the vicinity of a polysilicon gate to induce transient-enhanced diffusion (TED) of dopant atoms such as boron or phosphorus for control of punchthrough characteristics of a device. A punchthrough control implant is performed following formation of gate electrodes on a substrate using a self-aligned gettering implant.
摘要翻译：受损硅的区域被用作吸杂硅衬底中的杂质的吸杂区域。损坏的硅的区域在器件的栅极电极形成之后通过将硅原子注入到硅衬底中而在器件的源极和漏极区域之间形成。受损区域随后退火，并且在退火过程期间，诸如硼的掺杂剂原子偏析到该区域，局部地增加该区域中的掺杂剂浓度。先前损坏的区域位于确定设备穿透特性的位置。用于产生吸杂效应的硅植入物在栅极形成之后进行，使得紧邻在结点处的区域保持在较低掺杂剂浓度以减小结电容。将硅注入到多晶硅栅极附近以引发诸如硼或磷的掺杂剂原子的瞬态增强扩散（TED），以控制器件的穿透特性。在使用自对准吸气植入物在衬底上形成栅电极之后执行穿通控制植入。

7. 发明授权

US5888675A Reticle that compensates for radiation-induced lens error in a photolithographic system 失效
标题翻译：补偿光刻系统中辐射诱发的透镜误差的光罩
公开(公告)号：US5888675A
公开(公告)日：1999-03-30
申请号：US760031
申请日：1996-12-04
申请人： Bradley T. Moore , Robert Dawson , H. Jim Fulford, Jr. , Mark I. Gardner , Frederick N. Hause , Mark W. Michael , Derick J. Wristers
发明人： Bradley T. Moore , Robert Dawson , H. Jim Fulford, Jr. , Mark I. Gardner , Frederick N. Hause , Mark W. Michael , Derick J. Wristers
IPC分类号： G03F1/00 , G03F7/20 , H01L21/027 , G03F9/00 , G03C5/00
CPC分类号： G03F7/70433 , G03F1/70 , G03F7/70241
摘要： A reticle provides an image pattern and compensates for a lens error in a photolithographic system. The reticle is structurally modified using image displacement data indicative of the lens error. The reticle can be structurally modified by adjusting the configuration (or layout) of radiation-transmitting regions, for instance by adjusting a chrome pattern on the top surface of a quartz base. Alternatively, the reticle can be structurally modified by adjusting the curvature of the reticle, for instance by providing a chrome pattern on the top surface of a quartz base and grinding away portions of the bottom surface of the quartz base. The image displacement data may also vary as a function of lens heating so that the reticle compensates for lens heating associated with the reticle pattern.
摘要翻译：掩模版提供图像图案并补偿光刻系统中的透镜误差。使用指示透镜误差的图像位移数据对结构上的掩模版进行修改。可以通过调节辐射透射区域的构造（或布局）来结构地修改掩模版，例如通过调节石英基底的顶表面上的铬图案。或者，可以通过调整掩模版的曲率来结构地修改掩模版，例如通过在石英基底的顶表面上提供铬图案并研磨掉石英基底的底表面的部分。图像位移数据也可以根据透镜加热而变化，使得掩模版补偿与标线图案相关联的透镜加热。

8. 发明授权

US5885877A Composite gate electrode incorporating dopant diffusion-retarding barrier layer adjacent to underlying gate dielectric 失效
标题翻译：复合栅电极，其与掺杂剂扩散阻滞层结合，邻近底层栅极电介质
公开(公告)号：US5885877A
公开(公告)日：1999-03-23
申请号：US837581
申请日：1997-04-21
申请人： Mark I. Gardner , Robert Dawson , H. Jim Fulford, Jr. , Frederick N. Hause , Daniel Kadosh , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
发明人： Mark I. Gardner , Robert Dawson , H. Jim Fulford, Jr. , Frederick N. Hause , Daniel Kadosh , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
IPC分类号： H01L21/28 , H01L29/49 , H01L21/336 , H01L21/3205
CPC分类号： H01L21/28035 , H01L29/4916
摘要： A composite gate electrode layer incorporates a diffusion-retarding barrier layer disposed at the bottom of the gate electrode layer to reduce the amount of dopant which diffuses into the gate dielectric layer from the gate electrode layer. A lower nitrogen-containing gate electrode layer provides a diffusion-retarding barrier layer against dopant diffusion into the gate dielectric layer disposed therebelow, and an upper gate electrode layer is formed upon the lower layer and is doped to form a highly conductive layer. Together the first and second gate electrode layers form a composite gate electrode layer which incorporates a diffusion-retarding barrier layer adjacent to the underlying gate dielectric layer. The barrier layer may be formed by annealing a first polysilicon layer in a nitrogen-containing ambient, such as N.sub.2, NO, N.sub.2 O, and NH.sub.3, by implanting a nitrogen-containing material, such as elemental or molecular nitrogen, into a first polysilicon layer, and by in-situ depositing a nitrogen-doped first polysilicon layer. Diffusion of dopants into the gate dielectric layer may be retarded, as most dopant atoms are prevented from diffusing from the composite gate electrode layer at all. In addition, the nitrogen concentration within the gate dielectric layer, particularly at or near the substrate interface, may be maintained at lower concentrations than otherwise necessary to prevent dopant diffusion into the underlying substrate. The present invention is particularly well suited to thin gate dielectrics, such as a those having a thickness less than approximately 60 .ANG. when using a p-type dopant, such as boron.
摘要翻译：复合栅极电极层包括设置在栅极电极层底部的扩散阻挡层，以减少从栅极电极层扩散到栅极电介质层中的掺杂剂的量。下部含氮栅电极层提供阻止扩散阻挡层，以阻止掺杂剂扩散到设置在其下方的栅介质层中，并且在下层上形成上栅极电极层，并且被掺杂以形成高导电层。第一和第二栅极电极层一起形成复合栅极电极层，该复合栅极电极层包含与下面的栅极电介质层相邻的扩散阻滞阻挡层。通过将含氮材料（例如元素或分子氮）注入到第一多晶硅层中，可以通过在氮气环境如N 2，NO，N 2 O和NH 3中退火第一多晶硅层来形成阻挡层，并通过原位沉积氮掺杂的第一多晶硅层。完全可以防止掺杂剂扩散到栅极电介质层中，因为大多数掺杂剂原子被阻止从复合栅极电极层扩散。此外，栅极电介质层内，特别是在衬底界面处或附近的氮浓度可以保持在比防止掺杂剂扩散到下面的衬底中所必需的更低的浓度。本发明特别适用于薄栅电介质，例如当使用诸如硼的p型掺杂剂时厚度小于约60的薄电介质。

9. 发明授权

US06552776B1 Photolithographic system including light filter that compensates for lens error 有权
标题翻译：光刻系统包括补偿透镜误差的滤光片
公开(公告)号：US06552776B1
公开(公告)日：2003-04-22
申请号：US09183176
申请日：1998-10-30
申请人： Derick J. Wristers , Robert Dawson , H. Jim Fulford, Jr. , Mark I. Gardner , Frederick N. Hause , Bradley T. Moore , Mark W. Michael
发明人： Derick J. Wristers , Robert Dawson , H. Jim Fulford, Jr. , Mark I. Gardner , Frederick N. Hause , Bradley T. Moore , Mark W. Michael
IPC分类号： G03B2754
CPC分类号： G03F7/70558 , G03F7/70191 , G03F7/706
摘要： A photolithographic system including a light filter that varies light intensity according to measured dimensional data that characterizes a lens error is disclosed. The light filter compensates for the lens error by reducing the light intensity of the image pattern as the lens error increases. In this manner, when the lens error causes focusing variations that result in enlarged portions of the image pattern, the light filter reduces the light intensity transmitted to the enlarged portions of the image pattern. This, in turn, reduces the rate in which regions of the photoresist layer beneath the enlarged portions of the image pattern are rendered soluble to a subsequent developer. As a result, after the photoresist layer is developed, linewidth variations that otherwise result from the lens error are reduced due to the light filter. Preferably, the light filter includes a light-absorbing film such as a semi-transparent layer such as calcium fluoride on a light-transmitting base such as a quartz plate, and the thickness of the light-absorbing film varies in accordance with the measured dimensional data to provide the desired variations in light intensity. The invention is particularly well-suited for patterning a photoresist layer that defines polysilicon gates of an integrated circuit device.
摘要翻译：公开了一种光刻系统，其包括根据测量的尺寸数据来表征透镜误差来改变光强度的滤光器。光滤波器通过降低镜头误差增大时图像图案的光强度来补偿镜头误差。以这种方式，当透镜错误导致导致图像图案的放大部分的聚焦变化时，光过滤器降低传输到图像图案的扩大部分的光强度。这又降低了图像图案的放大部分之下的光致抗蚀剂层的区域变得可溶于后续显影剂的速率。结果，在光致抗蚀剂层显影之后，由于滤光器而导致透镜误差导致的线宽变化会降低。优选地，光滤波器包括诸如石英板等透光基底上的诸如氟化钙的半透明层的光吸收膜，并且光吸收膜的厚度根据测量的尺寸而变化数据以提供所需的光强度变化。本发明特别适用于图案化限定集成电路器件的多晶硅栅极的光致抗蚀剂层。

10. 发明授权

US6060345A Method of making NMOS and PMOS devices with reduced masking steps 失效
标题翻译：制造具有减少掩蔽步骤的NMOS和PMOS器件的方法
公开(公告)号：US6060345A
公开(公告)日：2000-05-09
申请号：US844924
申请日：1997-04-21
申请人： Frederick N. Hause , Robert Dawson , H. Jim Fulford, Jr. , Mark I. Gardner , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
发明人： Frederick N. Hause , Robert Dawson , H. Jim Fulford, Jr. , Mark I. Gardner , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
IPC分类号： H01L21/8238 , H01L27/092
CPC分类号： H01L21/823814
摘要： A method of making NMOS and PMOS devices with reduced masking steps is disclosed. The method includes providing a semiconductor substrate with a first active region of first conductivity type and a second active region of second conductivity type, forming a gate material over the first and second active regions, forming a first masking layer over the gate material, etching the gate material using the first masking layer as an etch mask to form a first gate over the first active region and a second gate over the second active region, implanting a dopant of second conductivity type into the first and second active regions using the first masking layer as an implant mask, forming a second masking layer that covers the first active region and includes an opening above the second active region, and implanting a dopant of first conductivity type into the second active region using the first and second masking layers as an implant mask. Advantageously, the dopant of first conductivity type counterdopes the dopant of second conductivity type in the second active region, thereby providing source and drain regions of second conductivity type in the first active region and source and drain regions of first conductivity type in the second active region with a single masking step and without subjecting either gate to dopants of first and second conductivity type.
摘要翻译：公开了一种制造具有减小的掩蔽步骤的NMOS和PMOS器件的方法。该方法包括提供具有第一导电类型的第一有源区和第二导电类型的第二有源区的半导体衬底，在第一和第二有源区上形成栅极材料，在栅极材料上形成第一掩模层，栅极材料，使用第一掩模层作为蚀刻掩模，以在第一有源区上形成第一栅极，在第二有源区上形成第二栅极，使用第一掩模层将第二导电类型的掺杂剂注入到第一和第二有源区中作为注入掩模，形成覆盖第一有源区并且包括在第二有源区上方的开口的第二掩模层，以及使用第一和第二掩模层作为注入掩模将第一导电类型的掺杂剂注入到第二有源区中。有利地，第一导电类型的掺杂剂在第二有源区域中抵消第二导电类型的掺杂剂，从而在第一有源区域中提供第二导电类型的源极和漏极区域，并且在第二有源区域中提供第一导电类型的源极和漏极区域具有单个掩蔽步骤，并且不对任一个栅极施加第一和第二导电类型的掺杂剂。

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