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11. 发明授权

US06737222B2 Dual damascene process utilizing a bi-layer imaging layer 有权
标题翻译：双镶嵌工艺利用双层成像层
公开(公告)号：US06737222B2
公开(公告)日：2004-05-18
申请号：US09884834
申请日：2001-06-19
申请人： Ramkumar Subramanian , Christopher F. Lyons , Marina V. Plat , Scott A. Bell
发明人： Ramkumar Subramanian , Christopher F. Lyons , Marina V. Plat , Scott A. Bell
IPC分类号： G03F700
CPC分类号： H01L21/76829 , G03F7/0035 , G03F7/095 , H01L21/0274 , H01L21/31144 , H01L21/76801 , H01L21/76802 , H01L21/76808 , H01L2221/1031
摘要： A method of utilizing a multilayer photoresist to form contact holes and/or conductors utilizing a dual damascene process includes utilizing layered photoresists. A contact in a conductive line can be formed in a single deposition step or in a two-stage deposition step. Image layers can remain as part of the interconnect structure or be removed by a polishing technique. The process can be utilized for any conductive structures provided above a substrate of an integrated circuit.
摘要翻译：利用多层光刻胶形成接触孔和/或使用双镶嵌工艺的导体的方法包括利用层状光致抗蚀剂。可以在单个沉积步骤中或在两级沉积步骤中形成导电线中的接触。图像层可以保留为互连结构的一部分，或者通过抛光技术去除。该方法可用于设置在集成电路的衬底上的任何导电结构。

12. 发明授权

US06534418B1 Use of silicon containing imaging layer to define sub-resolution gate structures 有权
标题翻译：使用含硅成像层来定义次分辨率门结构
公开(公告)号：US06534418B1
公开(公告)日：2003-03-18
申请号：US09845656
申请日：2001-04-30
申请人： Marina V. Plat , Scott A. Bell , Christopher F. Lyons , Ramkumar Subramanian , Bhanwar Singh
发明人： Marina V. Plat , Scott A. Bell , Christopher F. Lyons , Ramkumar Subramanian , Bhanwar Singh
IPC分类号： H01L21302
CPC分类号： H01L21/0338 , H01L21/0337 , H01L21/28123 , H01L29/6659 , H01L29/7833
摘要： An exemplary method of using silicon containing imaging layers to define sub-resolution gate structures can include depositing an anti-reflective coating over a layer of polysilicon, depositing an imaging layer over the anti-reflective coating, selectively etching the anti-reflective coating to form a pattern, and removing portions of the polysilicon layer using the pattern formed from the removed portions of anti-reflective coating. Thus, the use of thin imaging layer, that has high etch selectivity to the organic underlayer, allows the use of trim etch techniques without a risk of resist erosion or aspect ratio pattern collapse. That, in turn, allows for the formation of the gate pattern with widths less than the widths of the pattern of the imaging layer.
摘要翻译：使用含硅成像层来限定次分辨率门结构的示例性方法可以包括在多晶硅层上沉积抗反射涂层，在抗反射涂层上沉积成像层，选择性地蚀刻抗反射涂层以形成使用由抗反射涂层的去除部分形成的图案去除多晶硅层的部分。因此，对有机底层具有高蚀刻选择性的薄成像层的使用允许使用修剪蚀刻技术，而不会有抗蚀剂侵蚀或高宽比图案崩溃的风险。这又反过来允许形成具有小于成像层的图案的宽度的宽度的栅极图案。

13. 发明授权

US07052921B1 System and method using in situ scatterometry to detect photoresist pattern integrity during the photolithography process 有权
标题翻译：使用原位散射法在光刻过程中检测光致抗蚀剂图案完整性的系统和方法
公开(公告)号：US07052921B1
公开(公告)日：2006-05-30
申请号：US10934192
申请日：2004-09-03
申请人： Marina V. Plat , Bhanwar Singh , Calvin T. Gabriel , Christopher F. Lyons , Scott A. Bell , Ramkumar Subramanian , Srikanteswara Dakshina-Murthy
发明人： Marina V. Plat , Bhanwar Singh , Calvin T. Gabriel , Christopher F. Lyons , Scott A. Bell , Ramkumar Subramanian , Srikanteswara Dakshina-Murthy
IPC分类号： H01L21/66
CPC分类号： G03F7/70625 , G03F7/70608 , H01L22/12
摘要： The present invention uses in situ scatterometry to determine if a defect (e.g., photoresist erosion, photoresist bending and pattern collapse) is present on a wafer. In one embodiment, in situ scatterometry is used to detect a pattern integrity defect associated with the layer of photoresist. In situ scatterometry produces diffraction data associated with the thickness of the photoresist patterned mask. This data is compared to a model of diffraction data associated with a suitable photoresist thickness. If the measured diffraction data is within an acceptable range, the next step of the photolithography process is carried out. However, if the measured thickness is outside of the suitable range, a defect is detected, and the wafer may be sent for re-working or re-patterned prior to main etch, thereby preventing unnecessary wafer scrap. Another aspect of the present invention allows for a feedback control mechanism to alter a physical parameter of the photolithographic process based upon the in situ scatterometry measurements.
摘要翻译：本发明使用原位散射法来确定晶片上是否存在缺陷（例如，光致抗蚀剂侵蚀，光致抗蚀剂弯曲和图案崩溃）。在一个实施例中，原位散射法用于检测与光致抗蚀剂层相关联的图案完整性缺陷。原位散射法产生与光致抗蚀剂图案掩模的厚度相关的衍射数据。将该数据与与合适的光致抗蚀剂厚度相关联的衍射数据的模型进行比较。如果测量的衍射数据在可接受的范围内，则进行光刻工艺的下一步骤。然而，如果测量的厚度在合适的范围之外，则检测到缺陷，并且可以在主蚀刻之前将晶片发送用于再加工或重新图案化，从而防止不必要的晶片废料。本发明的另一方面允许反馈控制机制基于原位散射测量来改变光刻工艺的物理参数。

14. 发明授权

US06541360B1 Bi-layer trim etch process to form integrated circuit gate structures 有权
标题翻译：双层微调蚀刻工艺形成集成电路门结构
公开(公告)号：US06541360B1
公开(公告)日：2003-04-01
申请号：US09845649
申请日：2001-04-30
申请人： Marina V. Plat , Scott A. Bell , Christopher F. Lyons , Ramkumar Subramanian , Bhanwar Singh
发明人： Marina V. Plat , Scott A. Bell , Christopher F. Lyons , Ramkumar Subramanian , Bhanwar Singh
IPC分类号： H01L213205
CPC分类号： H01L21/0338 , H01L21/0271 , H01L21/0337 , H01L21/32139 , Y10S438/947 , Y10S438/952
摘要： A bi-layer trim etch process to form integrated circuit gate structures can include depositing an organic underlayer over a layer of polysilicon, depositing an imaging layer over the organic underlayer, patterning the imaging layer, selectively trim etching the organic underlayer to form a pattern, and removing portions of the polysilicon layer using the pattern formed from the removed portions of organic underlayer. Thus, the use of thin imaging layer, that has high etch selectivity to the organic underlayer, allows the use of trim etch techniques without a risk of resist erosion or the aspect ratio pattern collapse. That, in turn, allows for the formation of the gate pattern with widths less than the widths of the pattern of the imaging layer.
摘要翻译：用于形成集成电路栅极结构的双层修剪蚀刻工艺可以包括在多晶硅层上沉积有机底层，在有机底层上沉积成像层，图案化成像层，选择性地修整蚀刻有机底层以形成图案，以及使用由有机底层的去除部分形成的图案去除多晶硅层的部分。因此，对有机底层具有高蚀刻选择性的薄成像层的使用允许使用微调蚀刻技术，而不会有抗蚀剂侵蚀或长宽比图案崩溃的风险。这又反过来允许形成具有小于成像层的图案的宽度的宽度的栅极图案。

15. 发明授权

US06383952B1 RELACS process to double the frequency or pitch of small feature formation 失效
标题翻译： RELACS过程将小特征形成的频率或间距加倍
公开(公告)号：US06383952B1
公开(公告)日：2002-05-07
申请号：US09794632
申请日：2001-02-28
申请人： Ramkumar Subramanian , Bhanwar Singh , Marina V. Plat , Christopher F. Lyons , Scott A. Bell
发明人： Ramkumar Subramanian , Bhanwar Singh , Marina V. Plat , Christopher F. Lyons , Scott A. Bell
IPC分类号： H01L2131
CPC分类号： H01L21/0271 , H01L21/0273 , H01L21/0332 , H01L21/0337 , H01L21/0338
摘要： A method of doubling the frequency of small pattern formation. The method includes forming a photoresist layer, and then patterning it. A RELACS polymer is spread over the patterned photoresist layer. Portions of the RELACS polymer on top portions of each patterned photoresist region are removed, by either etching or by polishing them off. Portions between each patterned photoresist region are also removed in this step. The patterned photoresist regions are removed, preferably by a flood exposure and then application of a developer to the exposed photoresist regions. The remaining RELACS polymer regions, which were disposed against respective sidewalls of the patterned photoresist regions, prior to their removal, are then used for forming small pattern regions to be used in a semiconductor device to be formed on the substrate. These small pattern regions can be used to form separate poly-gates.
摘要翻译：一种将图案形成加倍的方法。该方法包括形成光致抗蚀剂层，然后对其进行图案化。 RELACS聚合物分散在图案化的光致抗蚀剂层上。通过蚀刻或通过抛光，去除每个图案化的光致抗蚀剂区域的顶部上的部分RELACS聚合物。在该步骤中也去除了每个图案化的光致抗蚀剂区域之间的部分。去除图案化的光致抗蚀剂区域，优选通过暴露曝光，然后将显影剂施加到曝光的光致抗蚀剂区域。然后将其去除之前设置在图案化光致抗蚀剂区域的相应侧壁上的剩余RELACS聚合物区域用于形成待用于形成在衬底上的半导体器件中的小图案区域。这些小图案区域可用于形成单独的多门。

16. 发明授权

US07008832B1 Damascene process for a T-shaped gate electrode 失效
标题翻译：用于T形栅电极的镶嵌工艺
公开(公告)号：US07008832B1
公开(公告)日：2006-03-07
申请号：US09900986
申请日：2001-07-09
申请人： Ramkumar Subramanian , Christopher F. Lyons , Marina V. Plat , Bhanwar Singh
发明人： Ramkumar Subramanian , Christopher F. Lyons , Marina V. Plat , Bhanwar Singh
IPC分类号： H01L21/338
CPC分类号： H01L21/28114 , H01L21/28123 , H01L29/42376 , H01L29/517
摘要： A damascene process can be utilized to form a T-shaped gate. A silicon rich nitride or SiON layer can be etched to form a first aperture. An oxide layer can be provided above the silicon rich nitride layer or SiON layer. A second aperture or trench can be provided in the oxide layer. The second trench can have a larger width than the trench in the silicon rich nitride layer or SiON layer. A gate conductor material, such as polysilicon, can be provided in the first trench and/or the second trench.
摘要翻译：可以使用镶嵌工艺来形成T形门。可以蚀刻富硅氮化物或SiON层以形成第一孔。可以在富硅的氮化物层或SiON层的上方设置氧化物层。可以在氧化物层中提供第二孔或沟槽。第二沟槽可以具有比富硅的氮化物层或SiON层中的沟槽更大的宽度。诸如多晶硅的栅极导体材料可以设置在第一沟槽和/或第二沟槽中。

17. 发明授权

US06589711B1 Dual inlaid process using a bilayer resist 有权
标题翻译：使用双层抗蚀剂的双镶嵌工艺
公开(公告)号：US06589711B1
公开(公告)日：2003-07-08
申请号：US09824696
申请日：2001-04-04
申请人： Ramkumar Subramanian , Christopher F. Lyons , Marina V. Plat , Bhanwar Singh
发明人： Ramkumar Subramanian , Christopher F. Lyons , Marina V. Plat , Bhanwar Singh
IPC分类号： H01L214763
CPC分类号： H01L21/76808
摘要： There is provided a method of making a dual inlaid via in a first layer. The first layer may be a polymer intermetal dielectric, such as HSQ, of a semiconductor device. The method includes forming a first opening, such as a via, in the first layer and forming a bilayer resist in the first opening. The bilayer resist includes an imaging layer above a bottom antireflective coating (BARC). The imaging layer is selectively exposed to radiation such that no radiation reaches the lower section of the BARC in the first opening through the upper section of the BARC. The bilayer resist is pattered, and a second opening, such as a trench, is formed in communication with the first opening using the patterned bilayer resist as a mask.
摘要翻译：提供了在第一层中制作双重嵌入通孔的方法。第一层可以是半导体器件的聚合物金属间电介质，例如HSQ。该方法包括在第一层中形成诸如通孔的第一开口，并在第一开口中形成双层抗蚀剂。双层抗蚀剂包括底部抗反射涂层（BARC）上方的成像层。成像层选择性地暴露于辐射，使得在通过BARC的上部的第一开口中没有辐射到达BARC的下部。双层抗蚀剂被图案化，并且使用图案化双层抗蚀剂作为掩模，形成与第一开口连通的第二开口，例如沟槽。

18. 发明授权

US06605546B1 Dual bake for BARC fill without voids 失效
标题翻译：双烘烤BARC填充无空隙
公开(公告)号：US06605546B1
公开(公告)日：2003-08-12
申请号：US09901699
申请日：2001-07-11
申请人： Ramkumar Subramanian , Wolfram Grundke , Bhanwar Singh , Christopher F. Lyons , Marina V. Plat
发明人： Ramkumar Subramanian , Wolfram Grundke , Bhanwar Singh , Christopher F. Lyons , Marina V. Plat
IPC分类号： H01L21302
CPC分类号： H01L21/76808
摘要： A method for forming a semiconductor device comprises forming a first layer over a semiconductor substrate. At least one hole is formed through the first layer. A bottom anti-reflective coating (BARC) layer is formed in the at least one hole. A first heating is performed to heat the BARC layer to a flow temperature. A second heating is performed to heat the BARC layer to a hardening temperature so that the BARC layer hardens, wherein the hardening temperature is greater than the flow temperature. An etch is performed to form a trench in the first layer and over the at least one hole, wherein the hardened BARC layer in the at least one hole acts as an etch resistant layer during the etch. As an alternative to the second heating step, the BARC may be simply hardened. The first and second heating may be performed within a heating chamber without removing the semiconductor substrate.
摘要翻译：一种用于形成半导体器件的方法包括在半导体衬底上形成第一层。通过第一层形成至少一个孔。在至少一个孔中形成底部抗反射涂层（BARC）层。执行第一次加热以将BARC层加热至流动温度。执行第二次加热以将BARC层加热至硬化温度，使得BARC层硬化，其中硬化温度大于流动温度。进行蚀刻以在第一层中和在至少一个孔上形成沟槽，其中至少一个孔中的硬化的BARC层在蚀刻期间用作耐蚀刻层。作为第二加热步骤的替代方案，BARC可以简单地硬化。第一和第二加热可以在加热室内进行，而不去除半导体衬底。

19. 发明授权

US06458691B1 Dual inlaid process using an imaging layer to protect via from poisoning 有权
标题翻译：双镶嵌工艺使用成像层保护通孔免受中毒
公开(公告)号：US06458691B1
公开(公告)日：2002-10-01
申请号：US09824662
申请日：2001-04-04
申请人： Ramkumar Subramanian , Christopher F. Lyons , Marina V. Plat , Bhanwar Singh
发明人： Ramkumar Subramanian , Christopher F. Lyons , Marina V. Plat , Bhanwar Singh
IPC分类号： H01L214763
CPC分类号： H01L21/31144 , H01L21/76807
摘要： There is provided a method of making a dual inlaid via in a first layer. The first layer may be a polymer intermetal dielectric, such as HSQ, of a semiconductor device. The method includes forming a first opening, such as a via, in the first layer and forming an inorganic base radiation sensitive layer in the first opening. The radiation sensitive layer may be a polysilane imaging layer. The inorganic base radiation sensitive layer is selectively exposed to radiation and then patterned. A second opening, such a trench, is formed in communication with the first opening using the patterned inorganic base radiation sensitive layer as a mask. A conductive layer may be formed in the dual inlaid via to complete a dual damascene process.
摘要翻译：提供了在第一层中制作双重嵌入通孔的方法。第一层可以是半导体器件的聚合物金属间电介质，例如HSQ。该方法包括在第一层中形成诸如通孔的第一开口，并在第一开口中形成无机碱辐射敏感层。辐射敏感层可以是聚硅烷成像层。无机碱辐射敏感层选择性地暴露于辐射，然后图案化。使用图案化的无机基底辐射敏感层作为掩模，形成与第一开口连通的第二开口，这样的沟槽。可以在双镶嵌通孔中形成导电层以完成双镶嵌工艺。

20. 发明授权

US07018922B1 Patterning for elongated VSS contact flash memory 有权
标题翻译：扩展VSS接触闪存的图案化
公开(公告)号：US07018922B1
公开(公告)日：2006-03-28
申请号：US10968713
申请日：2004-10-19
申请人： Hung-eil Kim , Anna Minvielle , Christopher F. Lyons , Marina V. Plat , Ramkumar Subramanian
发明人： Hung-eil Kim , Anna Minvielle , Christopher F. Lyons , Marina V. Plat , Ramkumar Subramanian
IPC分类号： H01L21/4763
CPC分类号： H01L27/11521 , H01L21/76802 , H01L27/115
摘要： A method of forming a contact in a flash memory device is disclosed. The method increases the depth of focus margin and the overlay margin between the contact and the stacked gate layers. A plurality of stacked gate layers are formed on a semiconductor substrate, wherein each stacked gate layer extends in a predefined direction and is substantially parallel to other stacked gate layers. An interlayer insulating layer is deposited over the plurality of stacked gate layers, and a contact hole is patterned between a first stacked gate layer of the plurality of stacked gate layers and a second stacked gate layer of the plurality of stacked gate layers. The contact hole is formed in an elongated shape, wherein a major axis of the contact hole is substantially parallel to the stacked gate layers. A conductive layer is deposited in the contact hole and excess conductive material is removed.
摘要翻译：公开了一种在闪速存储器件中形成触点的方法。该方法增加了接触和层叠栅极层之间的焦距裕度和覆盖边缘的深度。在半导体衬底上形成多个层叠的栅极层，其中每个堆叠的栅极层沿预定的方向延伸并且基本上平行于其它堆叠的栅极层。层叠绝缘层沉积在多个堆叠的栅极层上，并且在多个堆叠的栅极层的第一堆叠的栅极层和多个堆叠的栅极层的第二叠层栅极层之间形成接触孔。接触孔形成为细长形状，其中接触孔的长轴基本上平行于堆叠的栅极层。导电层沉积在接触孔中，去除过量的导电材料。

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