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1. 发明授权

US06660645B1 Process for etching an organic dielectric using a silyated photoresist mask 有权
标题翻译：使用硅化光致抗蚀剂掩模蚀刻有机电介质的方法
公开(公告)号：US06660645B1
公开(公告)日：2003-12-09
申请号：US10051725
申请日：2002-01-17
申请人： Scott A. Bell , Todd P. Lukanc , Christopher F. Lyons , Marina V. Plat , Ramkumar Subramanian
发明人： Scott A. Bell , Todd P. Lukanc , Christopher F. Lyons , Marina V. Plat , Ramkumar Subramanian
IPC分类号： H07L21302
CPC分类号： H01L21/31144
摘要： A process for forming a semiconductor device may comprise forming an organic dielectric layer on a substrate, forming a protective layer on the organic dielectric layer, forming a photoresist mask on the protective layer, and silyating the photoresist mask. The protective layer is etched using the silyated photoresist mask as an etch mask, and then the organic dielectric layer is etched using the silyated photoresist mask as an etch mask. Metal may be deposited in a void etched in the organic dielectric layer to form a wiring, contact or via.
摘要翻译：用于形成半导体器件的工艺可以包括在衬底上形成有机电介质层，在有机介电层上形成保护层，在保护层上形成光致抗蚀剂掩模，并使光刻胶掩模进行硅化。使用硅化光致抗蚀剂掩模作为蚀刻掩模蚀刻保护层，然后使用硅化光致抗蚀剂掩模作为蚀刻掩模蚀刻有机介电层。金属可以沉积在蚀刻在有机介电层中的空隙中以形成布线，接触或通孔。

2. 发明授权

US06689541B1 Process for forming a photoresist mask 有权
标题翻译：光刻胶掩模形成工艺
公开(公告)号：US06689541B1
公开(公告)日：2004-02-10
申请号：US09884182
申请日：2001-06-19
申请人： Scott A. Bell , Todd P. Lukanc , Christopher F. Lyons , Marina V. Plat , Ramkumar Subramanian
发明人： Scott A. Bell , Todd P. Lukanc , Christopher F. Lyons , Marina V. Plat , Ramkumar Subramanian
IPC分类号： G03C500
CPC分类号： G03F7/38 , G03F7/265 , G03F7/40
摘要： In a process for forming a photoresist mask, a photoresist layer is applied to a substrate. A silyated layer is formed in the photoresist layer. The features of the silyated area correspond to the features of a photoresist mask to be formed. The photoresist layer is then etched to form a photoresist base beneath the silyated area. The photoresist base is etched to remove material from its sides such that it becomes narrower than the silyated area. The silyated area is then removed, leaving a photoresist mask on the substrate.
摘要翻译：在形成光致抗蚀剂掩模的工艺中，将光致抗蚀剂层施加到基底上。在光致抗蚀剂层中形成硅化层。硅酸盐化区域的特征对应于要形成的光致抗蚀剂掩模的特征。然后蚀刻光致抗蚀剂层以在硅化区域下方形成光致抗蚀剂基底。蚀刻光致抗蚀剂基底以从其侧面去除材料，使得它比斯里芬特区域变窄。然后除去硅酸盐化区域，在基材上留下光刻胶掩模。

3. 发明授权

US06563221B1 Connection structures for integrated circuits and processes for their formation 失效
标题翻译：集成电路的连接结构及其形成过程
公开(公告)号：US06563221B1
公开(公告)日：2003-05-13
申请号：US10081982
申请日：2002-02-21
申请人： Scott A. Bell , Todd P. Lukanc , Christopher F. Lyons , Marina V. Plat , Ramkumar Subramanian
发明人： Scott A. Bell , Todd P. Lukanc , Christopher F. Lyons , Marina V. Plat , Ramkumar Subramanian
IPC分类号： H01L2348
CPC分类号： H01L21/76885 , H01L21/76831 , H01L23/485 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： In a method for forming a connection structure in an integrated circuit, a first conducting material is deposited over a substrate and patterned to form a conducting stud in electrical contact with a conducting element of the substrate. A dielectric is formed over the substrate and the conducting stud. A trench is formed in the dielectric to expose a top portion of the conducting stud, and a second conducting material is inlaid in the trench to form wiring in electrical contact with the conducting stud. The electrically conducting element of the substrate may be an element of a semiconductor device or a wiring, contact or via. The first conducting material may be aluminum, and the second conducting material may be copper. The dielectric may be formed as a single layer and may be an organic low-k dielectric. Related connection structures are also disclosed.
摘要翻译：在用于在集成电路中形成连接结构的方法中，第一导电材料沉积在衬底上并被图案化以形成与衬底的导电元件电接触的导电柱。电介质形成在衬底和导电柱上。在电介质中形成沟槽以暴露导电柱的顶部，并且第二导电材料镶嵌在沟槽中以形成与导电柱电接触的布线。衬底的导电元件可以是半导体器件或布线，接触或通孔的元件。第一导电材料可以是铝，第二导电材料可以是铜。电介质可以形成为单层，并且可以是有机低k电介质。还公开了相关的连接结构。

4. 发明授权

US06534418B1 Use of silicon containing imaging layer to define sub-resolution gate structures 有权
标题翻译：使用含硅成像层来定义次分辨率门结构
公开(公告)号：US06534418B1
公开(公告)日：2003-03-18
申请号：US09845656
申请日：2001-04-30
申请人： Marina V. Plat , Scott A. Bell , Christopher F. Lyons , Ramkumar Subramanian , Bhanwar Singh
发明人： Marina V. Plat , Scott A. Bell , Christopher F. Lyons , Ramkumar Subramanian , Bhanwar Singh
IPC分类号： H01L21302
CPC分类号： H01L21/0338 , H01L21/0337 , H01L21/28123 , H01L29/6659 , H01L29/7833
摘要： An exemplary method of using silicon containing imaging layers to define sub-resolution gate structures can include depositing an anti-reflective coating over a layer of polysilicon, depositing an imaging layer over the anti-reflective coating, selectively etching the anti-reflective coating to form a pattern, and removing portions of the polysilicon layer using the pattern formed from the removed portions of anti-reflective coating. Thus, the use of thin imaging layer, that has high etch selectivity to the organic underlayer, allows the use of trim etch techniques without a risk of resist erosion or aspect ratio pattern collapse. That, in turn, allows for the formation of the gate pattern with widths less than the widths of the pattern of the imaging layer.
摘要翻译：使用含硅成像层来限定次分辨率门结构的示例性方法可以包括在多晶硅层上沉积抗反射涂层，在抗反射涂层上沉积成像层，选择性地蚀刻抗反射涂层以形成使用由抗反射涂层的去除部分形成的图案去除多晶硅层的部分。因此，对有机底层具有高蚀刻选择性的薄成像层的使用允许使用修剪蚀刻技术，而不会有抗蚀剂侵蚀或高宽比图案崩溃的风险。这又反过来允许形成具有小于成像层的图案的宽度的宽度的栅极图案。

5. 发明授权

US06737222B2 Dual damascene process utilizing a bi-layer imaging layer 有权
标题翻译：双镶嵌工艺利用双层成像层
公开(公告)号：US06737222B2
公开(公告)日：2004-05-18
申请号：US09884834
申请日：2001-06-19
申请人： Ramkumar Subramanian , Christopher F. Lyons , Marina V. Plat , Scott A. Bell
发明人： Ramkumar Subramanian , Christopher F. Lyons , Marina V. Plat , Scott A. Bell
IPC分类号： G03F700
CPC分类号： H01L21/76829 , G03F7/0035 , G03F7/095 , H01L21/0274 , H01L21/31144 , H01L21/76801 , H01L21/76802 , H01L21/76808 , H01L2221/1031
摘要： A method of utilizing a multilayer photoresist to form contact holes and/or conductors utilizing a dual damascene process includes utilizing layered photoresists. A contact in a conductive line can be formed in a single deposition step or in a two-stage deposition step. Image layers can remain as part of the interconnect structure or be removed by a polishing technique. The process can be utilized for any conductive structures provided above a substrate of an integrated circuit.
摘要翻译：利用多层光刻胶形成接触孔和/或使用双镶嵌工艺的导体的方法包括利用层状光致抗蚀剂。可以在单个沉积步骤中或在两级沉积步骤中形成导电线中的接触。图像层可以保留为互连结构的一部分，或者通过抛光技术去除。该方法可用于设置在集成电路的衬底上的任何导电结构。

6. 发明授权

US07052921B1 System and method using in situ scatterometry to detect photoresist pattern integrity during the photolithography process 有权
标题翻译：使用原位散射法在光刻过程中检测光致抗蚀剂图案完整性的系统和方法
公开(公告)号：US07052921B1
公开(公告)日：2006-05-30
申请号：US10934192
申请日：2004-09-03
申请人： Marina V. Plat , Bhanwar Singh , Calvin T. Gabriel , Christopher F. Lyons , Scott A. Bell , Ramkumar Subramanian , Srikanteswara Dakshina-Murthy
发明人： Marina V. Plat , Bhanwar Singh , Calvin T. Gabriel , Christopher F. Lyons , Scott A. Bell , Ramkumar Subramanian , Srikanteswara Dakshina-Murthy
IPC分类号： H01L21/66
CPC分类号： G03F7/70625 , G03F7/70608 , H01L22/12
摘要： The present invention uses in situ scatterometry to determine if a defect (e.g., photoresist erosion, photoresist bending and pattern collapse) is present on a wafer. In one embodiment, in situ scatterometry is used to detect a pattern integrity defect associated with the layer of photoresist. In situ scatterometry produces diffraction data associated with the thickness of the photoresist patterned mask. This data is compared to a model of diffraction data associated with a suitable photoresist thickness. If the measured diffraction data is within an acceptable range, the next step of the photolithography process is carried out. However, if the measured thickness is outside of the suitable range, a defect is detected, and the wafer may be sent for re-working or re-patterned prior to main etch, thereby preventing unnecessary wafer scrap. Another aspect of the present invention allows for a feedback control mechanism to alter a physical parameter of the photolithographic process based upon the in situ scatterometry measurements.
摘要翻译：本发明使用原位散射法来确定晶片上是否存在缺陷（例如，光致抗蚀剂侵蚀，光致抗蚀剂弯曲和图案崩溃）。在一个实施例中，原位散射法用于检测与光致抗蚀剂层相关联的图案完整性缺陷。原位散射法产生与光致抗蚀剂图案掩模的厚度相关的衍射数据。将该数据与与合适的光致抗蚀剂厚度相关联的衍射数据的模型进行比较。如果测量的衍射数据在可接受的范围内，则进行光刻工艺的下一步骤。然而，如果测量的厚度在合适的范围之外，则检测到缺陷，并且可以在主蚀刻之前将晶片发送用于再加工或重新图案化，从而防止不必要的晶片废料。本发明的另一方面允许反馈控制机制基于原位散射测量来改变光刻工艺的物理参数。

7. 发明授权

US06541360B1 Bi-layer trim etch process to form integrated circuit gate structures 有权
标题翻译：双层微调蚀刻工艺形成集成电路门结构
公开(公告)号：US06541360B1
公开(公告)日：2003-04-01
申请号：US09845649
申请日：2001-04-30
申请人： Marina V. Plat , Scott A. Bell , Christopher F. Lyons , Ramkumar Subramanian , Bhanwar Singh
发明人： Marina V. Plat , Scott A. Bell , Christopher F. Lyons , Ramkumar Subramanian , Bhanwar Singh
IPC分类号： H01L213205
CPC分类号： H01L21/0338 , H01L21/0271 , H01L21/0337 , H01L21/32139 , Y10S438/947 , Y10S438/952
摘要： A bi-layer trim etch process to form integrated circuit gate structures can include depositing an organic underlayer over a layer of polysilicon, depositing an imaging layer over the organic underlayer, patterning the imaging layer, selectively trim etching the organic underlayer to form a pattern, and removing portions of the polysilicon layer using the pattern formed from the removed portions of organic underlayer. Thus, the use of thin imaging layer, that has high etch selectivity to the organic underlayer, allows the use of trim etch techniques without a risk of resist erosion or the aspect ratio pattern collapse. That, in turn, allows for the formation of the gate pattern with widths less than the widths of the pattern of the imaging layer.
摘要翻译：用于形成集成电路栅极结构的双层修剪蚀刻工艺可以包括在多晶硅层上沉积有机底层，在有机底层上沉积成像层，图案化成像层，选择性地修整蚀刻有机底层以形成图案，以及使用由有机底层的去除部分形成的图案去除多晶硅层的部分。因此，对有机底层具有高蚀刻选择性的薄成像层的使用允许使用微调蚀刻技术，而不会有抗蚀剂侵蚀或长宽比图案崩溃的风险。这又反过来允许形成具有小于成像层的图案的宽度的宽度的栅极图案。

8. 发明授权

US06383952B1 RELACS process to double the frequency or pitch of small feature formation 失效
标题翻译： RELACS过程将小特征形成的频率或间距加倍
公开(公告)号：US06383952B1
公开(公告)日：2002-05-07
申请号：US09794632
申请日：2001-02-28
申请人： Ramkumar Subramanian , Bhanwar Singh , Marina V. Plat , Christopher F. Lyons , Scott A. Bell
发明人： Ramkumar Subramanian , Bhanwar Singh , Marina V. Plat , Christopher F. Lyons , Scott A. Bell
IPC分类号： H01L2131
CPC分类号： H01L21/0271 , H01L21/0273 , H01L21/0332 , H01L21/0337 , H01L21/0338
摘要： A method of doubling the frequency of small pattern formation. The method includes forming a photoresist layer, and then patterning it. A RELACS polymer is spread over the patterned photoresist layer. Portions of the RELACS polymer on top portions of each patterned photoresist region are removed, by either etching or by polishing them off. Portions between each patterned photoresist region are also removed in this step. The patterned photoresist regions are removed, preferably by a flood exposure and then application of a developer to the exposed photoresist regions. The remaining RELACS polymer regions, which were disposed against respective sidewalls of the patterned photoresist regions, prior to their removal, are then used for forming small pattern regions to be used in a semiconductor device to be formed on the substrate. These small pattern regions can be used to form separate poly-gates.
摘要翻译：一种将图案形成加倍的方法。该方法包括形成光致抗蚀剂层，然后对其进行图案化。 RELACS聚合物分散在图案化的光致抗蚀剂层上。通过蚀刻或通过抛光，去除每个图案化的光致抗蚀剂区域的顶部上的部分RELACS聚合物。在该步骤中也去除了每个图案化的光致抗蚀剂区域之间的部分。去除图案化的光致抗蚀剂区域，优选通过暴露曝光，然后将显影剂施加到曝光的光致抗蚀剂区域。然后将其去除之前设置在图案化光致抗蚀剂区域的相应侧壁上的剩余RELACS聚合物区域用于形成待用于形成在衬底上的半导体器件中的小图案区域。这些小图案区域可用于形成单独的多门。

9. 发明授权

US06753266B1 Method of enhancing gate patterning properties with reflective hard mask 有权
标题翻译：用反射硬掩模增强栅极图案化性能的方法
公开(公告)号：US06753266B1
公开(公告)日：2004-06-22
申请号：US09845654
申请日：2001-04-30
申请人： Todd P. Lukanc , Scott A. Bell , Christopher F. Lyons , Marina V. Plat , Ramkumar Subramanian
发明人： Todd P. Lukanc , Scott A. Bell , Christopher F. Lyons , Marina V. Plat , Ramkumar Subramanian
IPC分类号： H01L21309
CPC分类号： H01L21/32139 , H01L21/0337 , H01L21/0338 , H01L21/823828
摘要： An exemplary method of fabricating an integrated circuit can include depositing a reflective metal material layer over a layer of polysilicon, depositing an anti-reflective coating over the reflective metal material layer, trim etching the anti-reflective coating to form a pattern, etching the reflective metal material layer according to the pattern, and removing portions of the polysilicon layer using the pattern formed from the removed portions of anti-reflective coating.
摘要翻译：制造集成电路的示例性方法可以包括在多晶硅层上沉积反射金属材料层，在反射金属材料层上沉积抗反射涂层，修整蚀刻抗反射涂层以形成图案，蚀刻反射金属材料层，并且使用由抗反射涂层的去除部分形成的图案去除多晶硅层的部分。

10. 发明授权

US06566214B1 Method of making a semiconductor device by annealing a metal layer to form metal silicide and using the metal silicide as a hard mask to pattern a polysilicon layer 失效
标题翻译：通过退火金属层以形成金属硅化物并且使用金属硅化物作为硬掩模来制造半导体器件以图案化多晶硅层的方法
公开(公告)号：US06566214B1
公开(公告)日：2003-05-20
申请号：US10047036
申请日：2002-01-17
申请人： Christopher F. Lyons , Ramkumar Subramanian , Scott A. Bell , Todd P. Lukanc , Marina V. Plat
发明人： Christopher F. Lyons , Ramkumar Subramanian , Scott A. Bell , Todd P. Lukanc , Marina V. Plat
IPC分类号： H01L213213
CPC分类号： H01L21/28123
摘要： A method of making a semiconductor device is provided. A polysilicon layer is formed over a substrate and a metal layer is formed on the polysilicon layer. The metal layer and the polysilicon layer are annealed to form a metal silicide layer on the polysilicon layer. The metal silicide layer is patterned and the polysilicon layer is then patterned using the patterned metal silicide layer as a mask. The patterned metal silicide and polysilicon layers may be used as a gate electrode of a MOSFET.
摘要翻译：提供制造半导体器件的方法。在衬底上形成多晶硅层，并且在多晶硅层上形成金属层。退火金属层和多晶硅层，以在多晶硅层上形成金属硅化物层。图案化金属硅化物层，然后使用图案化的金属硅化物层作为掩模来对多晶硅层进行构图。图案化的金属硅化物和多晶硅层可以用作MOSFET的栅电极。

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