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11. 发明授权

US06507474B1 Using localized ionizer to reduce electrostatic charge from wafer and mask 有权
标题翻译：使用局部电离器来减少晶片和掩模的静电电荷
公开(公告)号：US06507474B1
公开(公告)日：2003-01-14
申请号：US09597126
申请日：2000-06-19
申请人： Bhanwar Singh , Ramkumar Subramanian , Khoi A. Phan , Bryan K. Choo , Bharath Rangarajan
发明人： Bhanwar Singh , Ramkumar Subramanian , Khoi A. Phan , Bryan K. Choo , Bharath Rangarajan
IPC分类号： H01T2300
CPC分类号： G03F7/70616 , G03F7/70941
摘要： One aspect of the present invention elates to a method of reducing electrostatic charges on a patterned photoresist to improve evaluation of the developed photoresist, involving the steps of evaluating the patterned photoresist to determine if electrostatic charges exist thereon; positioning an ionizer near the patterned photoresist, the ionizer generating ions thereby reducing the electrostatic charges on the patterned photoresist; and evaluating the patterned photoresist with an electron beam. Another aspect of the present invention relates to a system for reducing electrostatic charges on a patterned photoresist, containing a charge sensor for determining if electrostatic charges exist on the patterned photoresist and measuring the electrostatic charges; an ionizer positioned near the patterned photoresist having electrostatic charges thereon for reducing the electrostatic charges on the patterned photoresist; a controller for setting at least one of time of ion generation and amount of ion generation by the ionizer, the controller coupled to the charge sensor and the ionizer; and a scanning electron microscope or an atomic force microscope for evaluating the patterned photoresist having reduced electrostatic charges thereon with an electron beam.
摘要翻译：本发明的一个方面是提供减少图案化光致抗蚀剂上的静电电荷以改进对显影光致抗蚀剂的评估的方法，包括评估图案化光致抗蚀剂以确定静电电荷是否存在于其中的步骤; 在图案化的光致抗蚀剂附近定位电离器，离子发生器产生离子，从而减少图案化光致抗蚀剂上的静电电荷; 并用电子束评估图案化的光致抗蚀剂。本发明的另一方面涉及一种用于减少图案化光致抗蚀剂上的静电电荷的系统，其包含用于确定图案化光致抗蚀剂上是否存在静电电荷并测量静电电荷的电荷传感器; 位于图案化的光致抗蚀剂附近的电离器，其上具有静电电荷，用于减少图案化光致抗蚀剂上的静电电荷; 用于设置离子发生时间和离子发生量中的至少一个的控制器，耦合到电荷传感器和离子发生器的控制器; 以及扫描电子显微镜或原子力显微镜，用于用电子束评估其上具有降低的静电电荷的图案化光致抗蚀剂。

12. 发明授权

US06632283B1 System and method for illuminating a semiconductor processing system 失效
标题翻译：用于照射半导体处理系统的系统和方法
公开(公告)号：US06632283B1
公开(公告)日：2003-10-14
申请号：US09591163
申请日：2000-06-09
申请人： Bhanwar Singh , Bharath Rangarajan , Khoi A. Phan , Bryan K. Choo , Ramkumar Subramanian
发明人： Bhanwar Singh , Bharath Rangarajan , Khoi A. Phan , Bryan K. Choo , Ramkumar Subramanian
IPC分类号： B05C1102
CPC分类号： H01L21/6719 , H01L21/67253
摘要： The present invention relates to illuminating an interior portion of a processing chamber in a semiconductor processing system. A light emitting diode is located in the chamber to illuminate the interior of the chamber to facilitate viewing the interior of the chamber.
摘要翻译：本发明涉及照射半导体处理系统中的处理室的内部部分。发光二极管位于腔室内以照亮腔室的内部，以便于观察腔室内部。

13. 发明授权

US06572252B1 System and method for illuminating a semiconductor processing system 有权
标题翻译：用于照射半导体处理系统的系统和方法
公开(公告)号：US06572252B1
公开(公告)日：2003-06-03
申请号：US09591085
申请日：2000-06-09
申请人： Bharath Rangarajan , Bhanwar Singh , Khoi A. Phan , Bryan K. Choo , Ramkumar Subramanian
发明人： Bharath Rangarajan , Bhanwar Singh , Khoi A. Phan , Bryan K. Choo , Ramkumar Subramanian
IPC分类号： F21V704
CPC分类号： H01L21/67005
摘要： The present invention relates to illuminating an interior portion of a processing chamber in a semiconductor processing system. A fiber optic light source is operatively associated with the processing chamber to illuminate the interior of the chamber to facilitate viewing the interior of the chamber.
摘要翻译：本发明涉及照射半导体处理系统中的处理室的内部部分。光纤光源与处理室可操作地相关联以照亮室的内部，以便于观察室的内部。

14. 发明授权

US06479820B1 Electrostatic charge reduction of photoresist pattern on development track 有权
标题翻译：光刻胶图案在显影轨上的静电电荷减少
公开(公告)号：US06479820B1
公开(公告)日：2002-11-12
申请号：US09557720
申请日：2000-04-25
申请人： Bhanwar Singh , Ramkumar Subramanian , Bharath Rangarajan , Khoi A. Phan , Bryan K. Choo
发明人： Bhanwar Singh , Ramkumar Subramanian , Bharath Rangarajan , Khoi A. Phan , Bryan K. Choo
IPC分类号： G03F730
CPC分类号： G03F7/40 , G03F7/405
摘要： In one embodiment, the present invention relates to a method of processing a photoresist on a semiconductor structure, involving the steps of exposing and developing the photoresist; evaluating the exposed and developed photoresist to determine if negative charges exist thereon; contacting the exposed and developed photoresist with a positive ion carrier thereby reducing any negative charges thereon; and evaluating the exposed and developed photoresist with an electron beam. In another embodiment, the present invention relates to a system for processing a patterned photoresist on a semiconductor structure, containing a charge sensor for determining if charges exist on the patterned photoresist and measuring the charges; a means for contacting the patterned photoresist with a positive ion carrier to reduce the charges thereon; a controller for setting at least one of time of contact between the patterned photoresist and the positive ion carrier, temperature of the positive ion carrier, concentration of positive ions in the positive ion carrier, and pressure under which contact between the patterned photoresist and the positive ion carrier occurs; and a device for evaluating the patterned photoresist with an electron beam.
摘要翻译：在一个实施方案中，本发明涉及一种在半导体结构上处理光致抗蚀剂的方法，包括曝光和显影光致抗蚀剂的步骤; 评估曝光和显影的光致抗蚀剂以确定其上是否存在负电荷; 使曝光和显影的光致抗蚀剂与正离子载体接触，从而减少其上的任何负电荷; 并用电子束评估曝光和显影的光致抗蚀剂。在另一个实施例中，本发明涉及一种用于处理半导体结构上的图案化光致抗蚀剂的系统，其包含用于确定图案化光致抗蚀剂上是否存在电荷并测量电荷的电荷传感器; 用于使图案化的光致抗蚀剂与正离子载体接触以减少其上的电荷的装置; 控制器，用于设置图案化的光致抗蚀剂和正离子载体之间的接触时间中的至少一个，正离子载体的温度，正离子载体中的正离子的浓度以及图案化的光致抗蚀剂和阳离子的正极之间的接触发生离子载体; 以及用电子束评估图案化光致抗蚀剂的装置。

15. 发明授权

US06373053B1 Analysis of CD-SEM signal to detect scummed/closed contact holes and lines 有权
标题翻译：分析CD-SEM信号以检测浮渣/闭合接触孔和管线
公开(公告)号：US06373053B1
公开(公告)日：2002-04-16
申请号：US09495281
申请日：2000-01-31
申请人： Bryan K. Choo , Bhanwar Singh , Sanjay K. Yedur , Khoi A. Phan
发明人： Bryan K. Choo , Bhanwar Singh , Sanjay K. Yedur , Khoi A. Phan
IPC分类号： G01N2300
CPC分类号： G01N21/9501 , H01L22/12 , H01L2924/0002 , H01L2924/00
摘要： A system is provided for detecting scumming in a wafer. The system includes an analysis system for providing a signal corresponding to a surface portion of the wafer and a processing system operatively coupled to the analysis system. The processing system is configured to determine a shape of at least a portion of the signal and, the processing system detects scumming in the wafer based upon the shape of at least a portion of the signal.
摘要翻译：提供了一种用于检测晶片中的浮渣的系统。该系统包括用于提供对应于晶片的表面部分的信号的分析系统和可操作地耦合到分析系统的处理系统。处理系统被配置为确定信号的至少一部分的形状，并且处理系统基于信号的至少一部分的形状来检测晶片中的浮渣。

16. 发明授权

US06354133B1 Use of carbon nanotubes to calibrate conventional tips used in AFM 失效
标题翻译：使用碳纳米管校准AFM中使用的常规提示
公开(公告)号：US06354133B1
公开(公告)日：2002-03-12
申请号：US09729293
申请日：2000-12-04
申请人： Sanjay K. Yedur , Bhanwar Singh , Bryan K. Choo , Michael K. Templeton , Ramkumar Subramanian
发明人： Sanjay K. Yedur , Bhanwar Singh , Bryan K. Choo , Michael K. Templeton , Ramkumar Subramanian
IPC分类号： G01B528
CPC分类号： G01Q40/02 , G01Q40/00 , Y10S977/742 , Y10S977/842 , Y10S977/849 , Y10S977/85 , Y10S977/876 , Y10S977/901
摘要： The present invention provides systems, methods, and standards for calibrating nano-measuring devices. Calibration standards of the invention include carbon nanotubes and methods of the invention involve scanning carbon nanotubes using nano-scale measuring devices. The widths of the carbon nanotube calibration standards are known with a high degree of accuracy. The invention allows calibration of a wide variety of nano-scale measuring devices, taking into account many, and in some cases all, of the systematic errors that may affect a nano-scale measurement. The invention may be used to accurately calibrate line width, line height, and trench width measurements and may be used to precisely characterize both scanning probe microscope tips and electron microscope beams.
摘要翻译：本发明提供了用于校准纳米测量装置的系统，方法和标准。本发明的校准标准包括碳纳米管，本发明的方法涉及使用纳米级测量装置扫描碳纳米管。碳纳米管校准标准品的宽度以高精度已知。考虑到可能影响纳米尺度测量的许多系统误差以及在所有这些系统误差中，本发明允许校准各种各样的纳米尺度的测量装置。本发明可以用于精确校准线宽，线高度和沟槽宽度测量，并且可以用于精确地表征扫描探针显微镜尖端和电子显微镜束。

17. 发明授权

US06591658B1 Carbon nanotubes as linewidth standards for SEM & AFM 失效
标题翻译：碳纳米管作为SEM和AFM的线宽标准
公开(公告)号：US06591658B1
公开(公告)日：2003-07-15
申请号：US09729297
申请日：2000-12-04
申请人： Sanjay K. Yedur , Bhanwar Singh , Bryan K. Choo , Michael K. Templeton , Ramkumar Subramanian
发明人： Sanjay K. Yedur , Bhanwar Singh , Bryan K. Choo , Michael K. Templeton , Ramkumar Subramanian
IPC分类号： G01B1508
CPC分类号： G01Q40/02 , H01J2237/2816 , H01J2237/2826 , Y10S977/742 , Y10S977/86 , Y10S977/863 , Y10S977/869 , Y10S977/875 , Y10S977/881 , Y10T29/53004
摘要： The present invention provides systems, methods, and standards for calibrating nano-measuring devices. Calibration standards of the invention include carbon nanotubes and methods of the invention involve scanning carbon nanotubes using nano-scale measuring devices. The widths of the carbon nanotube calibration standards are known with a high degree of accuracy. The invention allows calibration of a wide variety of nano-scale measuring devices, taking into account many, and in some cases all, of the systematic errors that may affect a nano-scale measurement. The invention may be used to accurately calibrate line width, line height, and trench width measurements and may be used to precisely characterize both scanning probe microscope tips and electron microscope beams.
摘要翻译：本发明提供了用于校准纳米测量装置的系统，方法和标准。本发明的校准标准包括碳纳米管，本发明的方法涉及使用纳米级测量装置扫描碳纳米管。碳纳米管校准标准品的宽度以高精度已知。考虑到可能影响纳米尺度测量的许多系统误差以及在所有这些系统误差中，本发明允许校准各种各样的纳米尺度的测量装置。本发明可以用于精确校准线宽，线高度和沟槽宽度测量，并且可以用于精确地表征扫描探针显微镜尖端和电子显微镜束。

18. 发明授权

US06813574B1 Topographically aligned layers and method for adjusting the relative alignment of layers and apparatus therefor 有权
标题翻译：用于调整层的相对对准的方法和用于其的设备的方法
公开(公告)号：US06813574B1
公开(公告)日：2004-11-02
申请号：US09992599
申请日：2001-11-06
申请人： Sanjay K. Yedur , Bhanwar Singh , Bharath Rangarajan , Ramkumar Subramanian
发明人： Sanjay K. Yedur , Bhanwar Singh , Bharath Rangarajan , Ramkumar Subramanian
IPC分类号： G01N2186
CPC分类号： H01L23/544 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： Patterned layers in an integrated circuit (IC) or other device are aligned in conjunction with the detection of the topology of the layers. The topology can be used to determine the location of a metrology mark and/or to compensate for a horizontal shift in the apparent location of the metrology mark. Precise detection of topography can be achieved without physical contact with the IC or other device with an atomic force microscope.
摘要翻译：集成电路（IC）或其他设备中的图案层与层的拓扑结构的检测结合对齐。拓扑结构可用于确定计量标记的位置和/或补偿计量标记的表观位置的水平位移。无需使用原子力显微镜与IC或其他器件物理接触即可实现精确的形貌检测。

19. 发明授权

US06605855B1 CVD plasma process to fill contact hole in damascene process 有权
标题翻译： CVD等离子体工艺在镶嵌工艺中填充接触孔
公开(公告)号：US06605855B1
公开(公告)日：2003-08-12
申请号：US09650538
申请日：2000-08-30
申请人： Bhanwar Singh , Michael K. Templeton , Bharath Rangarajan , Christopher F. Lyons , Sanjay K. Yedur , Ramkumar Subramanian
发明人： Bhanwar Singh , Michael K. Templeton , Bharath Rangarajan , Christopher F. Lyons , Sanjay K. Yedur , Ramkumar Subramanian
IPC分类号： H01L2900
CPC分类号： H01L21/76808 , H01L21/31144 , H01L21/312 , H01L21/76831 , H01L2221/1063
摘要： The present invention relates to a method for fabricating interconnecting lines and vias in a layer of insulating material. A via is formed in the layer of insulating material. A protective material is formed so as to be conformal to at least edges and sidewalls of the via, the protective material facilitating shielding of at least the edges and sidewalls of the via from a trench etch step. The trench etch step is performed to form a trench opening in the insulating material. The via and trench are filled with a conductive metal.
摘要翻译：本发明涉及在绝缘材料层中制造互连线和通孔的方法。在绝缘材料层中形成通孔。形成保护材料以至少与通孔的边缘和侧壁共形，所述保护材料有助于屏蔽通孔的至少边缘和侧壁至沟槽蚀刻步骤。执行沟槽蚀刻步骤以在绝缘材料中形成沟槽开口。通孔和沟槽填充有导电金属。

20. 发明授权

US06326231B1 Use of silicon oxynitride ARC for metal layers 有权
标题翻译：氧氮化硅ARC用于金属层
公开(公告)号：US06326231B1
公开(公告)日：2001-12-04
申请号：US09207562
申请日：1998-12-08
申请人： Ramkumar Subramanian , Bhanwar Singh , Sanjay K. Yedur , Marina V. Plat , Christopher F. Lyons , Bharath Rangarajan , Michael K. Templeton
发明人： Ramkumar Subramanian , Bhanwar Singh , Sanjay K. Yedur , Marina V. Plat , Christopher F. Lyons , Bharath Rangarajan , Michael K. Templeton
IPC分类号： H01L2100
CPC分类号： H01L21/32139 , H01L21/0276 , H01L21/3143 , H01L21/3145
摘要： In one embodiment, the present invention relates to a method of forming a silicon oxynitride antireflection coating over a metal layer, involving the steps of providing a semiconductor substrate comprising the metal layer over at least part of the semiconductor substrate; depositing a silicon oxynitride layer over the metal layer having a thickness from about 100 Å to about 150 Å; and forming an oxide layer having a thickness from about 5 Å to about 50 Å over the silicon oxynitride layer to provide the silicon oxynitride antireflection coating. In another embodiment, the present invention relates to a method of reducing an apparent reflectivity of a metal layer having a first reflectivity in a semiconductor structure, involing forming a silicon oxynitride antireflection coating over the metal layer; wherein the silicon oxynitride antireflection coating formed over the metal layer has a second reflectivity and is formed by depositing silicon oxynitride on the metal layer by chemical vapor deposition and forming an oxide layer over the oxynitride, and the difference between the first reflectivity and the second reflectivity is at least about 60%.
摘要翻译：在一个实施方案中，本发明涉及在金属层上形成氮氧化硅抗反射涂层的方法，包括以下步骤：在半导体衬底的至少一部分上提供包括金属层的半导体衬底; 在所述金属层上沉积厚度为约至约的氧氮化硅层; 并在氮氧化硅层上形成厚度约为5-20埃的氧化物层，以提供氮氧化硅抗反射涂层。在另一个实施方案中，本发明涉及一种在半导体结构中减少具有第一反射率的金属层的表观反射率的方法，包括在金属层上形成氮氧化硅抗反射涂层; 其中形成在所述金属层上的所述氧氮化硅抗反射涂层具有第二反射率，并且通过化学气相沉积在所述金属层上沉积氧氮化硅并在所述氧氮化物上形成氧化物层，并且所述第一反射率和所述第二反射率之间的差异至少约60％。

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