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11. 发明授权

US07122435B2 Methods, systems and structures for forming improved transistors 有权
标题翻译：用于形成改进的晶体管的方法，系统和结构
公开(公告)号：US07122435B2
公开(公告)日：2006-10-17
申请号：US10909515
申请日：2004-08-02
申请人： PR Chidambaram , Haowen Bu
发明人： PR Chidambaram , Haowen Bu
IPC分类号： H01L21/336
CPC分类号： H01L29/7842 , H01L21/823807 , H01L21/823814 , H01L29/6659 , H01L29/66636 , H01L29/7833 , H01L29/7848
摘要： A method (100) of forming a transistor includes forming a gate structure (106, 108) over a semiconductor body and forming recesses (112) substantially aligned to the gate structure in the semiconductor body. Amorphous silicon regions are then formed (114) in the recesses. The amorphous silicon regions are re-crystallized. Sidewall spacers are formed (118) over lateral edges of the gate structure. The method continues by implanting source and drain regions in the semiconductor body (120) after forming the sidewall spacers. The re-crystallized silicon regions formed in the recesses reside close to the transistor channel and serve to facilitate improved carrier mobility in NMOS type transistor devices.
摘要翻译：形成晶体管的方法（100）包括在半导体主体上形成栅极结构（106,108），并形成与半导体本体中的栅极结构基本对齐的凹槽（112）。然后在凹部中形成非晶硅区域（114）。非晶硅区域再结晶。在门结构的横向边缘上形成侧壁间隔物（118）。该方法通过在形成侧壁间隔物之后将源区和漏区注入半导体本体（120）中来继续。形成在凹槽中的再结晶硅区域靠近晶体管沟道，并且有助于改善NMOS型晶体管器件中的载流子迁移率。

12. 发明申请

US20060166457A1 Method of making transistors and non-silicided polysilicon resistors for mixed signal circuits 审中-公开
标题翻译：制造用于混合信号电路的晶体管和非硅化多晶硅电阻器的方法
公开(公告)号：US20060166457A1
公开(公告)日：2006-07-27
申请号：US11040749
申请日：2005-01-21
申请人： Sarah Liu , Greg Baldwin , Haowen Bu , Shashank Ekbote
发明人： Sarah Liu , Greg Baldwin , Haowen Bu , Shashank Ekbote
IPC分类号： H01L21/336
CPC分类号： H01L28/20 , H01L27/0629
摘要： A method for manufacturing a semiconductor wafer 10 that includes implanting source/drain regions 75 within a top surface of the semiconductor substrate 20, forming a dielectric capping layer 170 over the semiconductor wafer 20, and annealing the semiconductor wafer 10 to activate sources/drains 70. The method further includes forming a layer of photoresist 180 and then patterning the layer of photoresist 180 to protect a middle portion of the polysilicon layer 100 of the non-silicided poly resistor stacks 30, etching the exposed portions of the dielectric capping layer 170, and removing the patterned photoresist 180. A layer of silicidation metal 190 is formed over the semiconductor wafer 10, and a silicide anneal is performed to create a silicide 160 within a top surface of said sources/drains 70 and also within unprotected top portions of the polysilicon layer 100 of the non-silicided poly resistors 30. Then the remaining portions of the dielectric capping layer 170 are etched.
摘要翻译：一种用于制造半导体晶片10的方法，其包括在半导体衬底20的顶表面内注入源极/漏极区域75，在半导体晶片20上方形成电介质覆盖层170，并且退火半导体晶片10以激活源极/漏极70 。该方法还包括形成光致抗蚀剂层180，然后对光致抗蚀剂180的层进行图案化，以保护非硅化多电阻堆叠30的多晶硅层100的中间部分，蚀刻介电覆盖层170的暴露部分，以及去除图案化的光致抗蚀剂180。在半导体晶片10上形成一层硅化金属190，并且进行硅化物退火以在所述源极/漏极70的顶表面内以及非多晶硅层100的非保护顶部内形成硅化物160，硅化聚电阻30。然后蚀刻介电覆盖层170的剩余部分。

13. 发明申请

US20050215038A1 Method for using a wet etch to manufacturing a semiconductor device having a silicided gate electrode and a method for manufacturing an integrated circuit including the same 有权
标题翻译：使用湿式蚀刻来制造具有硅化物栅电极的半导体器件的方法以及包括其的集成电路的制造方法
公开(公告)号：US20050215038A1
公开(公告)日：2005-09-29
申请号：US10884665
申请日：2004-07-02
申请人： Lindsey Hall , Haowen Bu , Shaofeng Yu
发明人： Lindsey Hall , Haowen Bu , Shaofeng Yu
IPC分类号： H01L21/28 , H01L21/336 , H01L21/44 , H01L29/49 , H01L29/78
CPC分类号： H01L29/66507 , H01L21/28097 , H01L29/4975 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： The present invention provides a method for manufacturing a semiconductor device and a method for manufacturing an integrated circuit including the semiconductor device. The method for manufacturing the semiconductor device, among other possible steps, forming a polysilicon gate electrode (250) over a substrate (210) and forming a protective layer (260) over the polysilicon gate electrode (250) to provide a capped polysilicon gate electrode (230). The method further includes forming a protective oxide (510) on a surface proximate the polysilicon gate electrode (250), and removing the protective oxide (510) using a wet etch, the wet etch not having a substantial impact on the protective layer (260).
摘要翻译：本发明提供一种制造半导体器件的方法及其制造方法，该集成电路包括该半导体器件。制造半导体器件的方法以及其它可能的步骤，在衬底（210）上形成多晶硅栅电极（250）并在多晶硅栅电极（250）上形成保护层（260），以提供封盖的多晶硅栅电极（230）。该方法还包括在邻近多晶硅栅极（250）的表面上形成保护氧化物（510），并且使用湿蚀刻去除保护氧化物（510），湿法蚀刻不会对保护层（260 ）。

14. 发明申请

US20050139872A1 Drive current improvement from recessed SiGe incorporation close to gate 有权
标题翻译：驱动目前从嵌入式SiGe并入门口的改进
公开(公告)号：US20050139872A1
公开(公告)日：2005-06-30
申请号：US10901568
申请日：2004-07-29
申请人： Pr Chidambaram , Douglas Grider , Brian Smith , Haowen Bu , Lindsey Hall
发明人： Pr Chidambaram , Douglas Grider , Brian Smith , Haowen Bu , Lindsey Hall
IPC分类号： H01L21/336 , H01L21/8238 , H01L29/76
CPC分类号： H01L29/6659 , H01L21/823807 , H01L21/823814 , H01L29/665 , H01L29/6656 , H01L29/66636 , H01L29/7842 , H01L29/7848
摘要： A method (100) of forming a transistor includes forming a gate structure (106, 108) over a semiconductor body and forming recesses (112) substantially aligned to the gate structure in the semiconductor body. Silicon germanium is then epitaxially grown (114) in the recesses, followed by forming sidewall spacers (118) over lateral edges of the gate structure. The method continues by implanting source and drain regions in the semiconductor body (120) after forming the sidewall spacers. The silicon germanium formed in the recesses resides close to the transistor channel and serves to provide a compressive stress to the channel, thereby facilitating improved carrier mobility in PMOS type transistor devices.
摘要翻译：形成晶体管的方法（100）包括在半导体主体上形成栅极结构（106,108），并形成与半导体本体中的栅极结构基本对齐的凹槽（112）。然后在凹槽中外延生长硅（114），随后在栅极结构的横向边缘上形成侧壁间隔物（118）。该方法通过在形成侧壁间隔物之后将源区和漏区注入半导体本体（120）中来继续。在凹槽中形成的硅锗位于晶体管沟道附近，用于向通道提供压缩应力，从而有助于改善PMOS型晶体管器件的载流子迁移率。

15. 发明申请

US20050136589A1 Method for integrating high-k dielectrics in transistor devices 有权
标题翻译：在晶体管器件中集成高k电介质的方法
公开(公告)号：US20050136589A1
公开(公告)日：2005-06-23
申请号：US10738958
申请日：2003-12-17
申请人： Antonio Rotondaro , Douglas Mercer , Luigi Colombo , Mark Visokay , Haowen Bu , Malcolm Bevan
发明人： Antonio Rotondaro , Douglas Mercer , Luigi Colombo , Mark Visokay , Haowen Bu , Malcolm Bevan
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8242 , H01L29/51
CPC分类号： H01L21/28176 , H01L21/28194 , H01L29/517 , H01L29/518 , H01L29/6656 , H01L29/6659
摘要： Methods are disclosed that fabricating semiconductor devices with high-k dielectric layers. The invention removes portions of deposited high-k dielectric layers not below gates and covers exposed portions (e.g., sidewalls) of high-k dielectric layers during fabrication with an encapsulation layer, which mitigates defects in the high-k dielectric layers and contamination of process tools. The encapsulation layer can also be employed as an etch stop layer and, at least partially, in comprising sidewall spacers. As a result, a semiconductor device can be fabricated with a substantially uniform equivalent oxide thickness.
摘要翻译：公开了制造具有高k电介质层的半导体器件的方法。本发明除了不在门下方的沉积的高k电介质层的部分，并且在用封装层制造期间覆盖高k电介质层的暴露部分（例如，侧壁），这减轻了高k电介质层中的缺陷和工艺污染工具封装层也可以用作蚀刻停止层，并且至少部分地包括侧壁间隔物。结果，可以制造具有基本均匀的等效氧化物厚度的半导体器件。

16. 发明申请

US20050059260A1 CMOS transistors and methods of forming same 审中-公开
标题翻译： CMOS晶体管及其形成方法
公开(公告)号：US20050059260A1
公开(公告)日：2005-03-17
申请号：US10810905
申请日：2004-03-26
申请人： Haowen Bu , Brian Hornung , P.R. Chidambaram , Amitabh Jain , Rajesh Khamankar , Nandu Mahalingam , Srinivansan Chakravarthi
发明人： Haowen Bu , Brian Hornung , P.R. Chidambaram , Amitabh Jain , Rajesh Khamankar , Nandu Mahalingam , Srinivansan Chakravarthi
IPC分类号： H01L21/00 , H01L21/265 , H01L21/3205 , H01L21/324 , H01L21/336 , H01L21/44 , H01L21/4763 , H01L21/8238 , H01L21/84 , H01L29/08 , H01L29/76 , H01L29/78
CPC分类号： H01L21/26506 , H01L21/265 , H01L21/26513 , H01L21/2658 , H01L21/3185 , H01L21/324 , H01L21/823814 , H01L21/823864 , H01L29/0847 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/7833 , H01L29/7843 , H01L29/7845
摘要： The present invention teaches the formation of CMOS transistors using interfacial nitrogen at the interface between the lightly doped extension regions and an overlying insulating layer in combination with a capping layer of silicon nitride, both prior to the final source/drain anneal. Doses and energies may be increased for the P-channel lightly-doped drain, source and drain regions. The resulting transistors exhibit desirably high drive current and low off-state leakage current and overlap capacitance.
摘要翻译：本发明教导了在最终的源极/漏极退火之前，在轻掺杂的延伸区域之间的界面处的界面氮和与氮化硅覆盖层结合的上覆绝缘层的CMOS晶体管的形成。 P沟道轻掺杂漏极，源极和漏极区域的剂量和能量可能会增加。所得到的晶体管显示期望的高驱动电流和低截止状态的漏电流和重叠电容。

17. 发明授权

US06806149B2 Sidewall processes using alkylsilane precursors for MOS transistor fabrication 有权
标题翻译：使用烷基硅烷前驱物进行MOS晶体管制造的侧壁工艺
公开(公告)号：US06806149B2
公开(公告)日：2004-10-19
申请号：US10255215
申请日：2002-09-26
申请人： Haowen Bu , Malcolm J. Bevan
发明人： Haowen Bu , Malcolm J. Bevan
IPC分类号： H01L21336
CPC分类号： H01L29/6659 , H01L29/6656 , H01L29/7833
摘要： A method for using alkylsilane precursors during the sidewall formation process in MOS transistor fabrication processes. Alkylsilane precursors are used to form carbon contain silicon oxide layers (110) and carbon containing silicon nitride layers (120) during the sidewall formation process. The carbon containing layers (110) (120) introduce carbon into the extension regions (100) and the gate region (30) during thermal annealing.
摘要翻译：在MOS晶体管制造工艺中在侧壁形成工艺期间使用烷基硅烷前体的方法。在侧壁形成过程中，烷基硅烷前体用于形成含有氧化硅层（110）和含碳氮化硅层（120）的碳。含碳层（110）（120）在热退火期间将碳引入到延伸区域（100）和栅极区域（30）中。

18. 发明授权

US08114784B2 Laminated stress overlayer using In-situ multiple plasma treatments for transistor improvement 有权
标题翻译：层压应力覆层使用原位多等离子体处理进行晶体管改良
公开(公告)号：US08114784B2
公开(公告)日：2012-02-14
申请号：US12904593
申请日：2010-10-14
申请人： Haowen Bu , Che-Jen Hu , Rajesh Khamankar
发明人： Haowen Bu , Che-Jen Hu , Rajesh Khamankar
IPC分类号： H01L21/31
CPC分类号： H01L21/3185 , C23C14/0652 , C23C16/56 , H01L21/3105 , H01L21/823807 , H01L29/665 , H01L29/7843
摘要： Integrated circuits (ICs) commonly contain pre-metal dielectric (PMD) liners with compressive stress to increase electron and hole mobilities in MOS transistors. The increase is limited by the thickness of the PMD liner. The instant invention is a multi-layered PMD liner in an integrated circuit which has a higher stress than single layer PMD liners. Each layer in the inventive PMD liner is exposed to a nitrogen-containing plasma, and which has a compressive stress higher than 1300 MPa. The PMD liner of the instant invention is composed of 3 to 10 layers. The hydrogen content of the first layer may be increased to improve transistor properties such as flicker noise and Negative Bias Temperature Instability (NBTI). An IC containing the inventive PMD liner and a method for forming same are also claimed.
摘要翻译：集成电路（IC）通常含有具有压应力的预金属电介质（PMD）衬垫，以增加MOS晶体管中的电子和空穴迁移率。该增加受到PMD衬套的厚度的限制。本发明是集成电路中的多层PMD衬垫，其具有比单层PMD衬垫更高的应力。将本发明的PMD衬垫中的每个层暴露于含氮等离子体，并且具有高于1300MPa的压缩应力。本发明的PMD衬垫由3〜10层构成。可以增加第一层的氢含量以改善诸如闪烁噪声和负偏压温度不稳定性（NBTI）的晶体管特性。还要求一种包含本发明的PMD衬垫的IC及其形成方法。

19. 发明授权

US08084312B2 Nitrogen based implants for defect reduction in strained silicon 有权
标题翻译：用于应变硅缺陷还原的氮基植入物
公开(公告)号：US08084312B2
公开(公告)日：2011-12-27
申请号：US12688442
申请日：2010-01-15
申请人： Srinivasan Chakravarthi , P R Chidambaram , Rajesh Khamankar , Haowen Bu , Douglas T. Grider
发明人： Srinivasan Chakravarthi , P R Chidambaram , Rajesh Khamankar , Haowen Bu , Douglas T. Grider
IPC分类号： H01L21/336 , H01L21/8234
CPC分类号： H01L29/7833 , H01L21/26506 , H01L29/665 , H01L29/6659 , H01L29/7843
摘要： A transistor is fabricated upon a semiconductor substrate, where the yield strength or elasticity of the substrate is enhanced or otherwise adapted. A strain inducing layer is formed over the transistor to apply a strain thereto to alter transistor operating characteristics, and more particularly to enhance the mobility of carriers within the transistor. Enhancing carrier mobility allows transistor dimensions to be reduced while also allowing the transistor to operate as desired. However, high strain and temperature associated with fabricating the transistor result in deleterious plastic deformation. The yield strength of the silicon substrate is therefore adapted by incorporating nitrogen into the substrate, and more particularly into source/drain extension regions and/or source/drain regions of the transistor. The nitrogen can be readily incorporated during transistor fabrication by adding it as part of source/drain extension region formation and/or source/drain region formation. The enhanced yield strength of the substrate mitigates plastic deformation of the transistor due to the strain inducing layer.
摘要翻译：晶体管制造在半导体衬底上，其中衬底的屈服强度或弹性得到增强或适应。应变感应层形成在晶体管上以向其施加应变以改变晶体管工作特性，更具体地说，增强晶体管内的载流子迁移率。增强载流子迁移率允许晶体管尺寸减小，同时也允许晶体管根据需要进行操作。然而，与制造晶体管相关的高应变和温度导致有害的塑性变形。因此，硅衬底的屈服强度通过将氮掺入到衬底中，更具体地掺入晶体管的源极/漏极延伸区域和/或源极/漏极区域来适应。在晶体管制造期间，可以通过将其作为源极/漏极延伸区域形成和/或源极/漏极区域形成的一部分来添加来将氮容易地并入。由于应变诱导层，衬底的增强的屈服强度减轻了晶体管的塑性变形。

20. 发明申请

US20110027953A1 Laminated Stress Overlayer Using In-SITU Multiple Plasma Treatments for Transistor Improvement 有权
标题翻译：使用In-SITU多重等离子体处理晶体管改进的层压应力覆盖层
公开(公告)号：US20110027953A1
公开(公告)日：2011-02-03
申请号：US12904593
申请日：2010-10-14
申请人： Haowen Bu , Jerry Che-Jen Hu , Rajesh Khamankar
发明人： Haowen Bu , Jerry Che-Jen Hu , Rajesh Khamankar
IPC分类号： H01L21/8238
CPC分类号： H01L21/3185 , C23C14/0652 , C23C16/56 , H01L21/3105 , H01L21/823807 , H01L29/665 , H01L29/7843
摘要： Integrated circuits (ICs) commonly contain pre-metal dielectric (PMD) liners with compressive stress to increase electron and hole mobilities in MOS transistors. The increase is limited by the thickness of the PMD liner. The instant invention is a multi-layered PMD liner in an integrated circuit which has a higher stress than single layer PMD liners. Each layer in the inventive PMD liner is exposed to a nitrogen-containing plasma, and which has a compressive stress higher than 1300 MPa. The PMD liner of the instant invention is composed of 3 to 10 layers. The hydrogen content of the first layer may be increased to improve transistor properties such as flicker noise and Negative Bias Temperature Instability (NBTI). An IC containing the inventive PMD liner and a method for forming same are also claimed.
摘要翻译：集成电路（IC）通常包含具有压缩应力的预金属电介质（PMD）衬垫，以增加MOS晶体管中的电子和空穴迁移率。该增加受到PMD衬套的厚度的限制。本发明是集成电路中的多层PMD衬垫，其具有比单层PMD衬垫更高的应力。将本发明的PMD衬垫中的每个层暴露于含氮等离子体，并且具有高于1300MPa的压缩应力。本发明的PMD衬垫由3〜10层构成。可以增加第一层的氢含量以改善诸如闪烁噪声和负偏压温度不稳定性（NBTI）的晶体管特性。还要求一种包含本发明的PMD衬垫的IC及其形成方法。

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