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1. 发明申请

US20090152639A1 Laminated Stress Overlayer Using In-SITU Multiple Plasma Treatments for Transistor Improvement 审中-公开
标题翻译：使用In-SITU多重等离子体处理晶体管改进的层压应力覆盖层
公开(公告)号：US20090152639A1
公开(公告)日：2009-06-18
申请号：US11959111
申请日：2007-12-18
申请人： Haowen Bu , Jerry Che-Jen Hu , Rajesh Khamankar
发明人： Haowen Bu , Jerry Che-Jen Hu , Rajesh Khamankar
IPC分类号： H01L29/94 , H01L21/31 , H01L21/8238 , H01L23/58
CPC分类号： H01L21/022 , C23C14/0652 , C23C16/56 , H01L21/02164 , H01L21/0217 , H01L21/02211 , H01L21/02274 , H01L21/3105 , H01L21/3185 , H01L21/76826 , H01L21/76832 , H01L21/76834 , H01L21/823807 , H01L29/665 , H01L29/7843
摘要： Integrated circuits (ICs) commonly contain pre-metal dielectric (PMD) liners with compressive stress to increase electron and hole mobilities in MOS transistors. The increase is limited by the thickness of the PMD liner. The instant invention is a multi-layered PMD liner in an integrated circuit which has a higher stress than single layer PMD liners. Each layer in the inventive PMD liner is exposed to a nitrogen-containing plasma, and which has a compressive stress higher than 1300 MPa. The PMD liner of the instant invention is composed of 3 to 10 layers. The hydrogen content of the first layer may be increased to improve transistor properties such as flicker noise and Negative Bias Temperature Instabilty (NBTI). An IC containing the inventive PMD liner and a method for forming same are also claimed.
摘要翻译：集成电路（IC）通常含有具有压应力的预金属电介质（PMD）衬垫，以增加MOS晶体管中的电子和空穴迁移率。该增加受到PMD衬套的厚度的限制。本发明是集成电路中的多层PMD衬垫，其具有比单层PMD衬垫更高的应力。将本发明的PMD衬垫中的每个层暴露于含氮等离子体，并且具有高于1300MPa的压缩应力。本发明的PMD衬垫由3〜10层构成。可以增加第一层的氢含量以改善诸如闪烁噪声和负偏压温度不稳定性（NBTI）的晶体管特性。还要求一种包含本发明的PMD衬垫的IC及其形成方法。

2. 发明授权

US08114784B2 Laminated stress overlayer using In-situ multiple plasma treatments for transistor improvement 有权
标题翻译：层压应力覆层使用原位多等离子体处理进行晶体管改良
公开(公告)号：US08114784B2
公开(公告)日：2012-02-14
申请号：US12904593
申请日：2010-10-14
申请人： Haowen Bu , Che-Jen Hu , Rajesh Khamankar
发明人： Haowen Bu , Che-Jen Hu , Rajesh Khamankar
IPC分类号： H01L21/31
CPC分类号： H01L21/3185 , C23C14/0652 , C23C16/56 , H01L21/3105 , H01L21/823807 , H01L29/665 , H01L29/7843
摘要： Integrated circuits (ICs) commonly contain pre-metal dielectric (PMD) liners with compressive stress to increase electron and hole mobilities in MOS transistors. The increase is limited by the thickness of the PMD liner. The instant invention is a multi-layered PMD liner in an integrated circuit which has a higher stress than single layer PMD liners. Each layer in the inventive PMD liner is exposed to a nitrogen-containing plasma, and which has a compressive stress higher than 1300 MPa. The PMD liner of the instant invention is composed of 3 to 10 layers. The hydrogen content of the first layer may be increased to improve transistor properties such as flicker noise and Negative Bias Temperature Instability (NBTI). An IC containing the inventive PMD liner and a method for forming same are also claimed.
摘要翻译：集成电路（IC）通常含有具有压应力的预金属电介质（PMD）衬垫，以增加MOS晶体管中的电子和空穴迁移率。该增加受到PMD衬套的厚度的限制。本发明是集成电路中的多层PMD衬垫，其具有比单层PMD衬垫更高的应力。将本发明的PMD衬垫中的每个层暴露于含氮等离子体，并且具有高于1300MPa的压缩应力。本发明的PMD衬垫由3〜10层构成。可以增加第一层的氢含量以改善诸如闪烁噪声和负偏压温度不稳定性（NBTI）的晶体管特性。还要求一种包含本发明的PMD衬垫的IC及其形成方法。

3. 发明申请

US20110027953A1 Laminated Stress Overlayer Using In-SITU Multiple Plasma Treatments for Transistor Improvement 有权
标题翻译：使用In-SITU多重等离子体处理晶体管改进的层压应力覆盖层
公开(公告)号：US20110027953A1
公开(公告)日：2011-02-03
申请号：US12904593
申请日：2010-10-14
申请人： Haowen Bu , Jerry Che-Jen Hu , Rajesh Khamankar
发明人： Haowen Bu , Jerry Che-Jen Hu , Rajesh Khamankar
IPC分类号： H01L21/8238
CPC分类号： H01L21/3185 , C23C14/0652 , C23C16/56 , H01L21/3105 , H01L21/823807 , H01L29/665 , H01L29/7843
摘要： Integrated circuits (ICs) commonly contain pre-metal dielectric (PMD) liners with compressive stress to increase electron and hole mobilities in MOS transistors. The increase is limited by the thickness of the PMD liner. The instant invention is a multi-layered PMD liner in an integrated circuit which has a higher stress than single layer PMD liners. Each layer in the inventive PMD liner is exposed to a nitrogen-containing plasma, and which has a compressive stress higher than 1300 MPa. The PMD liner of the instant invention is composed of 3 to 10 layers. The hydrogen content of the first layer may be increased to improve transistor properties such as flicker noise and Negative Bias Temperature Instability (NBTI). An IC containing the inventive PMD liner and a method for forming same are also claimed.
摘要翻译：集成电路（IC）通常包含具有压缩应力的预金属电介质（PMD）衬垫，以增加MOS晶体管中的电子和空穴迁移率。该增加受到PMD衬套的厚度的限制。本发明是集成电路中的多层PMD衬垫，其具有比单层PMD衬垫更高的应力。将本发明的PMD衬垫中的每个层暴露于含氮等离子体，并且具有高于1300MPa的压缩应力。本发明的PMD衬垫由3〜10层构成。可以增加第一层的氢含量以改善诸如闪烁噪声和负偏压温度不稳定性（NBTI）的晶体管特性。还要求一种包含本发明的PMD衬垫的IC及其形成方法。

4. 发明授权

US07601575B2 Integration of pre-S/D anneal selective nitride/oxide composite cap for improving transistor performance 有权
标题翻译：用于改善晶体管性能的前S / D退火选择性氮化物/氧化物复合帽的集成
公开(公告)号：US07601575B2
公开(公告)日：2009-10-13
申请号：US11072779
申请日：2005-03-04
申请人： Haowen Bu , Shashank Ekbote , Rajesh Khamankar , Shaoping Tang , Freidoon Mehrad
发明人： Haowen Bu , Shashank Ekbote , Rajesh Khamankar , Shaoping Tang , Freidoon Mehrad
IPC分类号： H01L21/336 , H01L21/8234 , H01L21/44
CPC分类号： H01L29/0847 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/7833 , H01L29/7845 , Y10S438/902
摘要： The present invention facilitates semiconductor device operation and fabrication by providing a cap-annealing process that improves channel electron mobility without substantially degrading PMOS transistor devices. The process uses an oxide/nitride composite cap to alter the active dopant profile across the channel regions. During an annealing process, dopants migrate out of the Si/SiO2 in a channel region thereby altering the dopant profile of the channel region. This altered profile generally improves channel mobility thereby improving transistor performance and permitting smaller density designs.
摘要翻译：本发明通过提供一种提高沟道电子迁移率而不会使PMOS晶体管器件基本上衰减的帽退火工艺来促进半导体器件的操作和制造。该方法使用氧化物/氮化物复合帽来改变通道区域上的活性掺杂剂分布。在退火过程中，掺杂剂在沟道区中迁移出Si / SiO 2，从而改变沟道区的掺杂物分布。这种改变的形状通常改善了沟道迁移率，从而提高了晶体管的性能并允许更小的密度设计。

5. 发明授权

US07192894B2 High performance CMOS transistors using PMD liner stress 有权
标题翻译：使用PMD衬垫应力的高性能CMOS晶体管
公开(公告)号：US07192894B2
公开(公告)日：2007-03-20
申请号：US10833419
申请日：2004-04-28
申请人： Haowen Bu , Rajesh Khamankar , Douglas T. Grider
发明人： Haowen Bu , Rajesh Khamankar , Douglas T. Grider
IPC分类号： H01L21/31
CPC分类号： H01L29/7842 , H01L29/665 , H01L29/6659 , H01L29/78 , H01L29/7843 , Y10S438/954
摘要： A silicon nitride layer (110) is formed over a transistor gate (40) and source and drain regions (70). The as-formed silicon nitride layer (110) comprises a first tensile stress and a high hydrogen concentration. The as-formed silicon nitride layer (110) is thermally annealed converting the first tensile stress into a second tensile stress that is larger than the first tensile stress. Following the thermal anneal, the hydrogen concentration in the silicon nitride layer (110) is greater than 12 atomic percent.
摘要翻译：氮化硅层（110）形成在晶体管栅极（40）和源极和漏极区域（70）之上。所形成的氮化硅层（110）包括第一拉伸应力和高氢浓度。将所形成的氮化硅层（110）进行热退火，将第一拉伸应力转换成大于第一拉伸应力的第二拉伸应力。在热退火之后，氮化硅层（110）中的氢浓度大于12原子％。

6. 发明申请

US20050059260A1 CMOS transistors and methods of forming same 审中-公开
标题翻译： CMOS晶体管及其形成方法
公开(公告)号：US20050059260A1
公开(公告)日：2005-03-17
申请号：US10810905
申请日：2004-03-26
申请人： Haowen Bu , Brian Hornung , P.R. Chidambaram , Amitabh Jain , Rajesh Khamankar , Nandu Mahalingam , Srinivansan Chakravarthi
发明人： Haowen Bu , Brian Hornung , P.R. Chidambaram , Amitabh Jain , Rajesh Khamankar , Nandu Mahalingam , Srinivansan Chakravarthi
IPC分类号： H01L21/00 , H01L21/265 , H01L21/3205 , H01L21/324 , H01L21/336 , H01L21/44 , H01L21/4763 , H01L21/8238 , H01L21/84 , H01L29/08 , H01L29/76 , H01L29/78
CPC分类号： H01L21/26506 , H01L21/265 , H01L21/26513 , H01L21/2658 , H01L21/3185 , H01L21/324 , H01L21/823814 , H01L21/823864 , H01L29/0847 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/7833 , H01L29/7843 , H01L29/7845
摘要： The present invention teaches the formation of CMOS transistors using interfacial nitrogen at the interface between the lightly doped extension regions and an overlying insulating layer in combination with a capping layer of silicon nitride, both prior to the final source/drain anneal. Doses and energies may be increased for the P-channel lightly-doped drain, source and drain regions. The resulting transistors exhibit desirably high drive current and low off-state leakage current and overlap capacitance.
摘要翻译：本发明教导了在最终的源极/漏极退火之前，在轻掺杂的延伸区域之间的界面处的界面氮和与氮化硅覆盖层结合的上覆绝缘层的CMOS晶体管的形成。 P沟道轻掺杂漏极，源极和漏极区域的剂量和能量可能会增加。所得到的晶体管显示期望的高驱动电流和低截止状态的漏电流和重叠电容。

7. 发明授权

US07670892B2 Nitrogen based implants for defect reduction in strained silicon 有权
标题翻译：用于应变硅缺陷还原的氮基植入物
公开(公告)号：US07670892B2
公开(公告)日：2010-03-02
申请号：US11268040
申请日：2005-11-07
申请人： Srinivasan Chakravarthi , Pr Chidambaram , Rajesh Khamankar , Haowen Bu , Douglas T. Grider
发明人： Srinivasan Chakravarthi , Pr Chidambaram , Rajesh Khamankar , Haowen Bu , Douglas T. Grider
IPC分类号： H01L21/336 , H01L21/8234
CPC分类号： H01L29/7833 , H01L21/26506 , H01L29/665 , H01L29/6659 , H01L29/7843
摘要： A transistor is fabricated upon a semiconductor substrate, where the yield strength or elasticity of the substrate is enhanced or otherwise adapted. A strain inducing layer is formed over the transistor to apply a strain thereto to alter transistor operating characteristics, and more particularly to enhance the mobility of carriers within the transistor. Enhancing carrier mobility allows transistor dimensions to be reduced while also allowing the transistor to operate as desired. However, high strain and temperature associated with fabricating the transistor result in deleterious plastic deformation. The yield strength of the silicon substrate is therefore adapted by incorporating nitrogen into the substrate, and more particularly into source/drain extension regions and/or source/drain regions of the transistor. The nitrogen can be readily incorporated during transistor fabrication by adding it as part of source/drain extension region formation and/or source/drain region formation. The enhanced yield strength of the substrate mitigates plastic deformation of the transistor due to the strain inducing layer.
摘要翻译：晶体管制造在半导体衬底上，其中衬底的屈服强度或弹性得到增强或适应。应变感应层形成在晶体管上以向其施加应变以改变晶体管工作特性，更具体地说，增强晶体管内的载流子迁移率。增强载流子迁移率允许晶体管尺寸减小，同时也允许晶体管根据需要进行操作。然而，与制造晶体管相关的高应变和温度导致有害的塑性变形。因此，硅衬底的屈服强度通过将氮掺入到衬底中，更具体地掺入晶体管的源极/漏极延伸区域和/或源极/漏极区域来适应。在晶体管制造期间，可以通过将其作为源极/漏极延伸区域形成和/或源极/漏极区域形成的一部分来添加来将氮容易地并入。由于应变诱导层，衬底的增强的屈服强度减轻了晶体管的塑性变形。

8. 发明申请

US20060154411A1 CMOS transistors and methods of forming same 审中-公开
标题翻译： CMOS晶体管及其形成方法
公开(公告)号：US20060154411A1
公开(公告)日：2006-07-13
申请号：US11372430
申请日：2006-03-09
申请人： Haowen Bu , Brian Hornung , P.R. Chidambaram , Amitabh Jain , Rajesh Khamankar , Nandu Mahalingam , Srinivansan Chakravarthi
发明人： Haowen Bu , Brian Hornung , P.R. Chidambaram , Amitabh Jain , Rajesh Khamankar , Nandu Mahalingam , Srinivansan Chakravarthi
IPC分类号： H01L21/338 , H01L21/31
CPC分类号： H01L21/26506 , H01L21/265 , H01L21/26513 , H01L21/2658 , H01L21/3185 , H01L21/324 , H01L21/823814 , H01L21/823864 , H01L29/0847 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/7833 , H01L29/7843 , H01L29/7845
摘要： The present invention teaches the formation of CMOS transistors using interfacial nitrogen at the interface between the lightly doped extension regions and an overlying insulating layer in combination with a capping layer of silicon nitride, both prior to the final source/drain anneal. Doses and energies may be increased for the P-channel lightly-doped drain, source and drain regions. The resulting transistors exhibit desirably high drive current and low off-state leakage current and overlap capacitance.
摘要翻译：本发明教导了在最终的源极/漏极退火之前，在轻掺杂的延伸区域之间的界面处的界面氮和与氮化硅覆盖层结合的上覆绝缘层的CMOS晶体管的形成。 P沟道轻掺杂漏极，源极和漏极区域的剂量和能量可能会增加。所得到的晶体管显示期望的高驱动电流和低截止状态的漏电流和重叠电容。

9. 发明授权

US06930007B2 Integration of pre-S/D anneal selective nitride/oxide composite cap for improving transistor performance 有权
标题翻译：用于改善晶体管性能的前S / D退火选择性氮化物/氧化物复合帽的集成
公开(公告)号：US06930007B2
公开(公告)日：2005-08-16
申请号：US10662850
申请日：2003-09-15
申请人： Haowen Bu , Shashank Ekbote , Rajesh Khamankar , Shaoping Tang , Freidoon Mehrad
发明人： Haowen Bu , Shashank Ekbote , Rajesh Khamankar , Shaoping Tang , Freidoon Mehrad
IPC分类号： H01L21/00 , H01L21/3205 , H01L21/336 , H01L21/44 , H01L21/4763 , H01L21/8238 , H01L21/84 , H01L29/08 , H01L29/76 , H01L29/78
CPC分类号： H01L29/0847 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/7833 , H01L29/7845 , Y10S438/902
摘要： The present invention facilitates semiconductor device operation and fabrication by providing a cap-annealing process that improves channel electron mobility without substantially degrading PMOS transistor devices. The process uses an oxide/nitride composite-cap to alter the active dopant profile across the channel regions. During an annealing process, dopants migrate out of the Si/SiO2 in a channel region thereby altering the dopant profile of the channel region. This altered profile generally improves channel mobility thereby improving transistor performance and permitting smaller density designs.
摘要翻译：本发明通过提供一种提高沟道电子迁移率而不会使PMOS晶体管器件基本上衰减的帽退火工艺来促进半导体器件的操作和制造。该方法使用氧化物/氮化物复合帽来改变通道区域上的活性掺杂剂分布。在退火过程中，掺杂剂在沟道区中迁移出Si / SiO 2，从而改变沟道区的掺杂物分布。这种改变的形状通常改善了沟道迁移率，从而提高了晶体管的性能并允许更小的密度设计。

10. 发明授权

US08809141B2 High performance CMOS transistors using PMD liner stress 有权
标题翻译：使用PMD衬垫应力的高性能CMOS晶体管
公开(公告)号：US08809141B2
公开(公告)日：2014-08-19
申请号：US11670192
申请日：2007-02-01
申请人： Haowen Bu , Rajesh Khamankar , Douglas T. Grider
发明人： Haowen Bu , Rajesh Khamankar , Douglas T. Grider
IPC分类号： H01L29/739
CPC分类号： H01L29/7842 , H01L29/665 , H01L29/6659 , H01L29/78 , H01L29/7843 , Y10S438/954
摘要： A silicon nitrate layer (110) is formed over a transistor gate (40) and source and drain regions (70). The as-formed silicon nitride layer (110) comprises a first tensile stress and a high hydrogen concentration. The as-formed silicon nitride layer (110) is thermally annealed converting the first tensile stress into a second tensile stress that is larger than the first tensile stress. Following the thermal anneal, the hydrogen concentration in the silicon nitride layer (110) is greater than 12 atomic percent.
摘要翻译：在晶体管栅极（40）和源极和漏极区域（70）之上形成硝酸氧化物层（110）。所形成的氮化硅层（110）包括第一拉伸应力和高氢浓度。将所形成的氮化硅层（110）进行热退火，将第一拉伸应力转换成大于第一拉伸应力的第二拉伸应力。在热退火之后，氮化硅层（110）中的氢浓度大于12原子％。

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