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11. 发明申请

US20130009277A1 STRUCTURE AND METHOD FOR FORMING ISOLATION AND BURIED PLATE FOR TRENCH CAPACITOR 有权
标题翻译：用于形成用于TRENCH电容器的隔离和平板的结构和方法
公开(公告)号：US20130009277A1
公开(公告)日：2013-01-10
申请号：US13617576
申请日：2012-09-14
申请人： Abhishek Dube , Subramanian S. Iyer , Babar Ali Khan , Oh-jung Kwon , Junedong Lee , Paul C. Parries , Chengwen Pei , Gerd Pfeiffer , Ravi M. Todi , Geng Wang
发明人： Abhishek Dube , Subramanian S. Iyer , Babar Ali Khan , Oh-jung Kwon , Junedong Lee , Paul C. Parries , Chengwen Pei , Gerd Pfeiffer , Ravi M. Todi , Geng Wang
IPC分类号： H01L29/06
CPC分类号： H01L29/945 , H01L21/76229 , H01L21/84 , H01L29/66181
摘要： A structure and method for forming isolation and a buried plate for a trench capacitor is disclosed. Embodiments of the structure comprise an epitaxial layer serving as the buried plate, and a bounded deep trench isolation area serving to isolate one or more deep trench structures. Embodiments of the method comprise angular implanting of the deep trench isolation area to form a P region at the base of the deep trench isolation area that serves as an anti-punch through implant.
摘要翻译：公开了用于形成隔离的结构和方法以及用于沟槽电容器的掩埋板。该结构的实施例包括用作掩埋板的外延层和用于隔离一个或多个深沟槽结构的有界深沟槽隔离区域。该方法的实施例包括深沟槽隔离区域的角度注入，以在用作抗穿孔植入物的深沟槽隔离区域的底部形成P区。

12. 发明授权

US5811935A Discharge lamp with T-shaped electrodes 失效
标题翻译：放电灯带T形电极
公开(公告)号：US5811935A
公开(公告)日：1998-09-22
申请号：US753546
申请日：1996-11-26
申请人： Ronald D. Pinker , Thomas F. McGee, III , David Alan Cammack , Babar Ali Khan
发明人： Ronald D. Pinker , Thomas F. McGee, III , David Alan Cammack , Babar Ali Khan
IPC分类号： H01J61/06 , H01J17/04
CPC分类号： H01J61/06
摘要： A discharge lamp includes a first and a second substrate (12, 14), a cavity disposed in the first substrate (12) or in a portion of the first and a second substrate (12, 14), a first and a second aligned electrode (270, 272) disposed between the first and a second substrate (12, 14) having respective ends extending into the cavity, wherein the first and the second aligned electrode (270, 272) are "T-shaped" when viewed in cross-section. The T-shaped electrodes provide mechanical support that minimizes bending and distortion in the horizontal and vertical directions. The discharge lamp may include a charge of mercury or an inert gas, and may further include a phosphor layer (80).
摘要翻译：放电灯包括第一和第二衬底（12,14），设置在第一衬底（12）中或在第一和第二衬底（12,14）的一部分中的空腔，第一和第二对齐电极（270,272），其设置在所述第一和第二基板（12,14）之间，所述第二基板（12,14）具有延伸到所述空腔中的相应端部，其中当横截面观察时，所述第一和第二对准电极（270,272）为“T” 部分。 T形电极提供了使水平和垂直方向上的弯曲和变形最小化的机械支撑。放电灯可以包括汞或惰性气体的电荷，并且还可以包括荧光体层（80）。

13. 发明授权

US5796209A Gas discharge lamps and lasers fabricated by michromachining 失效
标题翻译：气体放电灯和激光器通过重晶加工制造
公开(公告)号：US5796209A
公开(公告)日：1998-08-18
申请号：US484256
申请日：1994-10-27
申请人： Babar Ali Khan , David Alan Cammack , Ronald D. Pinker , Nikhil Ramesh Taskar
发明人： Babar Ali Khan , David Alan Cammack , Ronald D. Pinker , Nikhil Ramesh Taskar
IPC分类号： H01J9/24 , G02F1/13357 , H01J9/00 , H01J9/26 , H01J9/28 , H01J17/49 , H01J61/00 , H01J61/30 , H01J61/36 , H01J61/82 , H01J65/00 , H01J65/04 , H01S3/03 , H01S3/097 , H01S3/0973 , H01J1/62 , H01J9/12 , H01J17/16
CPC分类号： G02F1/133617 , H01J17/492 , H01J61/00 , H01J61/30 , H01J61/82 , H01J65/00 , H01J9/00 , H01J9/261 , H01S3/03 , H01S3/097 , H01S3/0973
摘要： A high pressure gas discharge lamp and the method of making same utilizing integrated circuit fabrication techniques. The lamp is manufactured from heat and pressure resistant planar substrates in which cavities are etched, by integrated circuit manufacturing techniques, so as to provide a cavity forming the gas discharge tube. Electrodes are deposited in the cavity. The cavity is filled with gas discharge materials such as mercury vapor, sodium vapor or metal halide. The substrates are bonded together and channels may be etched in the substrate so as to provide a means for connection to the electrodes. Electrodeless RF activated lamps may also be fabricated by this technique. Micro-lasers may also be fabricated by this technique as well.
摘要翻译：一种高压气体放电灯及其利用集成电路制造技术的方法。该灯由通过集成电路制造技术蚀刻空腔的耐热和耐压平面基板制造，以提供形成气体放电管的空腔。电极沉积在腔中。空腔填充有气体放电材料，例如汞蒸气，钠蒸气或金属卤化物。将基板粘合在一起，并且可以在基板中蚀刻通道，以便提供连接到电极的装置。也可以通过这种技术制造无电极RF激活灯。也可以通过该技术来制造微型激光器。

14. 发明申请

US20110193193A1 STRUCTURE AND METHOD FOR FORMING ISOLATION AND BURIED PLATE FOR TRENCH CAPACITOR 有权
标题翻译：用于形成用于TRENCH电容器的隔离和平板的结构和方法
公开(公告)号：US20110193193A1
公开(公告)日：2011-08-11
申请号：US12704084
申请日：2010-02-11
申请人： Abhishek Dube , Subramanian S. Iyer , Babar Ali Khan , Oh-jung Kwon , Junedong Lee , Paul C. Parries , Chengwen Pei , Gerd Pfeiffer , Ravi M. Todi , Geng Wang
发明人： Abhishek Dube , Subramanian S. Iyer , Babar Ali Khan , Oh-jung Kwon , Junedong Lee , Paul C. Parries , Chengwen Pei , Gerd Pfeiffer , Ravi M. Todi , Geng Wang
IPC分类号： H01L29/94 , H01L21/02
CPC分类号： H01L29/945 , H01L21/76229 , H01L21/84 , H01L29/66181
摘要： A structure and method for forming isolation and a buried plate for a trench capacitor is disclosed. Embodiments of the structure comprise an epitaxial layer serving as the buried plate, and a bounded deep trench isolation area serving to isolate one or more deep trench structures. Embodiments of the method comprise angular implanting of the deep trench isolation area to form a P region at the base of the deep trench isolation area that serves as an anti-punch through implant.
摘要翻译：公开了用于形成隔离的结构和方法以及用于沟槽电容器的掩埋板。该结构的实施例包括用作掩埋板的外延层和用于隔离一个或多个深沟槽结构的有界深沟槽隔离区域。该方法的实施例包括深沟槽隔离区域的角度注入，以在用作抗穿孔植入物的深沟槽隔离区域的底部形成P区。

15. 发明授权

US06727540B2 Structure and method of fabricating embedded DRAM having a vertical device array and a bordered bitline contact 有权
标题翻译：制造具有垂直器件阵列和边界位线接触的嵌入式DRAM的结构和方法
公开(公告)号：US06727540B2
公开(公告)日：2004-04-27
申请号：US10227404
申请日：2002-08-23
申请人： Ramachandra Divakaruni , Babar Ali Khan , Carl John Radens
发明人： Ramachandra Divakaruni , Babar Ali Khan , Carl John Radens
IPC分类号： H01L27108
CPC分类号： H01L27/10891 , H01L27/0207 , H01L27/10864
摘要： An integrated circuit including a dynamic random access memory (DRAM) array is disclosed herein in which a DRAM cell includes a storage capacitor within a deep trench, a transistor having a channel extending along a sidewall of the deep trench and a gate conductor within the deep trench, and a wordline contacting the gate conductor from above, wherein the wordline has a centerline which is offset from the centerline of the gate conductor. The DRAM cell further includes active area extending from the transistor channel, and a bitline contact to the active area which is bordered by an insulating spacer of the sidewall of the wordline.
摘要翻译：本文公开了一种包括动态随机存取存储器（DRAM）阵列的集成电路，其中DRAM单元在深沟槽内包括存储电容器，具有沿着深沟槽的侧壁延伸的沟道的晶体管和深沟槽内的栅极导体沟槽和从上方接触栅极导体的字线，其中字线具有偏离栅极导体的中心线的中心线。 DRAM单元进一步包括从晶体管沟道延伸的有源区和与由字线的侧壁的绝缘间隔物界定的有源区的位线接触。

16. 发明授权

US08637958B2 Structure and method for forming isolation and buried plate for trench capacitor 有权
标题翻译：用于形成沟槽电容器的隔离和掩埋板的结构和方法
公开(公告)号：US08637958B2
公开(公告)日：2014-01-28
申请号：US13617576
申请日：2012-09-14
申请人： Abhishek Dube , Subramanian S. Iyer , Babar Ali Khan , Oh-jung Kwon , Junedong Lee , Paul C. Parries , Chengwen Pei , Gerd Pfeiffer , Ravi Todi , Geng Wang
发明人： Abhishek Dube , Subramanian S. Iyer , Babar Ali Khan , Oh-jung Kwon , Junedong Lee , Paul C. Parries , Chengwen Pei , Gerd Pfeiffer , Ravi Todi , Geng Wang
IPC分类号： H01L21/02
CPC分类号： H01L29/945 , H01L21/76229 , H01L21/84 , H01L29/66181
摘要： A structure and method for forming isolation and a buried plate for a trench capacitor is disclosed. Embodiments of the structure comprise an epitaxial layer serving as the buried plate, and a bounded deep trench isolation area serving to isolate one or more deep trench structures. Embodiments of the method comprise angular implanting of the deep trench isolation area to form a P region at the base of the deep trench isolation area that serves as an anti-punch through implant.
摘要翻译：公开了用于形成隔离的结构和方法以及用于沟槽电容器的掩埋板。该结构的实施例包括用作掩埋板的外延层和用于隔离一个或多个深沟槽结构的有界深沟槽隔离区。该方法的实施例包括深沟槽隔离区域的角度注入，以在用作抗穿孔植入物的深沟槽隔离区域的底部形成P区。

17. 发明申请

US20090267179A1 SYSTEM FOR POWER PERFORMANCE OPTIMIZATION OF MULTICORE PROCESSOR CHIP 审中-公开
标题翻译：多处理器芯片的功率性能优化系统
公开(公告)号：US20090267179A1
公开(公告)日：2009-10-29
申请号：US12108905
申请日：2008-04-24
申请人： Subramanian S. Iyer , Babar Ali Khan , Chandrasekharan Kothandaraman , Norman Whitelaw Robson
发明人： Subramanian S. Iyer , Babar Ali Khan , Chandrasekharan Kothandaraman , Norman Whitelaw Robson
IPC分类号： H01L23/525
CPC分类号： H01L23/5256 , H01L23/5286 , H01L2924/0002 , H01L2924/00
摘要： A system in one embodiment includes a multiprocessor chip comprising a plurality of cores; a plurality of power circuits, each power circuit being coupled to one of the cores; and an electrically programmable fuse in each power circuit. Each electrically programmable fuse further comprises a first electrode coupled to the associated power circuit; a second electrode coupled to the associated power circuit; a first pad coupled to the first electrode; a second pad coupled to the second electrode; and an electrically conductive material extending between the first and second electrodes and forming part of the associated power circuit, the electrically conductive material being characterized as tending to electromigrate from one of the electrodes to the other electrode under an applied electrical current passing between the electrodes, wherein the electromigration increases an overall resistance of the power circuit.
摘要翻译：一个实施例中的系统包括包括多个核心的多处理器芯片; 多个电源电路，每个电源电路耦合到一个核心; 和每个电源电路中的电可编程保险丝。每个电可编程保险丝还包括耦合到相关联的电力电路的第一电极; 耦合到相关联的电力电路的第二电极; 耦合到所述第一电极的第一焊盘; 耦合到所述第二电极的第二焊盘; 以及导电材料，其在所述第一和第二电极之间延伸并形成所述相关联的电力电路的一部分，所述导电材料的特征在于，在通过所述电极之间的施加的电流下，倾向于从所述电极之一电极转移到所述另一个电极，其中电迁移增加了电源电路的整体电阻。

18. 发明授权

US5955838A Gas discharge lamps and lasers fabricated by micromachining methodology 失效
标题翻译：气体放电灯和激光器通过微加工方法制造
公开(公告)号：US5955838A
公开(公告)日：1999-09-21
申请号：US856836
申请日：1997-05-15
申请人： Babar Ali Khan , David A. Cammack , Ronald D. Pinker
发明人： Babar Ali Khan , David A. Cammack , Ronald D. Pinker
IPC分类号： G02F1/13357 , H01J9/26 , H01J61/00 , H01J61/30 , H01J61/82 , H01J65/00 , H01S3/03 , H01S3/097 , H01S3/0973 , H01J17/16
CPC分类号： H01J9/261 , G02F1/133617 , H01J17/492 , H01J61/00 , H01J61/30 , H01J61/82 , H01J65/00 , H01J9/00 , H01S3/03 , H01S3/097 , H01S3/0973
摘要： A high pressure gas discharge lamp and the method of making same utilizing integrated circuit fabrication techniques. The lamp is manufactured from heat and pressure resistant planar substrates in which cavities are etched, by integrated circuit manufacturing techniques, so as to provide a cavity forming the gas discharge tube. Electrodes are deposited in the cavity. The cavity is filled with gas discharge materials such as mercury vapor, sodium vapor or metal halide. The substrates are bonded together and channels may be etched in the substrate so as to provide a means for connection to the electrodes. Electrodeless RF activated lamps may also be fabricated by this technique. Lamps fabricated from three or more planar substrates are disclosed.
摘要翻译：一种高压气体放电灯及其利用集成电路制造技术的方法。该灯由通过集成电路制造技术蚀刻空腔的耐热和耐压平面基板制造，以提供形成气体放电管的空腔。电极沉积在腔中。空腔填充有气体放电材料，例如汞蒸气，钠蒸气或金属卤化物。将基板粘合在一起，并且可以在基板中蚀刻通道，以便提供连接到电极的装置。也可以通过这种技术制造无电极RF激活灯。公开了由三个或更多个平面基板制造的灯。

19. 发明授权

US08298908B2 Structure and method for forming isolation and buried plate for trench capacitor 有权
标题翻译：用于形成沟槽电容器的隔离和掩埋板的结构和方法
公开(公告)号：US08298908B2
公开(公告)日：2012-10-30
申请号：US12704084
申请日：2010-02-11
申请人： Abhishek Dube , Subramanian S. Iyer , Babar Ali Khan , Oh-jung Kwon , Junedong Lee , Paul C. Parries , Chengwen Pei , Gerd Pfeiffer , Ravi M. Todi , Geng Wang
发明人： Abhishek Dube , Subramanian S. Iyer , Babar Ali Khan , Oh-jung Kwon , Junedong Lee , Paul C. Parries , Chengwen Pei , Gerd Pfeiffer , Ravi M. Todi , Geng Wang
IPC分类号： H01L21/20
CPC分类号： H01L29/945 , H01L21/76229 , H01L21/84 , H01L29/66181
摘要： A structure and method for forming isolation and a buried plate for a trench capacitor is disclosed. Embodiments of the structure comprise an epitaxial layer serving as the buried plate, and a bounded deep trench isolation area serving to isolate one or more deep trench structures. Embodiments of the method comprise angular implanting of the deep trench isolation area to form a P region at the base of the deep trench isolation area that serves as an anti-punch through implant.
摘要翻译：公开了用于形成隔离的结构和方法以及用于沟槽电容器的掩埋板。该结构的实施例包括用作掩埋板的外延层和用于隔离一个或多个深沟槽结构的有界深沟槽隔离区域。该方法的实施例包括深沟槽隔离区域的角度注入，以在用作抗穿孔植入物的深沟槽隔离区域的底部形成P区。

20. 发明授权

US07294543B2 DRAM (Dynamic Random Access Memory) cells 失效
标题翻译： DRAM（动态随机存取存储器）单元
公开(公告)号：US07294543B2
公开(公告)日：2007-11-13
申请号：US11308404
申请日：2006-03-22
申请人： Kangguo Cheng , Babar Ali Khan
发明人： Kangguo Cheng , Babar Ali Khan
IPC分类号： H01L21/8242
CPC分类号： H01L27/1087
摘要： A DRAM cell with a self-aligned gradient P-well and a method for forming the same. The DRAM cell includes (a) a semiconductor substrate; (b) an electrically conducting region including a first portion, a second portion, and a third portion; (c) a first doped semiconductor region wrapping around the first portion, but electrically insulated from the first portion by a capacitor dielectric layer; (d) a second doped semiconductor region wrapping around the second portion, but electrically insulated from the second portion by a collar dielectric layer. The second portion is on top of and electrically coupled to the first portion, and the third portion is on top of and electrically coupled to the second portion. The collar dielectric layer is in direct physical contact with the capacitor dielectric layer. When going away from the collar dielectric layer, a doping concentration of the second doped semiconductor region decreases.
摘要翻译：具有自对准梯度P阱的DRAM单元及其形成方法。 DRAM单元包括（a）半导体衬底; （b）包括第一部分，第二部分和第三部分的导电区域; （c）围绕所述第一部分包围但与所述第一部分由电容器介电层电绝缘的第一掺杂半导体区域; （d）围绕第二部分缠绕的第二掺杂半导体区域，但是通过套环电介质层与第二部分电绝缘。第二部分在第一部分的顶部并且电耦合到第一部分，并且第三部分在第二部分的顶部并且电耦合到第二部分。套环电介质层与电容器电介质层直接物理接触。当离开套环电介质层时，第二掺杂半导体区域的掺杂浓度降低。

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